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DS18B20.map.rpt
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VHDL/FPGA/Verilog
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- Analysis & Synthesis report for DS18B20
- Sat Mar 13 15:06:15 2010
- Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Analysis & Synthesis Source Files Read
- 5. Analysis & Synthesis Resource Usage Summary
- 6. Analysis & Synthesis Resource Utilization by Entity
- 7. User-Specified and Inferred Latches
- 8. General Register Statistics
- 9. Multiplexer Restructuring Statistics (Restructuring Performed)
- 10. Parameter Settings for Inferred Entity Instance: DS18B20VHDL:inst4|lpm_divide:Div0
- 11. Parameter Settings for Inferred Entity Instance: DS18B20VHDL:inst4|lpm_divide:Mod0
- 12. Analysis & Synthesis Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2008 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +-----------------------------+------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Sat Mar 13 15:06:15 2010 ;
- ; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
- ; Revision Name ; DS18B20 ;
- ; Top-level Entity Name ; DS18B20 ;
- ; Family ; MAX II ;
- ; Total logic elements ; 295 ;
- ; Total pins ; 24 ;
- ; Total virtual pins ; 0 ;
- ; Total memory bits ; 0 ;
- ; DSP block 9-bit elements ; 0 ;
- ; Total PLLs ; 0 ;
- ; Total DLLs ; 0 ;
- +-----------------------------+------------------------------------------+
- +--------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +--------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +--------------------------------------------------------------+--------------------+--------------------+
- ; Device ; EPM570T100C5 ; ;
- ; Top-level entity name ; DS18B20 ; DS18B20 ;
- ; Family name ; MAX II ; Stratix ;
- ; Use smart compilation ; Off ; Off ;
- ; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL93 ; VHDL93 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Safe State Machine ; Off ; Off ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
- ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Parallel Synthesis ; Off ; Off ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique ; Balanced ; Balanced ;
- ; Carry Chain Length ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto Open-Drain Pins ; On ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
- ; Perform gate-level register retiming ; Off ; Off ;
- ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
- ; Auto Shift Register Replacement ; Auto ; Auto ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Synchronization Register Chain Length ; 2 ; 2 ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; HDL message level ; Level2 ; Level2 ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Clock MUX Protection ; On ; On ;
- ; Block Design Naming ; Auto ; Auto ;
- ; Synthesis Effort ; Auto ; Auto ;
- ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
- +--------------------------------------------------------------+--------------------+--------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
- +----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------+
- ; DS18B20.bdf ; yes ; User Block Diagram/Schematic File ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/DS18B20.bdf ;
- ; DS18B20VHDL.vhd ; yes ; User VHDL File ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/DS18B20VHDL.vhd ;
- ; Frequency.vhd ; yes ; Other ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/Frequency.vhd ;
- ; LED4.vhd ; yes ; Other ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/LED4.vhd ;
- ; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/lpm_divide.tdf ;
- ; abs_divider.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/abs_divider.inc ;
- ; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/sign_div_unsign.inc ;
- ; aglobal80.inc ; yes ; Megafunction ; c:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ;
- ; db/lpm_divide_qvl.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/lpm_divide_qvl.tdf ;
- ; db/sign_div_unsign_bkh.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/sign_div_unsign_bkh.tdf ;
- ; db/alt_u_div_hie.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/alt_u_div_hie.tdf ;
- ; db/add_sub_e7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_e7c.tdf ;
- ; db/add_sub_f7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_f7c.tdf ;
- ; db/add_sub_g7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_g7c.tdf ;
- ; db/add_sub_h7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_h7c.tdf ;
- ; db/add_sub_i7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_i7c.tdf ;
- ; db/lpm_divide_1ol.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/lpm_divide_1ol.tdf ;
- ; db/sign_div_unsign_fkh.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/sign_div_unsign_fkh.tdf ;
- ; db/alt_u_div_pie.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/alt_u_div_pie.tdf ;
- ; db/add_sub_j7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_j7c.tdf ;
- ; db/add_sub_k7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_k7c.tdf ;
- ; db/add_sub_l7c.tdf ; yes ; Auto-Generated Megafunction ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/db/add_sub_l7c.tdf ;
- +----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------+
- +-----------------------------------------------------+
- ; Analysis & Synthesis Resource Usage Summary ;
- +---------------------------------------------+-------+
- ; Resource ; Usage ;
- +---------------------------------------------+-------+
- ; Total logic elements ; 295 ;
- ; -- Combinational with no register ; 235 ;
- ; -- Register only ; 8 ;
- ; -- Combinational with a register ; 52 ;
- ; ; ;
- ; Logic element usage by number of LUT inputs ; ;
- ; -- 4 input functions ; 75 ;
- ; -- 3 input functions ; 49 ;
- ; -- 2 input functions ; 123 ;
- ; -- 1 input functions ; 40 ;
- ; -- 0 input functions ; 0 ;
- ; ; ;
- ; Logic elements by mode ; ;
- ; -- normal mode ; 216 ;
- ; -- arithmetic mode ; 79 ;
- ; -- qfbk mode ; 0 ;
- ; -- register cascade mode ; 0 ;
- ; -- synchronous clear/load mode ; 5 ;
- ; -- asynchronous clear/load mode ; 30 ;
- ; ; ;
- ; Total registers ; 60 ;
- ; Total logic cells in carry chains ; 102 ;
- ; I/O pins ; 24 ;
- ; Maximum fan-out node ; RESET ;
- ; Maximum fan-out ; 31 ;
- ; Total fan-out ; 857 ;
- ; Average fan-out ; 2.69 ;
- +---------------------------------------------+-------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Utilization by Entity ;
- +-------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
- ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
- +-------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
- ; |DS18B20 ; 295 (0) ; 60 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 ; 0 ; 235 (0) ; 8 (0) ; 52 (0) ; 102 (0) ; 0 (0) ; |DS18B20 ; work ;
- ; |DS18B20VHDL:inst4| ; 214 (85) ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 184 (55) ; 4 (4) ; 26 (26) ; 82 (15) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4 ; work ;
- ; |lpm_divide:Div0| ; 53 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (0) ; 0 (0) ; 0 (0) ; 27 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0 ; work ;
- ; |lpm_divide_qvl:auto_generated| ; 53 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (0) ; 0 (0) ; 0 (0) ; 27 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated ; work ;
- ; |sign_div_unsign_bkh:divider| ; 53 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (0) ; 0 (0) ; 0 (0) ; 27 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_bkh:divider ; work ;
- ; |alt_u_div_hie:divider| ; 53 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (26) ; 0 (0) ; 0 (0) ; 27 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_hie:divider ; work ;
- ; |add_sub_h7c:add_sub_3| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_hie:divider|add_sub_h7c:add_sub_3 ; work ;
- ; |add_sub_i7c:add_sub_4| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_hie:divider|add_sub_i7c:add_sub_4 ; work ;
- ; |add_sub_i7c:add_sub_5| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_hie:divider|add_sub_i7c:add_sub_5 ; work ;
- ; |add_sub_i7c:add_sub_6| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_bkh:divider|alt_u_div_hie:divider|add_sub_i7c:add_sub_6 ; work ;
- ; |lpm_divide:Mod0| ; 76 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 76 (0) ; 0 (0) ; 0 (0) ; 40 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0 ; work ;
- ; |lpm_divide_1ol:auto_generated| ; 76 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 76 (0) ; 0 (0) ; 0 (0) ; 40 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated ; work ;
- ; |sign_div_unsign_fkh:divider| ; 76 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 76 (0) ; 0 (0) ; 0 (0) ; 40 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider ; work ;
- ; |alt_u_div_pie:divider| ; 76 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 76 (36) ; 0 (0) ; 0 (0) ; 40 (0) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_pie:divider ; work ;
- ; |add_sub_h7c:add_sub_3| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_pie:divider|add_sub_h7c:add_sub_3 ; work ;
- ; |add_sub_i7c:add_sub_4| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_pie:divider|add_sub_i7c:add_sub_4 ; work ;
- ; |add_sub_j7c:add_sub_5| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_pie:divider|add_sub_j7c:add_sub_5 ; work ;
- ; |add_sub_k7c:add_sub_6| ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 0 (0) ; 9 (9) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_pie:divider|add_sub_k7c:add_sub_6 ; work ;
- ; |add_sub_l7c:add_sub_7| ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; 10 (10) ; 0 (0) ; |DS18B20|DS18B20VHDL:inst4|lpm_divide:Mod0|lpm_divide_1ol:auto_generated|sign_div_unsign_fkh:divider|alt_u_div_pie:divider|add_sub_l7c:add_sub_7 ; work ;
- ; |Frequency:inst| ; 57 (57) ; 28 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 4 (4) ; 24 (24) ; 20 (20) ; 0 (0) ; |DS18B20|Frequency:inst ; work ;
- ; |LED4:inst2| ; 24 (24) ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |DS18B20|LED4:inst2 ; work ;
- +-------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +---------------------------------------------------------------------------------------------------+
- ; User-Specified and Inferred Latches ;
- +----------------------------------------------------+---------------------+------------------------+
- ; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
- +----------------------------------------------------+---------------------+------------------------+
- ; DS18B20VHDL:inst4|EOCtemp ; RESET ; yes ;
- ; Number of user-specified and inferred latches = 1 ; ; ;
- +----------------------------------------------------+---------------------+------------------------+
- Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
- +------------------------------------------------------+
- ; General Register Statistics ;
- +----------------------------------------------+-------+
- ; Statistic ; Value ;
- +----------------------------------------------+-------+
- ; Total registers ; 60 ;
- ; Number of registers using Synchronous Clear ; 5 ;
- ; Number of registers using Synchronous Load ; 0 ;
- ; Number of registers using Asynchronous Clear ; 30 ;
- ; Number of registers using Asynchronous Load ; 0 ;
- ; Number of registers using Clock Enable ; 0 ;
- ; Number of registers using Preset ; 0 ;
- +----------------------------------------------+-------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Multiplexer Restructuring Statistics (Restructuring Performed) ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
- ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
- ; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |DS18B20|DS18B20VHDL:inst4|Count[3] ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
- +------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: DS18B20VHDL:inst4|lpm_divide:Div0 ;
- +------------------------+----------------+------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------+----------------+------------------------------------------+
- ; LPM_WIDTHN ; 8 ; Untyped ;
- ; LPM_WIDTHD ; 4 ; Untyped ;
- ; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_PIPELINE ; 0 ; Untyped ;
- ; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
- ; MAXIMIZE_SPEED ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; lpm_divide_qvl ; Untyped ;
- ; CARRY_CHAIN ; MANUAL ; Untyped ;
- ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- +------------------------+----------------+------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: DS18B20VHDL:inst4|lpm_divide:Mod0 ;
- +------------------------+----------------+------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------+----------------+------------------------------------------+
- ; LPM_WIDTHN ; 8 ; Untyped ;
- ; LPM_WIDTHD ; 8 ; Untyped ;
- ; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_PIPELINE ; 0 ; Untyped ;
- ; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
- ; MAXIMIZE_SPEED ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; lpm_divide_1ol ; Untyped ;
- ; CARRY_CHAIN ; MANUAL ; Untyped ;
- ; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- +------------------------+----------------+------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Analysis & Synthesis
- Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
- Info: Processing started: Sat Mar 13 15:06:09 2010
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DS18B20 -c DS18B20
- Info: Found 1 design units, including 1 entities, in source file DS18B20.bdf
- Info: Found entity 1: DS18B20
- Info: Found 2 design units, including 1 entities, in source file DS18B20VHDL.vhd
- Info: Found design unit 1: DS18B20VHDL-DS18B20VHDL_arch
- Info: Found entity 1: DS18B20VHDL
- Info: Elaborating entity "DS18B20" for the top level hierarchy
- Info: Elaborating entity "DS18B20VHDL" for hierarchy "DS18B20VHDL:inst4"
- Warning (10631): VHDL Process Statement warning at DS18B20VHDL.vhd(203): inferring latch(es) for signal or variable "EOCtemp", which holds its previous value in one or more paths through the process
- Warning (10492): VHDL Process Statement warning at DS18B20VHDL.vhd(243): signal "DATA" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Info (10041): Inferred latch for "EOCtemp" at DS18B20VHDL.vhd(203)
- Warning: Using design file Frequency.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
- Info: Found design unit 1: Frequency-Frequency_arch
- Info: Found entity 1: Frequency
- Info: Elaborating entity "Frequency" for hierarchy "Frequency:inst"
- Warning (10036): Verilog HDL or VHDL warning at Frequency.vhd(39): object "Period1S" assigned a value but never read
- Warning: Using design file LED4.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
- Info: Found design unit 1: LED4-LED4_arch
- Info: Found entity 1: LED4
- Info: Elaborating entity "LED4" for hierarchy "LED4:inst2"
- Info: Inferred 2 megafunctions from design logic
- Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "DS18B20VHDL:inst4|Div0"
- Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "DS18B20VHDL:inst4|Mod0"
- Info: Elaborated megafunction instantiation "DS18B20VHDL:inst4|lpm_divide:Div0"
- Info: Instantiated megafunction "DS18B20VHDL:inst4|lpm_divide:Div0" with the following parameter:
- Info: Parameter "LPM_WIDTHN" = "8"
- Info: Parameter "LPM_WIDTHD" = "4"
- Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
- Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
- Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_qvl.tdf
- Info: Found entity 1: lpm_divide_qvl
- Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf
- Info: Found entity 1: sign_div_unsign_bkh
- Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_hie.tdf
- Info: Found entity 1: alt_u_div_hie
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_e7c.tdf
- Info: Found entity 1: add_sub_e7c
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_f7c.tdf
- Info: Found entity 1: add_sub_f7c
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_g7c.tdf
- Info: Found entity 1: add_sub_g7c
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_h7c.tdf
- Info: Found entity 1: add_sub_h7c
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_i7c.tdf
- Info: Found entity 1: add_sub_i7c
- Info: Elaborated megafunction instantiation "DS18B20VHDL:inst4|lpm_divide:Mod0"
- Info: Instantiated megafunction "DS18B20VHDL:inst4|lpm_divide:Mod0" with the following parameter:
- Info: Parameter "LPM_WIDTHN" = "8"
- Info: Parameter "LPM_WIDTHD" = "8"
- Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
- Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
- Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_1ol.tdf
- Info: Found entity 1: lpm_divide_1ol
- Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_fkh.tdf
- Info: Found entity 1: sign_div_unsign_fkh
- Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_pie.tdf
- Info: Found entity 1: alt_u_div_pie
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_j7c.tdf
- Info: Found entity 1: add_sub_j7c
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_k7c.tdf
- Info: Found entity 1: add_sub_k7c
- Info: Found 1 design units, including 1 entities, in source file db/add_sub_l7c.tdf
- Info: Found entity 1: add_sub_l7c
- Warning: Design contains 1 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "GCLKP2"
- Info: Implemented 319 device resources after synthesis - the final resource count might be different
- Info: Implemented 3 input pins
- Info: Implemented 20 output pins
- Info: Implemented 1 bidirectional pins
- Info: Implemented 295 logic cells
- Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
- Info: Peak virtual memory: 211 megabytes
- Info: Processing ended: Sat Mar 13 15:06:15 2010
- Info: Elapsed time: 00:00:06
- Info: Total CPU time (on all processors): 00:00:05
