DS18B20.tmw_info
上传用户:whms_168
上传日期:2022-08-09
资源大小:592k
文件大小:0k
源码类别:

VHDL/FPGA/Verilog

开发平台:

Others

  1. start_full_compilation:s:00:00:22
  2. start_analysis_synthesis:s:00:00:08