sign_div_unsign_qhg.tdf
资源名称:DS18B20.rar [点击查看]
上传用户:whms_168
上传日期:2022-08-09
资源大小:592k
文件大小:2k
源码类别:
VHDL/FPGA/Verilog
开发平台:
Others
- --sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=8 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=8 denominator numerator quotient remainder
- --VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_abs 2005:08:17:17:24:32:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_divide 2005:03:24:20:40:32:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ VERSION_END
- -- Copyright (C) 1991-2005 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Altera Program License
- -- Subscription Agreement, Altera MegaCore Function License
- -- Agreement, or other applicable license agreement, including,
- -- without limitation, that your use is for the sole purpose of
- -- programming logic devices manufactured by Altera and sold by
- -- Altera or its authorized distributors. Please refer to the
- -- applicable agreement for further details.
- FUNCTION alt_u_div_4gd (denominator[7..0], numerator[7..0])
- RETURNS ( den_out[7..0], quotient[7..0], remainder[7..0]);
- FUNCTION add_sub_558 (cin, dataa[7..0], datab[7..0])
- RETURNS ( result[7..0]);
- --synthesis_resources = lut 42
- SUBDESIGN sign_div_unsign_qhg
- (
- denominator[7..0] : input;
- numerator[7..0] : input;
- quotient[7..0] : output;
- remainder[7..0] : output;
- )
- VARIABLE
- divider : alt_u_div_4gd;
- adder : add_sub_558;
- gnd_wire : WIRE;
- norm_num[7..0] : WIRE;
- protect_quotient[7..0] : WIRE;
- protect_remainder[7..0] : WIRE;
- BEGIN
- divider.denominator[] = denominator[];
- divider.numerator[] = norm_num[];
- adder.cin = gnd_wire;
- adder.dataa[] = denominator[];
- adder.datab[] = protect_remainder[];
- gnd_wire = B"0";
- norm_num[] = numerator[];
- protect_quotient[] = divider.quotient[];
- protect_remainder[] = divider.remainder[];
- quotient[] = protect_quotient[];
- remainder[] = protect_remainder[];
- END;
- --VALID FILE