DS18B20.map.summary
资源名称:DS18B20.rar [点击查看]
上传用户:whms_168
上传日期:2022-08-09
资源大小:592k
文件大小:0k
源码类别:
VHDL/FPGA/Verilog
开发平台:
Others
- Analysis & Synthesis Status : Successful - Sat Mar 13 15:06:15 2010
- Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
- Revision Name : DS18B20
- Top-level Entity Name : DS18B20
- Family : MAX II
- Total logic elements : 295
- Total pins : 24
- Total virtual pins : 0
- Total memory bits : 0
- DSP block 9-bit elements : 0
- Total PLLs : 0
- Total DLLs : 0