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DS18B20.asm.rpt
资源名称：DS18B20.rar [点击查看]
上传用户：whms_168
上传日期：2022-08-09
资源大小：592k
文件大小：7k
源码类别：
VHDL/FPGA/Verilog
开发平台：
Others
- Assembler report for DS18B20
- Sat Mar 13 15:06:26 2010
- Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/DS18B20.pof
- 6. Assembler Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2008 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +---------------------------------------------------------------+
- ; Assembler Summary ;
- +-----------------------+---------------------------------------+
- ; Assembler Status ; Successful - Sat Mar 13 15:06:26 2010 ;
- ; Revision Name ; DS18B20 ;
- ; Top-level Entity Name ; DS18B20 ;
- ; Family ; MAX II ;
- ; Device ; EPM570T100C5 ;
- +-----------------------+---------------------------------------+
- +---------------------------------------------------------------------------------------------------------+
- ; Assembler Settings ;
- +-----------------------------------------------------------------------------+-----------+---------------+
- ; Option ; Setting ; Default Value ;
- +-----------------------------------------------------------------------------+-----------+---------------+
- ; Use smart compilation ; Off ; Off ;
- ; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
- ; Compression mode ; Off ; Off ;
- ; Clock source for configuration device ; Internal ; Internal ;
- ; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
- ; Divide clock frequency by ; 1 ; 1 ;
- ; Auto user code ; Off ; Off ;
- ; Security bit ; Off ; Off ;
- ; Use configuration device ; On ; On ;
- ; Configuration device ; Auto ; Auto ;
- ; Configuration device auto user code ; Off ; Off ;
- ; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
- ; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
- ; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
- ; Hexadecimal Output File start address ; 0 ; 0 ;
- ; Hexadecimal Output File count direction ; Up ; Up ;
- ; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
- ; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
- ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
- ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
- ; In-System Programming Default Clamp State ; Tri-state ; Tri-state ;
- +-----------------------------------------------------------------------------+-----------+---------------+
- +------------------------------------------------------------------------------------------------------+
- ; Assembler Generated Files ;
- +------------------------------------------------------------------------------------------------------+
- ; File Name ;
- +------------------------------------------------------------------------------------------------------+
- ; D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/DS18B20.pof ;
- +------------------------------------------------------------------------------------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------+
- ; Assembler Device Options: D:/ICDev_CPLD开发板资料/cpld/Code Example/MAX_II_EPM570/EPM570_VHDL/Quartus_V8.0/DS18B20/DS18B20.pof ;
- +----------------+---------------------------------------------------------------------------------------------------------------+
- ; Option ; Setting ;
- +----------------+---------------------------------------------------------------------------------------------------------------+
- ; Device ; EPM570T100C5 ;
- ; JTAG usercode ; 0xFFFFFFFF ;
- ; Checksum ; 0x003124D4 ;
- +----------------+---------------------------------------------------------------------------------------------------------------+
- +--------------------+
- ; Assembler Messages ;
- +--------------------+
- Info: *******************************************************************
- Info: Running Quartus II Assembler
- Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
- Info: Processing started: Sat Mar 13 15:06:24 2010
- Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DS18B20 -c DS18B20
- Info: Writing out detailed assembly data for power analysis
- Info: Assembler is generating device programming files
- Info: Quartus II Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 166 megabytes
- Info: Processing ended: Sat Mar 13 15:06:26 2010
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:01
