English
Light.tan.rpt
资源名称：LED8.rar [点击查看]
上传用户：sunkay99
上传日期：2022-08-09
资源大小：204k
文件大小：70k
源码类别：
VHDL/FPGA/Verilog
开发平台：
Others
- Classic Timing Analyzer report for Light
- Thu Jun 11 23:37:37 2009
- Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Timing Analyzer Settings
- 4. Clock Settings Summary
- 5. Clock Setup: 'GCLKP1'
- 6. Clock Hold: 'GCLKP1'
- 7. tco
- 8. Timing Analyzer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2008 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Summary ;
- +------------------------------+------------------------------------------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
- ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
- +------------------------------+------------------------------------------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
- ; Worst-case tco ; N/A ; None ; 31.417 ns ; light[4]~reg0 ; light[4] ; GCLKP1 ; -- ; 0 ;
- ; Clock Setup: 'GCLKP1' ; N/A ; None ; 118.58 MHz ( period = 8.433 ns ) ; Count1[0] ; Count1[9] ; GCLKP1 ; GCLKP1 ; 0 ;
- ; Clock Hold: 'GCLKP1' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; flag[2] ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; 22 ;
- ; Total number of failed paths ; ; ; ; ; ; ; ; 22 ;
- +------------------------------+------------------------------------------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
- +--------------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Settings ;
- +---------------------------------------------------------------------+--------------------+------+----+-------------+
- ; Option ; Setting ; From ; To ; Entity Name ;
- +---------------------------------------------------------------------+--------------------+------+----+-------------+
- ; Device Name ; EPM570T100C5 ; ; ; ;
- ; Timing Models ; Final ; ; ; ;
- ; Default hold multicycle ; Same as Multicycle ; ; ; ;
- ; Cut paths between unrelated clock domains ; On ; ; ; ;
- ; Cut off read during write signal paths ; On ; ; ; ;
- ; Cut off feedback from I/O pins ; On ; ; ; ;
- ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
- ; Ignore Clock Settings ; Off ; ; ; ;
- ; Analyze latches as synchronous elements ; On ; ; ; ;
- ; Enable Recovery/Removal analysis ; Off ; ; ; ;
- ; Enable Clock Latency ; Off ; ; ; ;
- ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
- ; Number of source nodes to report per destination node ; 10 ; ; ; ;
- ; Number of destination nodes to report ; 10 ; ; ; ;
- ; Number of paths to report ; 200 ; ; ; ;
- ; Report Minimum Timing Checks ; Off ; ; ; ;
- ; Use Fast Timing Models ; Off ; ; ; ;
- ; Report IO Paths Separately ; Off ; ; ; ;
- ; Perform Multicorner Analysis ; Off ; ; ; ;
- ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
- ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
- +---------------------------------------------------------------------+--------------------+------+----+-------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Settings Summary ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; GCLKP1 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Setup: 'GCLKP1' ;
- +-----------------------------------------+-----------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
- +-----------------------------------------+-----------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; N/A ; 118.58 MHz ( period = 8.433 ns ) ; Count1[0] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.724 ns ;
- ; N/A ; 118.76 MHz ( period = 8.420 ns ) ; Count1[1] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.711 ns ;
- ; N/A ; 120.60 MHz ( period = 8.292 ns ) ; flag[2] ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 5.034 ns ;
- ; N/A ; 121.09 MHz ( period = 8.258 ns ) ; flag[1] ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 5.000 ns ;
- ; N/A ; 121.91 MHz ( period = 8.203 ns ) ; flag[1] ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.945 ns ;
- ; N/A ; 123.84 MHz ( period = 8.075 ns ) ; Count1[6] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.366 ns ;
- ; N/A ; 123.90 MHz ( period = 8.071 ns ) ; Count1[4] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.362 ns ;
- ; N/A ; 123.92 MHz ( period = 8.070 ns ) ; flag[2] ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.812 ns ;
- ; N/A ; 124.05 MHz ( period = 8.061 ns ) ; light[5]~reg0 ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.803 ns ;
- ; N/A ; 125.49 MHz ( period = 7.969 ns ) ; Count1[7] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.260 ns ;
- ; N/A ; 126.10 MHz ( period = 7.930 ns ) ; flag[0] ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.672 ns ;
- ; N/A ; 126.29 MHz ( period = 7.918 ns ) ; Count1[0] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.209 ns ;
- ; N/A ; 126.50 MHz ( period = 7.905 ns ) ; Count1[1] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.196 ns ;
- ; N/A ; 127.62 MHz ( period = 7.836 ns ) ; flag[0] ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.578 ns ;
- ; N/A ; 128.65 MHz ( period = 7.773 ns ) ; light[3]~reg0 ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.515 ns ;
- ; N/A ; 128.65 MHz ( period = 7.773 ns ) ; light[6]~reg0 ; light[5]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.515 ns ;
- ; N/A ; 128.67 MHz ( period = 7.772 ns ) ; Count1[0] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 7.063 ns ;
- ; N/A ; 128.88 MHz ( period = 7.759 ns ) ; Count1[1] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 7.050 ns ;
- ; N/A ; 129.15 MHz ( period = 7.743 ns ) ; Count1[8] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.034 ns ;
- ; N/A ; 129.92 MHz ( period = 7.697 ns ) ; flag[1] ; light[0]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.439 ns ;
- ; N/A ; 129.99 MHz ( period = 7.693 ns ) ; light[4]~reg0 ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.435 ns ;
- ; N/A ; 130.01 MHz ( period = 7.692 ns ) ; light[4]~reg0 ; light[5]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.434 ns ;
- ; N/A ; 130.99 MHz ( period = 7.634 ns ) ; flag[2] ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.376 ns ;
- ; N/A ; 131.46 MHz ( period = 7.607 ns ) ; Count1[3] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.898 ns ;
- ; N/A ; 131.70 MHz ( period = 7.593 ns ) ; flag[1] ; light[7]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.335 ns ;
- ; N/A ; 132.26 MHz ( period = 7.561 ns ) ; flag[1] ; light[5]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.303 ns ;
- ; N/A ; 132.35 MHz ( period = 7.556 ns ) ; Count1[4] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.847 ns ;
- ; N/A ; 132.54 MHz ( period = 7.545 ns ) ; flag[1] ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.287 ns ;
- ; N/A ; 133.14 MHz ( period = 7.511 ns ) ; light[0]~reg0 ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.253 ns ;
- ; N/A ; 133.33 MHz ( period = 7.500 ns ) ; Count1[2] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.791 ns ;
- ; N/A ; 134.17 MHz ( period = 7.453 ns ) ; Count1[5] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.744 ns ;
- ; N/A ; 134.23 MHz ( period = 7.450 ns ) ; Count1[0] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.741 ns ;
- ; N/A ; 134.25 MHz ( period = 7.449 ns ) ; Count1[5] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.740 ns ;
- ; N/A ; 134.28 MHz ( period = 7.447 ns ) ; flag[0] ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.189 ns ;
- ; N/A ; 134.28 MHz ( period = 7.447 ns ) ; Count1[5] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.738 ns ;
- ; N/A ; 134.46 MHz ( period = 7.437 ns ) ; Count1[6] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.728 ns ;
- ; N/A ; 134.46 MHz ( period = 7.437 ns ) ; Count1[1] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.728 ns ;
- ; N/A ; 134.88 MHz ( period = 7.414 ns ) ; Count1[6] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.705 ns ;
- ; N/A ; 134.95 MHz ( period = 7.410 ns ) ; Count1[4] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.701 ns ;
- ; N/A ; 135.41 MHz ( period = 7.385 ns ) ; flag[2] ; light[0]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.127 ns ;
- ; N/A ; 135.98 MHz ( period = 7.354 ns ) ; light[6]~reg0 ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.096 ns ;
- ; N/A ; 136.22 MHz ( period = 7.341 ns ) ; Count1[0] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.632 ns ;
- ; N/A ; 136.35 MHz ( period = 7.334 ns ) ; Count1[2] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.625 ns ;
- ; N/A ; 136.37 MHz ( period = 7.333 ns ) ; Count1[5] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.624 ns ;
- ; N/A ; 136.37 MHz ( period = 7.333 ns ) ; Count1[0] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.624 ns ;
- ; N/A ; 136.41 MHz ( period = 7.331 ns ) ; Count1[7] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.622 ns ;
- ; N/A ; 136.43 MHz ( period = 7.330 ns ) ; Count1[2] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.621 ns ;
- ; N/A ; 136.46 MHz ( period = 7.328 ns ) ; Count1[2] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.619 ns ;
- ; N/A ; 136.46 MHz ( period = 7.328 ns ) ; Count1[1] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.619 ns ;
- ; N/A ; 136.61 MHz ( period = 7.320 ns ) ; Count1[1] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.611 ns ;
- ; N/A ; 136.71 MHz ( period = 7.315 ns ) ; Count1[0] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.606 ns ;
- ; N/A ; 136.78 MHz ( period = 7.311 ns ) ; Count1[0] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.602 ns ;
- ; N/A ; 136.82 MHz ( period = 7.309 ns ) ; Count1[0] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.600 ns ;
- ; N/A ; 136.84 MHz ( period = 7.308 ns ) ; Count1[7] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.599 ns ;
- ; N/A ; 137.89 MHz ( period = 7.252 ns ) ; flag[0] ; light[7]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.994 ns ;
- ; N/A ; 137.91 MHz ( period = 7.251 ns ) ; Count1[1] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.542 ns ;
- ; N/A ; 139.18 MHz ( period = 7.185 ns ) ; Count1[7] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.476 ns ;
- ; N/A ; 139.20 MHz ( period = 7.184 ns ) ; flag[0] ; light[5]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.926 ns ;
- ; N/A ; 139.26 MHz ( period = 7.181 ns ) ; Count1[7] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.472 ns ;
- ; N/A ; 139.30 MHz ( period = 7.179 ns ) ; Count1[7] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.470 ns ;
- ; N/A ; 140.85 MHz ( period = 7.100 ns ) ; Count2[6] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.391 ns ;
- ; N/A ; 141.00 MHz ( period = 7.092 ns ) ; Count1[3] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.383 ns ;
- ; N/A ; 141.08 MHz ( period = 7.088 ns ) ; Count1[4] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.379 ns ;
- ; N/A ; 141.20 MHz ( period = 7.082 ns ) ; Count1[8] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.373 ns ;
- ; N/A ; 141.32 MHz ( period = 7.076 ns ) ; Count2[0] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.367 ns ;
- ; N/A ; 141.84 MHz ( period = 7.050 ns ) ; Count1[3] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.341 ns ;
- ; N/A ; 141.92 MHz ( period = 7.046 ns ) ; Count1[3] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.337 ns ;
- ; N/A ; 141.96 MHz ( period = 7.044 ns ) ; Count1[3] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.335 ns ;
- ; N/A ; 142.19 MHz ( period = 7.033 ns ) ; Count2[1] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.324 ns ;
- ; N/A ; 143.16 MHz ( period = 6.985 ns ) ; Count1[2] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.276 ns ;
- ; N/A ; 143.45 MHz ( period = 6.971 ns ) ; light[6]~reg0 ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 3.713 ns ;
- ; N/A ; 143.45 MHz ( period = 6.971 ns ) ; Count1[4] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.262 ns ;
- ; N/A ; 143.97 MHz ( period = 6.946 ns ) ; Count1[3] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.237 ns ;
- ; N/A ; 143.99 MHz ( period = 6.945 ns ) ; Count1[9] ; Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.236 ns ;
- ; N/A ; 144.01 MHz ( period = 6.944 ns ) ; flag[2] ; light[7]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.686 ns ;
- ; N/A ; 144.89 MHz ( period = 6.902 ns ) ; Count1[4] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.193 ns ;
- ; N/A ; 145.16 MHz ( period = 6.889 ns ) ; Count2[2] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.180 ns ;
- ; N/A ; 146.22 MHz ( period = 6.839 ns ) ; Count1[2] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.130 ns ;
- ; N/A ; 147.38 MHz ( period = 6.785 ns ) ; flag[1] ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.527 ns ;
- ; N/A ; 147.38 MHz ( period = 6.785 ns ) ; flag[1] ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.527 ns ;
- ; N/A ; 147.82 MHz ( period = 6.765 ns ) ; Count2[4] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.056 ns ;
- ; N/A ; 148.61 MHz ( period = 6.729 ns ) ; Count1[6] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.020 ns ;
- ; N/A ; 148.79 MHz ( period = 6.721 ns ) ; light[1]~reg0 ; light[0]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.463 ns ;
- ; N/A ; 149.28 MHz ( period = 6.699 ns ) ; Count2[3] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.990 ns ;
- ; N/A ; 149.37 MHz ( period = 6.695 ns ) ; Count1[5] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.986 ns ;
- ; N/A ; 149.81 MHz ( period = 6.675 ns ) ; Count1[0] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.966 ns ;
- ; N/A ; 149.88 MHz ( period = 6.672 ns ) ; Count1[5] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 5.963 ns ;
- ; N/A ; 150.02 MHz ( period = 6.666 ns ) ; Count1[6] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.957 ns ;
- ; N/A ; 150.11 MHz ( period = 6.662 ns ) ; Count1[6] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.953 ns ;
- ; N/A ; 150.15 MHz ( period = 6.660 ns ) ; Count1[6] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.951 ns ;
- ; N/A ; 150.44 MHz ( period = 6.647 ns ) ; flag[0] ; light[0]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.389 ns ;
- ; N/A ; 150.74 MHz ( period = 6.634 ns ) ; Count2[5] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.925 ns ;
- ; N/A ; 150.97 MHz ( period = 6.624 ns ) ; Count1[3] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.915 ns ;
- ; N/A ; 152.09 MHz ( period = 6.575 ns ) ; flag[1] ; banner ; GCLKP1 ; GCLKP1 ; None ; None ; 3.317 ns ;
- ; N/A ; 153.44 MHz ( period = 6.517 ns ) ; Count1[2] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.808 ns ;
- ; N/A ; 153.49 MHz ( period = 6.515 ns ) ; Count1[3] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.806 ns ;
- ; N/A ; 153.68 MHz ( period = 6.507 ns ) ; Count1[3] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.798 ns ;
- ; N/A ; 154.11 MHz ( period = 6.489 ns ) ; Count1[1] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.780 ns ;
- ; N/A ; 154.30 MHz ( period = 6.481 ns ) ; Count1[4] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.772 ns ;
- ; N/A ; 154.39 MHz ( period = 6.477 ns ) ; Count1[4] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.768 ns ;
- ; N/A ; 154.49 MHz ( period = 6.473 ns ) ; flag[2] ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.215 ns ;
- ; N/A ; 154.49 MHz ( period = 6.473 ns ) ; flag[2] ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.215 ns ;
- ; N/A ; 156.05 MHz ( period = 6.408 ns ) ; Count1[2] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.699 ns ;
- ; N/A ; 156.10 MHz ( period = 6.406 ns ) ; Count1[8] ; Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.697 ns ;
- ; N/A ; 156.25 MHz ( period = 6.400 ns ) ; Count1[2] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.691 ns ;
- ; N/A ; 156.69 MHz ( period = 6.382 ns ) ; flag[2] ; banner ; GCLKP1 ; GCLKP1 ; None ; None ; 3.124 ns ;
- ; N/A ; 156.96 MHz ( period = 6.371 ns ) ; flag[2] ; light[5]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.113 ns ;
- ; N/A ; 157.11 MHz ( period = 6.365 ns ) ; light[5]~reg0 ; light[5]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 3.107 ns ;
- ; N/A ; 157.16 MHz ( period = 6.363 ns ) ; Count1[1] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.654 ns ;
- ; N/A ; 157.16 MHz ( period = 6.363 ns ) ; Count1[5] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.654 ns ;
- ; N/A ; 157.18 MHz ( period = 6.362 ns ) ; Count1[5] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.653 ns ;
- ; N/A ; 157.23 MHz ( period = 6.360 ns ) ; Count1[5] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.651 ns ;
- ; N/A ; 157.41 MHz ( period = 6.353 ns ) ; Count1[5] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.644 ns ;
- ; N/A ; 157.58 MHz ( period = 6.346 ns ) ; Count1[5] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.637 ns ;
- ; N/A ; 158.08 MHz ( period = 6.326 ns ) ; Count2[0] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.617 ns ;
- ; N/A ; 158.20 MHz ( period = 6.321 ns ) ; Count2[6] ; Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.612 ns ;
- ; N/A ; 158.28 MHz ( period = 6.318 ns ) ; Count2[6] ; Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.609 ns ;
- ; N/A ; 158.60 MHz ( period = 6.305 ns ) ; Count2[6] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.596 ns ;
- ; N/A ; 158.68 MHz ( period = 6.302 ns ) ; Count2[6] ; Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.593 ns ;
- ; N/A ; 159.13 MHz ( period = 6.284 ns ) ; Count1[9] ; Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 5.575 ns ;
- ; N/A ; 159.16 MHz ( period = 6.283 ns ) ; Count2[1] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.574 ns ;
- ; N/A ; 159.69 MHz ( period = 6.262 ns ) ; Count1[4] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.553 ns ;
- ; N/A ; 160.15 MHz ( period = 6.244 ns ) ; Count1[2] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.535 ns ;
- ; N/A ; 160.38 MHz ( period = 6.235 ns ) ; light[6]~reg0 ; light[7]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.977 ns ;
- ; N/A ; 160.41 MHz ( period = 6.234 ns ) ; Count1[2] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.525 ns ;
- ; N/A ; 160.90 MHz ( period = 6.215 ns ) ; Count1[0] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.506 ns ;
- ; N/A ; 161.11 MHz ( period = 6.207 ns ) ; light[2]~reg0 ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.949 ns ;
- ; N/A ; 161.58 MHz ( period = 6.189 ns ) ; light[3]~reg0 ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.931 ns ;
- ; N/A ; 161.73 MHz ( period = 6.183 ns ) ; Count2[1] ; Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.474 ns ;
- ; N/A ; 161.81 MHz ( period = 6.180 ns ) ; Count2[1] ; Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.471 ns ;
- ; N/A ; 162.23 MHz ( period = 6.164 ns ) ; Count2[1] ; Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.455 ns ;
- ; N/A ; 162.89 MHz ( period = 6.139 ns ) ; Count2[2] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.430 ns ;
- ; N/A ; 164.07 MHz ( period = 6.095 ns ) ; Count1[7] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.386 ns ;
- ; N/A ; 164.10 MHz ( period = 6.094 ns ) ; Count1[7] ; Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.385 ns ;
- ; N/A ; 164.15 MHz ( period = 6.092 ns ) ; Count1[7] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.383 ns ;
- ; N/A ; 164.20 MHz ( period = 6.090 ns ) ; light[5]~reg0 ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.832 ns ;
- ; N/A ; 164.28 MHz ( period = 6.087 ns ) ; Count2[0] ; Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.378 ns ;
- ; N/A ; 164.34 MHz ( period = 6.085 ns ) ; Count1[7] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.376 ns ;
- ; N/A ; 164.53 MHz ( period = 6.078 ns ) ; Count1[7] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.369 ns ;
- ; N/A ; 164.66 MHz ( period = 6.073 ns ) ; flag[1] ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.815 ns ;
- ; N/A ; 164.69 MHz ( period = 6.072 ns ) ; Count1[8] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.363 ns ;
- ; N/A ; 164.80 MHz ( period = 6.068 ns ) ; Count1[8] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.359 ns ;
- ; N/A ; 164.85 MHz ( period = 6.066 ns ) ; Count1[8] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.357 ns ;
- ; N/A ; 165.07 MHz ( period = 6.058 ns ) ; flag[1] ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.800 ns ;
- ; N/A ; 165.45 MHz ( period = 6.044 ns ) ; Count2[1] ; Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.335 ns ;
- ; N/A ; 165.76 MHz ( period = 6.033 ns ) ; Count2[6] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 5.324 ns ;
- ; N/A ; 166.25 MHz ( period = 6.015 ns ) ; Count2[4] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.306 ns ;
- ; N/A ; 167.00 MHz ( period = 5.988 ns ) ; Count2[6] ; Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.279 ns ;
- ; N/A ; 167.03 MHz ( period = 5.987 ns ) ; Count2[6] ; Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.278 ns ;
- ; N/A ; 167.17 MHz ( period = 5.982 ns ) ; flag[0] ; banner ; GCLKP1 ; GCLKP1 ; None ; None ; 2.724 ns ;
- ; N/A ; 167.59 MHz ( period = 5.967 ns ) ; Count1[6] ; Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.258 ns ;
- ; N/A ; 167.70 MHz ( period = 5.963 ns ) ; Count1[1] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.254 ns ;
- ; N/A ; 167.73 MHz ( period = 5.962 ns ) ; Count2[6] ; Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.253 ns ;
- ; N/A ; 167.79 MHz ( period = 5.960 ns ) ; Count1[3] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.251 ns ;
- ; N/A ; 168.07 MHz ( period = 5.950 ns ) ; Count1[3] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.241 ns ;
- ; N/A ; 168.10 MHz ( period = 5.949 ns ) ; Count2[3] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.240 ns ;
- ; N/A ; 168.21 MHz ( period = 5.945 ns ) ; flag[2] ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.687 ns ;
- ; N/A ; 169.18 MHz ( period = 5.911 ns ) ; Count2[0] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 5.202 ns ;
- ; N/A ; 169.49 MHz ( period = 5.900 ns ) ; Count2[2] ; Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.191 ns ;
- ; N/A ; 169.64 MHz ( period = 5.895 ns ) ; Count2[1] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 5.186 ns ;
- ; N/A ; 170.71 MHz ( period = 5.858 ns ) ; light[2]~reg0 ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.600 ns ;
- ; N/A ; 170.94 MHz ( period = 5.850 ns ) ; Count2[1] ; Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.141 ns ;
- ; N/A ; 171.70 MHz ( period = 5.824 ns ) ; Count2[1] ; Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.115 ns ;
- ; N/A ; 172.29 MHz ( period = 5.804 ns ) ; light[7]~reg0 ; light[7]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.546 ns ;
- ; N/A ; 172.53 MHz ( period = 5.796 ns ) ; Count2[0] ; Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.087 ns ;
- ; N/A ; 173.13 MHz ( period = 5.776 ns ) ; Count2[4] ; Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.067 ns ;
- ; N/A ; 173.58 MHz ( period = 5.761 ns ) ; Count2[5] ; Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.052 ns ;
- ; N/A ; 174.70 MHz ( period = 5.724 ns ) ; Count2[2] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 5.015 ns ;
- ; N/A ; 175.13 MHz ( period = 5.710 ns ) ; Count2[3] ; Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.001 ns ;
- ; N/A ; 175.84 MHz ( period = 5.687 ns ) ; light[2]~reg0 ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.429 ns ;
- ; N/A ; 176.58 MHz ( period = 5.663 ns ) ; Count2[0] ; Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.954 ns ;
- ; N/A ; 177.18 MHz ( period = 5.644 ns ) ; Count2[0] ; Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.935 ns ;
- ; N/A ; 177.81 MHz ( period = 5.624 ns ) ; Count2[2] ; Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.915 ns ;
- ; N/A ; 177.90 MHz ( period = 5.621 ns ) ; Count2[2] ; Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.912 ns ;
- ; N/A ; 178.41 MHz ( period = 5.605 ns ) ; Count2[2] ; Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.896 ns ;
- ; N/A ; 178.57 MHz ( period = 5.600 ns ) ; Count2[4] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.891 ns ;
- ; N/A ; 179.34 MHz ( period = 5.576 ns ) ; Count1[6] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.867 ns ;
- ; N/A ; 179.44 MHz ( period = 5.573 ns ) ; Count1[6] ; Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.864 ns ;
- ; N/A ; 179.66 MHz ( period = 5.566 ns ) ; Count1[6] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.857 ns ;
- ; N/A ; 179.79 MHz ( period = 5.562 ns ) ; Count1[9] ; Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.853 ns ;
- ; N/A ; 179.92 MHz ( period = 5.558 ns ) ; Count1[9] ; Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.849 ns ;
- ; N/A ; 179.99 MHz ( period = 5.556 ns ) ; Count1[9] ; Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.847 ns ;
- ; N/A ; 180.70 MHz ( period = 5.534 ns ) ; Count2[3] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.825 ns ;
- ; N/A ; 182.68 MHz ( period = 5.474 ns ) ; Count2[7] ; Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.765 ns ;
- ; N/A ; 182.85 MHz ( period = 5.469 ns ) ; Count2[5] ; clk1 ; GCLKP1 ; GCLKP1 ; None ; None ; 4.760 ns ;
- ; N/A ; 183.25 MHz ( period = 5.457 ns ) ; Count2[2] ; Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.748 ns ;
- ; N/A ; 183.89 MHz ( period = 5.438 ns ) ; flag[1] ; flag[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.180 ns ;
- ; N/A ; 184.84 MHz ( period = 5.410 ns ) ; flag[2] ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.152 ns ;
- ; N/A ; 185.49 MHz ( period = 5.391 ns ) ; Count1[4] ; Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.682 ns ;
- ; N/A ; 185.84 MHz ( period = 5.381 ns ) ; Count1[4] ; Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.672 ns ;
- ; N/A ; 185.98 MHz ( period = 5.377 ns ) ; flag[0] ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.119 ns ;
- ; N/A ; 186.01 MHz ( period = 5.376 ns ) ; flag[0] ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.118 ns ;
- ; N/A ; 186.57 MHz ( period = 5.360 ns ) ; flag[2] ; flag[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.102 ns ;
- ; N/A ; 186.74 MHz ( period = 5.355 ns ) ; flag[0] ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.097 ns ;
- ; N/A ; 186.85 MHz ( period = 5.352 ns ) ; light[3]~reg0 ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.094 ns ;
- ; N/A ; 186.88 MHz ( period = 5.351 ns ) ; light[1]~reg0 ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.093 ns ;
- ; N/A ; 187.09 MHz ( period = 5.345 ns ) ; light[1]~reg0 ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.087 ns ;
- ; N/A ; 187.48 MHz ( period = 5.334 ns ) ; light[4]~reg0 ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.076 ns ;
- ; N/A ; 188.15 MHz ( period = 5.315 ns ) ; light[0]~reg0 ; light[0]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.057 ns ;
- ; N/A ; 188.18 MHz ( period = 5.314 ns ) ; light[6]~reg0 ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.056 ns ;
- ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
- +-----------------------------------------+-----------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Hold: 'GCLKP1' ;
- +------------------------------------------+---------------+---------------+------------+----------+----------------------------+----------------------------+--------------------------+
- ; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
- +------------------------------------------+---------------+---------------+------------+----------+----------------------------+----------------------------+--------------------------+
- ; Not operational: Clock Skew > Data Delay ; flag[2] ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 1.642 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[0] ; flag[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 1.653 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[0] ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 1.661 ns ;
- ; Not operational: Clock Skew > Data Delay ; banner ; banner ; GCLKP1 ; GCLKP1 ; None ; None ; 1.779 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[2]~reg0 ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 1.817 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[2]~reg0 ; flag[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 1.819 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[7]~reg0 ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 1.978 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[6]~reg0 ; light[6]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.056 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[0]~reg0 ; light[0]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.057 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[4]~reg0 ; light[4]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.076 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[1]~reg0 ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.087 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[1]~reg0 ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.093 ns ;
- ; Not operational: Clock Skew > Data Delay ; light[3]~reg0 ; light[3]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.094 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[0] ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.097 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[2] ; flag[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.102 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[2] ; light[2]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.104 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[0] ; light[1]~reg0 ; GCLKP1 ; GCLKP1 ; None ; None ; 2.118 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[0] ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.119 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[2] ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.152 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[2] ; flag[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.154 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[1] ; flag[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.173 ns ;
- ; Not operational: Clock Skew > Data Delay ; flag[1] ; flag[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 2.180 ns ;
- +------------------------------------------+---------------+---------------+------------+----------+----------------------------+----------------------------+--------------------------+
- +---------------------------------------------------------------------------+
- ; tco ;
- +-------+--------------+------------+---------------+----------+------------+
- ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
- +-------+--------------+------------+---------------+----------+------------+
- ; N/A ; None ; 31.417 ns ; light[4]~reg0 ; light[4] ; GCLKP1 ;
- ; N/A ; None ; 31.400 ns ; light[2]~reg0 ; light[2] ; GCLKP1 ;
- ; N/A ; None ; 31.349 ns ; light[6]~reg0 ; light[6] ; GCLKP1 ;
- ; N/A ; None ; 31.297 ns ; light[0]~reg0 ; light[0] ; GCLKP1 ;
- ; N/A ; None ; 30.863 ns ; light[5]~reg0 ; light[5] ; GCLKP1 ;
- ; N/A ; None ; 30.838 ns ; light[1]~reg0 ; light[1] ; GCLKP1 ;
- ; N/A ; None ; 30.836 ns ; light[3]~reg0 ; light[3] ; GCLKP1 ;
- ; N/A ; None ; 30.743 ns ; light[7]~reg0 ; light[7] ; GCLKP1 ;
- +-------+--------------+------------+---------------+----------+------------+
- +--------------------------+
- ; Timing Analyzer Messages ;
- +--------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Classic Timing Analyzer
- Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
- Info: Processing started: Thu Jun 11 23:37:36 2009
- Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Light -c Light
- Info: Started post-fitting delay annotation
- Info: Delay annotation completed successfully
- Warning: Found pins functioning as undefined clocks and/or memory enables
- Info: Assuming node "GCLKP1" is an undefined clock
- Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
- Info: Detected ripple clock "Period1uS" as buffer
- Info: Detected ripple clock "Period1mS" as buffer
- Info: Detected ripple clock "clk1" as buffer
- Info: Detected ripple clock "clk2" as buffer
- Info: Detected ripple clock "banner" as buffer
- Info: Detected gated clock "clk" as buffer
- Info: Clock "GCLKP1" has Internal fmax of 118.58 MHz between source register "Count1[0]" and destination register "Count1[9]" (period= 8.433 ns)
- Info: + Longest register to register delay is 7.724 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y1_N4; Fanout = 4; REG Node = 'Count1[0]'
- Info: 2: + IC(2.012 ns) + CELL(0.747 ns) = 2.759 ns; Loc. = LC_X11_Y2_N0; Fanout = 2; COMB Node = 'Add1~660'
- Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.882 ns; Loc. = LC_X11_Y2_N1; Fanout = 2; COMB Node = 'Add1~657'
- Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.005 ns; Loc. = LC_X11_Y2_N2; Fanout = 2; COMB Node = 'Add1~654'
- Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 3.128 ns; Loc. = LC_X11_Y2_N3; Fanout = 2; COMB Node = 'Add1~648'
- Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 3.389 ns; Loc. = LC_X11_Y2_N4; Fanout = 5; COMB Node = 'Add1~651'
- Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 4.364 ns; Loc. = LC_X11_Y2_N9; Fanout = 2; COMB Node = 'Add1~632'
- Info: 8: + IC(2.108 ns) + CELL(0.200 ns) = 6.672 ns; Loc. = LC_X12_Y1_N6; Fanout = 1; COMB Node = 'Add1~634'
- Info: 9: + IC(0.772 ns) + CELL(0.280 ns) = 7.724 ns; Loc. = LC_X12_Y1_N0; Fanout = 2; REG Node = 'Count1[9]'
- Info: Total cell delay = 2.832 ns ( 36.66 % )
- Info: Total interconnect delay = 4.892 ns ( 63.34 % )
- Info: - Smallest clock skew is 0.000 ns
- Info: + Shortest clock path from clock "GCLKP1" to destination register is 9.796 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X5_Y7_N0; Fanout = 11; REG Node = 'Period1uS'
- Info: 3: + IC(4.821 ns) + CELL(0.918 ns) = 9.796 ns; Loc. = LC_X12_Y1_N0; Fanout = 2; REG Node = 'Count1[9]'
- Info: Total cell delay = 3.375 ns ( 34.45 % )
- Info: Total interconnect delay = 6.421 ns ( 65.55 % )
- Info: - Longest clock path from clock "GCLKP1" to source register is 9.796 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X5_Y7_N0; Fanout = 11; REG Node = 'Period1uS'
- Info: 3: + IC(4.821 ns) + CELL(0.918 ns) = 9.796 ns; Loc. = LC_X12_Y1_N4; Fanout = 4; REG Node = 'Count1[0]'
- Info: Total cell delay = 3.375 ns ( 34.45 % )
- Info: Total interconnect delay = 6.421 ns ( 65.55 % )
- Info: + Micro clock to output delay of source is 0.376 ns
- Info: + Micro setup delay of destination is 0.333 ns
- Warning: Circuit may not operate. Detected 22 non-operational path(s) clocked by clock "GCLKP1" with clock skew larger than data delay. See Compilation Report for details.
- Info: Found hold time violation between source pin or register "flag[2]" and destination pin or register "light[1]~reg0" for clock "GCLKP1" (Hold time is 752 ps)
- Info: + Largest clock skew is 2.549 ns
- Info: + Longest clock path from clock "GCLKP1" to destination register is 26.174 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X5_Y7_N0; Fanout = 11; REG Node = 'Period1uS'
- Info: 3: + IC(4.821 ns) + CELL(1.294 ns) = 10.172 ns; Loc. = LC_X12_Y1_N6; Fanout = 9; REG Node = 'Period1mS'
- Info: 4: + IC(4.228 ns) + CELL(1.294 ns) = 15.694 ns; Loc. = LC_X9_Y4_N9; Fanout = 2; REG Node = 'clk1'
- Info: 5: + IC(2.652 ns) + CELL(1.294 ns) = 19.640 ns; Loc. = LC_X5_Y6_N7; Fanout = 2; REG Node = 'clk2'
- Info: 6: + IC(0.985 ns) + CELL(0.511 ns) = 21.136 ns; Loc. = LC_X5_Y6_N3; Fanout = 12; COMB Node = 'clk'
- Info: 7: + IC(4.120 ns) + CELL(0.918 ns) = 26.174 ns; Loc. = LC_X7_Y6_N8; Fanout = 4; REG Node = 'light[1]~reg0'
- Info: Total cell delay = 7.768 ns ( 29.68 % )
- Info: Total interconnect delay = 18.406 ns ( 70.32 % )
- Info: - Shortest clock path from clock "GCLKP1" to source register is 23.625 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X5_Y7_N0; Fanout = 11; REG Node = 'Period1uS'
- Info: 3: + IC(4.821 ns) + CELL(1.294 ns) = 10.172 ns; Loc. = LC_X12_Y1_N6; Fanout = 9; REG Node = 'Period1mS'
- Info: 4: + IC(4.228 ns) + CELL(1.294 ns) = 15.694 ns; Loc. = LC_X9_Y4_N9; Fanout = 2; REG Node = 'clk1'
- Info: 5: + IC(2.693 ns) + CELL(0.200 ns) = 18.587 ns; Loc. = LC_X5_Y6_N3; Fanout = 12; COMB Node = 'clk'
- Info: 6: + IC(4.120 ns) + CELL(0.918 ns) = 23.625 ns; Loc. = LC_X7_Y6_N9; Fanout = 17; REG Node = 'flag[2]'
- Info: Total cell delay = 6.163 ns ( 26.09 % )
- Info: Total interconnect delay = 17.462 ns ( 73.91 % )
- Info: - Micro clock to output delay of source is 0.376 ns
- Info: - Shortest register to register delay is 1.642 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N9; Fanout = 17; REG Node = 'flag[2]'
- Info: 2: + IC(1.051 ns) + CELL(0.591 ns) = 1.642 ns; Loc. = LC_X7_Y6_N8; Fanout = 4; REG Node = 'light[1]~reg0'
- Info: Total cell delay = 0.591 ns ( 35.99 % )
- Info: Total interconnect delay = 1.051 ns ( 64.01 % )
- Info: + Micro hold delay of destination is 0.221 ns
- Info: tco from clock "GCLKP1" to destination pin "light[4]" through register "light[4]~reg0" is 31.417 ns
- Info: + Longest clock path from clock "GCLKP1" to source register is 26.174 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X5_Y7_N0; Fanout = 11; REG Node = 'Period1uS'
- Info: 3: + IC(4.821 ns) + CELL(1.294 ns) = 10.172 ns; Loc. = LC_X12_Y1_N6; Fanout = 9; REG Node = 'Period1mS'
- Info: 4: + IC(4.228 ns) + CELL(1.294 ns) = 15.694 ns; Loc. = LC_X9_Y4_N9; Fanout = 2; REG Node = 'clk1'
- Info: 5: + IC(2.652 ns) + CELL(1.294 ns) = 19.640 ns; Loc. = LC_X5_Y6_N7; Fanout = 2; REG Node = 'clk2'
- Info: 6: + IC(0.985 ns) + CELL(0.511 ns) = 21.136 ns; Loc. = LC_X5_Y6_N3; Fanout = 12; COMB Node = 'clk'
- Info: 7: + IC(4.120 ns) + CELL(0.918 ns) = 26.174 ns; Loc. = LC_X7_Y6_N3; Fanout = 4; REG Node = 'light[4]~reg0'
- Info: Total cell delay = 7.768 ns ( 29.68 % )
- Info: Total interconnect delay = 18.406 ns ( 70.32 % )
- Info: + Micro clock to output delay of source is 0.376 ns
- Info: + Longest register to pin delay is 4.867 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y6_N3; Fanout = 4; REG Node = 'light[4]~reg0'
- Info: 2: + IC(2.545 ns) + CELL(2.322 ns) = 4.867 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'light[4]'
- Info: Total cell delay = 2.322 ns ( 47.71 % )
- Info: Total interconnect delay = 2.545 ns ( 52.29 % )
- Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 123 megabytes
- Info: Processing ended: Thu Jun 11 23:37:37 2009
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
