VHDL/FPGA/Verilog

开发平台：
Others

Display.vhd：源码内容
							---------------------------------------------------------------------------------------------------
--*************************************************************************************************
--  CreateDate  :  2007-07-12 
--  ModifData   :  2007-07-12 
--  Description :  LED4 Display 
--  Author      :  Explorer01 
--  Version     :  V1.0  
--*************************************************************************************************
---------------------------------------------------------------------------------------------------
-- VHDL library Declarations 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- The Entity Declarations 
ENTITY LED4 IS
	PORT 
	(
		RESET: 		IN STD_LOGIC; 
		ClockScan:	IN STD_LOGIC;
		
		LED1:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		LED2:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		LED3:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		LED4:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		
		Light:		 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		
		LEDOut:		 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		DigitSelect: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END LED4;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- The Architecture of Entity Declarations 
ARCHITECTURE LED4_arch OF LED4 IS
	SIGNAL LED:		STD_LOGIC_VECTOR(3 downto 0);
--	SIGNAL LED2, LED3, LED4:	STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL Refresh: STD_LOGIC_VECTOR(1 downto 0);
BEGIN
	
	-------------------------------------------------
	-- Encoder 
	-- HEX-to-seven-segment decoder 
	-- segment encoding 
	--      0 
	--     ---  
	--  5 |   | 1
	--     ---   <- 6
	--  4 |   | 2
	--     ---  
	--      3
	PROCESS( LED )   
	BEGIN
		CASE LED IS
			when "0000"=>LEDOut<= "00111111";    --'0'
			when "0001"=>LEDOut<= "00000110";    --'1'
			when "0010"=>LEDOut<= "01011011";    --'2'
			when "0011"=>LEDOut<= "01001111";    --'3'
			when "0100"=>LEDOut<= "01100110";    --'4'
			when "0101"=>LEDOut<= "01101101";    --'5'
			when "0110"=>LEDOut<= "01111101";    --'6'
			when "0111"=>LEDOut<= "00000111";    --'7'
			when "1000"=>LEDOut<= "01111111";    --'8'
			when "1001"=>LEDOut<= "01101111";    --'9'
			when "1010"=>LEDOut<= "01110111";    --'A'
			when "1011"=>LEDOut<= "01111100";    --'b'
			when "1100"=>LEDOut<= "00111001";    --'C'
			when "1101"=>LEDOut<= "01011110";    --'d'
			when "1110"=>LEDOut<= "01111001";    --'E'
			when "1111"=>LEDOut<= "01110001";    --'F'
			when others=>LEDOut<= "XXXXXXXX";    --' '
		END CASE;
	END PROCESS;
	
	-------------------------------------------------
	-- Scan 
--	PROCESS( ClockScan, clock ) 
--	BEGIN
--		IF ClockScan = '0' THEN clock <= '0';
--		ELSE					clock <= '1';
--		END IF; 
--	END PROCESS;
	
	-------------------------------------------------
	-- clock 
	PROCESS( ClockScan )   
	BEGIN
		IF( ClockScan'EVENT AND ClockScan = '1' )THEN 
			Refresh <= Refresh + 1; 
		END IF; 
	END PROCESS;
	
	-------------------------------------------------
	-- MUX 
	LED <= 
	LED1 when( Refresh=0 ) else
	LED2 when( Refresh=1 ) else
	LED3 when( Refresh=2 ) else
	LED4;
	
	-------------------------------------------------
	--  LED Digit Select 
	DigitSelect <= 
	"1110" when( Refresh=0 ) else
	"1101" when( Refresh=1 ) else
	"1011" when( Refresh=2 ) else
	"0111";
	
	-------------------------------------------------
	-- 
	Light <= NOT (LED1 & LED2); 
	
END LED4_arch;

						