VHDL/FPGA/Verilog

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key44.v：源码内容
							module key44(
       code      ,
       col       ,
       valid     ,
       row       ,
       sys_clk       ,
       rst       
                );
 output  [3:0]  col     ;
 output         valid   ;
 output  [3:0]  code    ;
 
 input   [3:0]  row     ;
 input          sys_clk,rst ;
 
 reg     [3:0]  col,code;
 reg     [5:0]  state,next_state;
 
 parameter  S_0 = 6'b000001,
            S_1 = 6'b000010,
            S_2 = 6'b000100,
            S_3 = 6'b001000,
            S_4 = 6'b010000,
            S_5 = 6'b100000;
 reg       S_row ; 
 reg [3:0] count,row_reg,col_reg;
 reg       clk2,clk4;
 
 
 reg [24:0] Mega_cnt;
 wire       clk;
/**************************************/
always @(posedge sys_clk or negedge rst)
begin
if(!rst)
  begin
  Mega_cnt<=0;
  end
else
  begin
  Mega_cnt<=Mega_cnt+1;
  end
end
assign clk = Mega_cnt[4];
/**************************************/ 
 
 always @ (posedge clk)
 clk2 <= ~clk2;
 
 always @ (posedge clk2)
 clk4 <= ~clk4;
           
 always @ (posedge clk4 or negedge rst)
 if(!rst)
     begin
         count <= 0;
         S_row <= 0;
     end
 else
     begin
         if(!(row[0]&row[1]&row[2]&row[3]))
             begin
                 if(count < 'd4)
                     count <= count +1 ;
                 else
                     S_row <= 1;
             end
         else if(state[5]||state[0])
            begin
                count <= 0;
                S_row <= 0;
            end
     end
     
 assign valid = ((state == S_1)||(state == S_2)||(state == S_3)||(state == S_4)) &&  (!(row[3]&row[2]&row[1]&row[0])) ;
 
 always @ (negedge clk)
 if(valid)
     begin
        row_reg <= row ;
        col_reg <= col ;
     end
  else
     begin
        row_reg <= row_reg ;
        col_reg <= col_reg ;
     end
     
 always @ (row_reg or col_reg or clk)
     case({row_reg,col_reg})
        8'b1110_1110: code = 13;
        8'b1110_1101: code = 9 ;
        8'b1110_1011: code = 5 ;
        8'b1110_0111: code = 1 ;
        
        8'b1101_1110: code = 14;
        8'b1101_1101: code = 10;
        8'b1101_1011: code = 6 ;
        8'b1101_0111: code = 2 ;
        
        8'b1011_1110: code = 15 ;
        8'b1011_1101: code = 11 ;
        8'b1011_1011: code = 7;
        8'b1011_0111: code = 3;
        
        8'b0111_1110: code = 0;
        8'b0111_1101: code = 12;
        8'b0111_1011: code = 8;
        8'b0111_0111: code = 4;              
    endcase
 
 always @ (posedge clk4 or negedge rst)
 if(!rst)
      state <= S_0 ;
 else
      state <= next_state ;
    
 always @ ( state or row or S_row)
 begin
   //  next_state = state ; 
     col =0;
     case(state)
        S_0 :  begin
                   col = 4'b0000;
                   if(S_row)
                       next_state = S_1;
                   else
                       next_state = S_0;
               end
        S_1 :  begin
                   col = 4'b1110;
                   if(row!='hf)
                       next_state = S_5;
                   else
                       next_state = S_2;
               end
        S_2 :  begin
                   col = 4'b1101;
                   if(row!='hf)
                       next_state = S_5;
                   else
                       next_state = S_3;
               end 
        S_3 :  begin
                   col = 4'b1011;
                   if(row!='hf)
                       next_state = S_5;
                   else
                       next_state = S_4;
               end  
        S_4 :  begin
                   col = 4'b0111;
                   if(row!='hf)
                       next_state = S_5;
                   else
                       next_state = S_0;
               end  
        S_5 :  begin
                   col = 4'b0000;
                   if(row == 4'b1111) 
                       next_state = S_0;
                   else 
                       next_state = S_5;
               end
        default: next_state = S_0;
  endcase
  end
endmodule

						