English
PS2.tan.rpt
资源名称：PS2.rar [点击查看]
上传用户：keloyb
上传日期：2022-08-09
资源大小：256k
文件大小：97k
源码类别：
VHDL/FPGA/Verilog
开发平台：
Others
- Classic Timing Analyzer report for PS2
- Thu Jun 11 23:51:40 2009
- Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Timing Analyzer Settings
- 4. Clock Settings Summary
- 5. Clock Setup: 'KBCLK'
- 6. Clock Setup: 'GCLKP1'
- 7. tsu
- 8. tco
- 9. th
- 10. Timing Analyzer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2008 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Summary ;
- +------------------------------+-------+---------------+----------------------------------+--------------------------------+--------------------------------+------------+----------+--------------+
- ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
- +------------------------------+-------+---------------+----------------------------------+--------------------------------+--------------------------------+------------+----------+--------------+
- ; Worst-case tsu ; N/A ; None ; -0.248 ns ; KBDATA ; PS2VHDL:inst2|spdata[1] ; -- ; KBCLK ; 0 ;
- ; Worst-case tco ; N/A ; None ; 29.186 ns ; LED4:inst|Refresh[1] ; LEDOUT[6] ; GCLKP1 ; -- ; 0 ;
- ; Worst-case th ; N/A ; None ; 1.094 ns ; KBDATA ; PS2VHDL:inst2|spdata[4] ; -- ; KBCLK ; 0 ;
- ; Clock Setup: 'GCLKP1' ; N/A ; None ; 119.08 MHz ( period = 8.398 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; 0 ;
- ; Clock Setup: 'KBCLK' ; N/A ; None ; 207.77 MHz ( period = 4.813 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[6] ; KBCLK ; KBCLK ; 0 ;
- ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
- +------------------------------+-------+---------------+----------------------------------+--------------------------------+--------------------------------+------------+----------+--------------+
- +--------------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Settings ;
- +---------------------------------------------------------------------+--------------------+------+----+-------------+
- ; Option ; Setting ; From ; To ; Entity Name ;
- +---------------------------------------------------------------------+--------------------+------+----+-------------+
- ; Device Name ; EPM570T100C5 ; ; ; ;
- ; Timing Models ; Final ; ; ; ;
- ; Default hold multicycle ; Same as Multicycle ; ; ; ;
- ; Cut paths between unrelated clock domains ; On ; ; ; ;
- ; Cut off read during write signal paths ; On ; ; ; ;
- ; Cut off feedback from I/O pins ; On ; ; ; ;
- ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
- ; Ignore Clock Settings ; Off ; ; ; ;
- ; Analyze latches as synchronous elements ; On ; ; ; ;
- ; Enable Recovery/Removal analysis ; Off ; ; ; ;
- ; Enable Clock Latency ; Off ; ; ; ;
- ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
- ; Number of source nodes to report per destination node ; 10 ; ; ; ;
- ; Number of destination nodes to report ; 10 ; ; ; ;
- ; Number of paths to report ; 200 ; ; ; ;
- ; Report Minimum Timing Checks ; Off ; ; ; ;
- ; Use Fast Timing Models ; Off ; ; ; ;
- ; Report IO Paths Separately ; Off ; ; ; ;
- ; Perform Multicorner Analysis ; Off ; ; ; ;
- ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
- ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
- +---------------------------------------------------------------------+--------------------+------+----+-------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Settings Summary ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; KBCLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
- ; GCLKP1 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Setup: 'KBCLK' ;
- +-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
- +-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; N/A ; 207.77 MHz ( period = 4.813 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[6] ; KBCLK ; KBCLK ; None ; None ; 4.104 ns ;
- ; N/A ; 215.94 MHz ( period = 4.631 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[6] ; KBCLK ; KBCLK ; None ; None ; 3.922 ns ;
- ; N/A ; 217.82 MHz ( period = 4.591 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[4] ; KBCLK ; KBCLK ; None ; None ; 3.882 ns ;
- ; N/A ; 217.91 MHz ( period = 4.589 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[2] ; KBCLK ; KBCLK ; None ; None ; 3.880 ns ;
- ; N/A ; 218.15 MHz ( period = 4.584 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[3] ; KBCLK ; KBCLK ; None ; None ; 3.875 ns ;
- ; N/A ; 218.20 MHz ( period = 4.583 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[7] ; KBCLK ; KBCLK ; None ; None ; 3.874 ns ;
- ; N/A ; 223.36 MHz ( period = 4.477 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[6] ; KBCLK ; KBCLK ; None ; None ; 3.768 ns ;
- ; N/A ; 226.96 MHz ( period = 4.406 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[3] ; KBCLK ; KBCLK ; None ; None ; 3.697 ns ;
- ; N/A ; 227.01 MHz ( period = 4.405 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[7] ; KBCLK ; KBCLK ; None ; None ; 3.696 ns ;
- ; N/A ; 227.43 MHz ( period = 4.397 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[4] ; KBCLK ; KBCLK ; None ; None ; 3.688 ns ;
- ; N/A ; 227.48 MHz ( period = 4.396 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[2] ; KBCLK ; KBCLK ; None ; None ; 3.687 ns ;
- ; N/A ; 235.18 MHz ( period = 4.252 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[3] ; KBCLK ; KBCLK ; None ; None ; 3.543 ns ;
- ; N/A ; 235.29 MHz ( period = 4.250 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[7] ; KBCLK ; KBCLK ; None ; None ; 3.541 ns ;
- ; N/A ; 235.68 MHz ( period = 4.243 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[4] ; KBCLK ; KBCLK ; None ; None ; 3.534 ns ;
- ; N/A ; 235.74 MHz ( period = 4.242 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[2] ; KBCLK ; KBCLK ; None ; None ; 3.533 ns ;
- ; N/A ; 240.62 MHz ( period = 4.156 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[6] ; KBCLK ; KBCLK ; None ; None ; 3.447 ns ;
- ; N/A ; 249.00 MHz ( period = 4.016 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[8] ; KBCLK ; KBCLK ; None ; None ; 3.307 ns ;
- ; N/A ; 254.45 MHz ( period = 3.930 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[4] ; KBCLK ; KBCLK ; None ; None ; 3.221 ns ;
- ; N/A ; 254.52 MHz ( period = 3.929 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[2] ; KBCLK ; KBCLK ; None ; None ; 3.220 ns ;
- ; N/A ; 254.91 MHz ( period = 3.923 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[7] ; KBCLK ; KBCLK ; None ; None ; 3.214 ns ;
- ; N/A ; 255.04 MHz ( period = 3.921 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[3] ; KBCLK ; KBCLK ; None ; None ; 3.212 ns ;
- ; N/A ; 265.18 MHz ( period = 3.771 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[8] ; KBCLK ; KBCLK ; None ; None ; 3.062 ns ;
- ; N/A ; 276.01 MHz ( period = 3.623 ns ) ; PS2VHDL:inst2|spdata[2] ; PS2VHDL:inst2|spdata[2] ; KBCLK ; KBCLK ; None ; None ; 2.914 ns ;
- ; N/A ; 277.32 MHz ( period = 3.606 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[5] ; KBCLK ; KBCLK ; None ; None ; 2.897 ns ;
- ; N/A ; 277.93 MHz ( period = 3.598 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[8] ; KBCLK ; KBCLK ; None ; None ; 2.889 ns ;
- ; N/A ; 278.01 MHz ( period = 3.597 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|spdata[1] ; KBCLK ; KBCLK ; None ; None ; 2.888 ns ;
- ; N/A ; 297.62 MHz ( period = 3.360 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[5] ; KBCLK ; KBCLK ; None ; None ; 2.651 ns ;
- ; N/A ; 299.04 MHz ( period = 3.344 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|spdata[1] ; KBCLK ; KBCLK ; None ; None ; 2.635 ns ;
- ; N/A ; 301.57 MHz ( period = 3.316 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[8] ; KBCLK ; KBCLK ; None ; None ; 2.607 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[1] ; KBCLK ; KBCLK ; None ; None ; 2.475 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|spdata[5] ; KBCLK ; KBCLK ; None ; None ; 2.467 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|cnt8[2] ; KBCLK ; KBCLK ; None ; None ; 2.268 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|cnt8[0] ; KBCLK ; KBCLK ; None ; None ; 2.267 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|cnt8[3] ; KBCLK ; KBCLK ; None ; None ; 2.259 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[1] ; PS2VHDL:inst2|cnt8[1] ; KBCLK ; KBCLK ; None ; None ; 2.257 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[1] ; KBCLK ; KBCLK ; None ; None ; 2.193 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|spdata[5] ; KBCLK ; KBCLK ; None ; None ; 2.180 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[3] ; PS2VHDL:inst2|spdata[3] ; KBCLK ; KBCLK ; None ; None ; 2.154 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[1] ; PS2VHDL:inst2|spdata[1] ; KBCLK ; KBCLK ; None ; None ; 2.122 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|cnt8[2] ; KBCLK ; KBCLK ; None ; None ; 2.074 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|cnt8[0] ; KBCLK ; KBCLK ; None ; None ; 2.072 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|cnt8[1] ; KBCLK ; KBCLK ; None ; None ; 2.063 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[3] ; PS2VHDL:inst2|cnt8[3] ; KBCLK ; KBCLK ; None ; None ; 2.059 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[7] ; PS2VHDL:inst2|spdata[7] ; KBCLK ; KBCLK ; None ; None ; 2.057 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[8] ; PS2VHDL:inst2|spdata[8] ; KBCLK ; KBCLK ; None ; None ; 2.009 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[5] ; PS2VHDL:inst2|spdata[5] ; KBCLK ; KBCLK ; None ; None ; 1.962 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|cnt8[3] ; KBCLK ; KBCLK ; None ; None ; 1.870 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|cnt8[1] ; KBCLK ; KBCLK ; None ; None ; 1.869 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|cnt8[2] ; KBCLK ; KBCLK ; None ; None ; 1.862 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[0] ; PS2VHDL:inst2|cnt8[0] ; KBCLK ; KBCLK ; None ; None ; 1.857 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[4] ; PS2VHDL:inst2|spdata[4] ; KBCLK ; KBCLK ; None ; None ; 1.754 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|spdata[6] ; PS2VHDL:inst2|spdata[6] ; KBCLK ; KBCLK ; None ; None ; 1.743 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|cnt8[3] ; KBCLK ; KBCLK ; None ; None ; 1.686 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|cnt8[1] ; KBCLK ; KBCLK ; None ; None ; 1.685 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|cnt8[0] ; KBCLK ; KBCLK ; None ; None ; 1.677 ns ;
- ; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; PS2VHDL:inst2|cnt8[2] ; PS2VHDL:inst2|cnt8[2] ; KBCLK ; KBCLK ; None ; None ; 1.674 ns ;
- +-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Setup: 'GCLKP1' ;
- +-----------------------------------------+-----------------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
- +-----------------------------------------+-----------------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; N/A ; 119.08 MHz ( period = 8.398 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.689 ns ;
- ; N/A ; 119.75 MHz ( period = 8.351 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.642 ns ;
- ; N/A ; 120.74 MHz ( period = 8.282 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.573 ns ;
- ; N/A ; 120.88 MHz ( period = 8.273 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.564 ns ;
- ; N/A ; 120.98 MHz ( period = 8.266 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.557 ns ;
- ; N/A ; 121.23 MHz ( period = 8.249 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.540 ns ;
- ; N/A ; 121.43 MHz ( period = 8.235 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.526 ns ;
- ; N/A ; 121.57 MHz ( period = 8.226 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.517 ns ;
- ; N/A ; 121.92 MHz ( period = 8.202 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.493 ns ;
- ; N/A ; 122.68 MHz ( period = 8.151 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.442 ns ;
- ; N/A ; 124.46 MHz ( period = 8.035 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.326 ns ;
- ; N/A ; 124.60 MHz ( period = 8.026 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.317 ns ;
- ; N/A ; 124.97 MHz ( period = 8.002 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.293 ns ;
- ; N/A ; 125.38 MHz ( period = 7.976 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.267 ns ;
- ; N/A ; 125.75 MHz ( period = 7.952 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.243 ns ;
- ; N/A ; 126.12 MHz ( period = 7.929 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.220 ns ;
- ; N/A ; 126.58 MHz ( period = 7.900 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.191 ns ;
- ; N/A ; 126.65 MHz ( period = 7.896 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.187 ns ;
- ; N/A ; 127.40 MHz ( period = 7.849 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.140 ns ;
- ; N/A ; 127.49 MHz ( period = 7.844 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.135 ns ;
- ; N/A ; 128.47 MHz ( period = 7.784 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.075 ns ;
- ; N/A ; 128.62 MHz ( period = 7.775 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.066 ns ;
- ; N/A ; 128.78 MHz ( period = 7.765 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.056 ns ;
- ; N/A ; 129.02 MHz ( period = 7.751 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.042 ns ;
- ; N/A ; 129.18 MHz ( period = 7.741 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.032 ns ;
- ; N/A ; 129.32 MHz ( period = 7.733 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.024 ns ;
- ; N/A ; 129.33 MHz ( period = 7.732 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 7.023 ns ;
- ; N/A ; 129.38 MHz ( period = 7.729 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.020 ns ;
- ; N/A ; 129.47 MHz ( period = 7.724 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 7.015 ns ;
- ; N/A ; 129.87 MHz ( period = 7.700 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.991 ns ;
- ; N/A ; 130.74 MHz ( period = 7.649 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.940 ns ;
- ; N/A ; 130.89 MHz ( period = 7.640 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.931 ns ;
- ; N/A ; 131.30 MHz ( period = 7.616 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.907 ns ;
- ; N/A ; 131.30 MHz ( period = 7.616 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.907 ns ;
- ; N/A ; 131.46 MHz ( period = 7.607 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.898 ns ;
- ; N/A ; 131.58 MHz ( period = 7.600 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.891 ns ;
- ; N/A ; 131.87 MHz ( period = 7.583 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.874 ns ;
- ; N/A ; 132.61 MHz ( period = 7.541 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.832 ns ;
- ; N/A ; 133.80 MHz ( period = 7.474 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.765 ns ;
- ; N/A ; 133.85 MHz ( period = 7.471 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.762 ns ;
- ; N/A ; 134.01 MHz ( period = 7.462 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.753 ns ;
- ; N/A ; 134.57 MHz ( period = 7.431 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.722 ns ;
- ; N/A ; 134.64 MHz ( period = 7.427 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.718 ns ;
- ; N/A ; 134.81 MHz ( period = 7.418 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.709 ns ;
- ; N/A ; 135.37 MHz ( period = 7.387 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.678 ns ;
- ; N/A ; 135.67 MHz ( period = 7.371 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.662 ns ;
- ; N/A ; 136.13 MHz ( period = 7.346 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.637 ns ;
- ; N/A ; 136.18 MHz ( period = 7.343 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.634 ns ;
- ; N/A ; 136.52 MHz ( period = 7.325 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.616 ns ;
- ; N/A ; 136.74 MHz ( period = 7.313 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.604 ns ;
- ; N/A ; 136.80 MHz ( period = 7.310 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.601 ns ;
- ; N/A ; 137.25 MHz ( period = 7.286 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.577 ns ;
- ; N/A ; 137.31 MHz ( period = 7.283 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.574 ns ;
- ; N/A ; 137.67 MHz ( period = 7.264 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.555 ns ;
- ; N/A ; 138.16 MHz ( period = 7.238 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.529 ns ;
- ; N/A ; 138.37 MHz ( period = 7.227 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.518 ns ;
- ; N/A ; 139.31 MHz ( period = 7.178 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.469 ns ;
- ; N/A ; 141.34 MHz ( period = 7.075 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 6.366 ns ;
- ; N/A ; 141.42 MHz ( period = 7.071 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.362 ns ;
- ; N/A ; 141.66 MHz ( period = 7.059 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.350 ns ;
- ; N/A ; 142.25 MHz ( period = 7.030 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.321 ns ;
- ; N/A ; 142.31 MHz ( period = 7.027 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.318 ns ;
- ; N/A ; 142.67 MHz ( period = 7.009 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.300 ns ;
- ; N/A ; 143.29 MHz ( period = 6.979 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.270 ns ;
- ; N/A ; 143.45 MHz ( period = 6.971 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.262 ns ;
- ; N/A ; 143.45 MHz ( period = 6.971 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.262 ns ;
- ; N/A ; 143.97 MHz ( period = 6.946 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.237 ns ;
- ; N/A ; 144.70 MHz ( period = 6.911 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.202 ns ;
- ; N/A ; 145.29 MHz ( period = 6.883 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.174 ns ;
- ; N/A ; 145.37 MHz ( period = 6.879 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.170 ns ;
- ; N/A ; 145.88 MHz ( period = 6.855 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.146 ns ;
- ; N/A ; 146.56 MHz ( period = 6.823 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.114 ns ;
- ; N/A ; 147.02 MHz ( period = 6.802 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.093 ns ;
- ; N/A ; 147.15 MHz ( period = 6.796 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.087 ns ;
- ; N/A ; 147.21 MHz ( period = 6.793 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.084 ns ;
- ; N/A ; 148.28 MHz ( period = 6.744 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.035 ns ;
- ; N/A ; 148.39 MHz ( period = 6.739 ns ) ; Frequency:inst5|CLK:Count1[9] ; Frequency:inst5|CLK:Count1[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.030 ns ;
- ; N/A ; 149.03 MHz ( period = 6.710 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 6.001 ns ;
- ; N/A ; 149.37 MHz ( period = 6.695 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.986 ns ;
- ; N/A ; 149.48 MHz ( period = 6.690 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.981 ns ;
- ; N/A ; 149.57 MHz ( period = 6.686 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.977 ns ;
- ; N/A ; 150.35 MHz ( period = 6.651 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.942 ns ;
- ; N/A ; 150.58 MHz ( period = 6.641 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.932 ns ;
- ; N/A ; 150.92 MHz ( period = 6.626 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.917 ns ;
- ; N/A ; 151.24 MHz ( period = 6.612 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.903 ns ;
- ; N/A ; 151.58 MHz ( period = 6.597 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.888 ns ;
- ; N/A ; 151.95 MHz ( period = 6.581 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.872 ns ;
- ; N/A ; 152.16 MHz ( period = 6.572 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.863 ns ;
- ; N/A ; 152.21 MHz ( period = 6.570 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.861 ns ;
- ; N/A ; 152.21 MHz ( period = 6.570 ns ) ; Frequency:inst5|CLK:Count1[1] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.861 ns ;
- ; N/A ; 152.53 MHz ( period = 6.556 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.847 ns ;
- ; N/A ; 153.07 MHz ( period = 6.533 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.824 ns ;
- ; N/A ; 153.28 MHz ( period = 6.524 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.815 ns ;
- ; N/A ; 153.85 MHz ( period = 6.500 ns ) ; Frequency:inst5|CLK:Count1[0] ; Frequency:inst5|CLK:Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.791 ns ;
- ; N/A ; 155.35 MHz ( period = 6.437 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.728 ns ;
- ; N/A ; 157.33 MHz ( period = 6.356 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.647 ns ;
- ; N/A ; 157.90 MHz ( period = 6.333 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.624 ns ;
- ; N/A ; 157.93 MHz ( period = 6.332 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.623 ns ;
- ; N/A ; 158.28 MHz ( period = 6.318 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.609 ns ;
- ; N/A ; 158.30 MHz ( period = 6.317 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.608 ns ;
- ; N/A ; 158.88 MHz ( period = 6.294 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.585 ns ;
- ; N/A ; 158.91 MHz ( period = 6.293 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.584 ns ;
- ; N/A ; 158.98 MHz ( period = 6.290 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.581 ns ;
- ; N/A ; 159.08 MHz ( period = 6.286 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.577 ns ;
- ; N/A ; 159.74 MHz ( period = 6.260 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.551 ns ;
- ; N/A ; 160.51 MHz ( period = 6.230 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.521 ns ;
- ; N/A ; 161.86 MHz ( period = 6.178 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.469 ns ;
- ; N/A ; 161.89 MHz ( period = 6.177 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.468 ns ;
- ; N/A ; 163.45 MHz ( period = 6.118 ns ) ; Frequency:inst5|CLK:Count2[7] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.409 ns ;
- ; N/A ; 163.85 MHz ( period = 6.103 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.394 ns ;
- ; N/A ; 164.23 MHz ( period = 6.089 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.380 ns ;
- ; N/A ; 164.28 MHz ( period = 6.087 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.378 ns ;
- ; N/A ; 164.50 MHz ( period = 6.079 ns ) ; Frequency:inst5|CLK:Count1[2] ; Frequency:inst5|CLK:Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.370 ns ;
- ; N/A ; 164.53 MHz ( period = 6.078 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.369 ns ;
- ; N/A ; 164.66 MHz ( period = 6.073 ns ) ; Frequency:inst5|CLK:Count1[9] ; Frequency:inst5|Period1mS ; GCLKP1 ; GCLKP1 ; None ; None ; 5.364 ns ;
- ; N/A ; 164.88 MHz ( period = 6.065 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.356 ns ;
- ; N/A ; 165.15 MHz ( period = 6.055 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.346 ns ;
- ; N/A ; 165.45 MHz ( period = 6.044 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.335 ns ;
- ; N/A ; 165.54 MHz ( period = 6.041 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.332 ns ;
- ; N/A ; 165.56 MHz ( period = 6.040 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.331 ns ;
- ; N/A ; 165.76 MHz ( period = 6.033 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.324 ns ;
- ; N/A ; 166.36 MHz ( period = 6.011 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.302 ns ;
- ; N/A ; 166.56 MHz ( period = 6.004 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.295 ns ;
- ; N/A ; 166.56 MHz ( period = 6.004 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.295 ns ;
- ; N/A ; 166.81 MHz ( period = 5.995 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.286 ns ;
- ; N/A ; 166.92 MHz ( period = 5.991 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.282 ns ;
- ; N/A ; 167.31 MHz ( period = 5.977 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.268 ns ;
- ; N/A ; 168.12 MHz ( period = 5.948 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.239 ns ;
- ; N/A ; 168.15 MHz ( period = 5.947 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.238 ns ;
- ; N/A ; 168.52 MHz ( period = 5.934 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.225 ns ;
- ; N/A ; 168.89 MHz ( period = 5.921 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.212 ns ;
- ; N/A ; 170.77 MHz ( period = 5.856 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.147 ns ;
- ; N/A ; 170.77 MHz ( period = 5.856 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.147 ns ;
- ; N/A ; 170.97 MHz ( period = 5.849 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.140 ns ;
- ; N/A ; 171.03 MHz ( period = 5.847 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.138 ns ;
- ; N/A ; 172.83 MHz ( period = 5.786 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.077 ns ;
- ; N/A ; 173.10 MHz ( period = 5.777 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.068 ns ;
- ; N/A ; 173.25 MHz ( period = 5.772 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.063 ns ;
- ; N/A ; 173.31 MHz ( period = 5.770 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.061 ns ;
- ; N/A ; 173.58 MHz ( period = 5.761 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.052 ns ;
- ; N/A ; 174.43 MHz ( period = 5.733 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.024 ns ;
- ; N/A ; 174.46 MHz ( period = 5.732 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 5.023 ns ;
- ; N/A ; 177.05 MHz ( period = 5.648 ns ) ; Frequency:inst5|CLK:Count2[7] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.939 ns ;
- ; N/A ; 177.30 MHz ( period = 5.640 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.931 ns ;
- ; N/A ; 177.34 MHz ( period = 5.639 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.930 ns ;
- ; N/A ; 178.73 MHz ( period = 5.595 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|ClockScan ; GCLKP1 ; GCLKP1 ; None ; None ; 4.886 ns ;
- ; N/A ; 178.86 MHz ( period = 5.591 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.882 ns ;
- ; N/A ; 179.02 MHz ( period = 5.586 ns ) ; Frequency:inst5|CLK:Count2[4] ; Frequency:inst5|CLK:Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.877 ns ;
- ; N/A ; 179.21 MHz ( period = 5.580 ns ) ; Frequency:inst5|CLK:Count1[9] ; Frequency:inst5|CLK:Count1[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.871 ns ;
- ; N/A ; 179.50 MHz ( period = 5.571 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.862 ns ;
- ; N/A ; 179.53 MHz ( period = 5.570 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.861 ns ;
- ; N/A ; 179.63 MHz ( period = 5.567 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.858 ns ;
- ; N/A ; 179.82 MHz ( period = 5.561 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.852 ns ;
- ; N/A ; 180.18 MHz ( period = 5.550 ns ) ; Frequency:inst5|CLK:Count2[7] ; Frequency:inst5|CLK:Count2[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.841 ns ;
- ; N/A ; 180.34 MHz ( period = 5.545 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.836 ns ;
- ; N/A ; 180.67 MHz ( period = 5.535 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.826 ns ;
- ; N/A ; 180.93 MHz ( period = 5.527 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|ClockScan ; GCLKP1 ; GCLKP1 ; None ; None ; 4.818 ns ;
- ; N/A ; 181.72 MHz ( period = 5.503 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.794 ns ;
- ; N/A ; 181.75 MHz ( period = 5.502 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.793 ns ;
- ; N/A ; 181.79 MHz ( period = 5.501 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.792 ns ;
- ; N/A ; 182.35 MHz ( period = 5.484 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[8] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.775 ns ;
- ; N/A ; 182.52 MHz ( period = 5.479 ns ) ; Frequency:inst5|CLK:Count2[0] ; Frequency:inst5|CLK:Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.770 ns ;
- ; N/A ; 184.09 MHz ( period = 5.432 ns ) ; Frequency:inst5|CLK:Count1[6] ; Frequency:inst5|CLK:Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.723 ns ;
- ; N/A ; 184.81 MHz ( period = 5.411 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.702 ns ;
- ; N/A ; 185.05 MHz ( period = 5.404 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.695 ns ;
- ; N/A ; 185.91 MHz ( period = 5.379 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.670 ns ;
- ; N/A ; 186.85 MHz ( period = 5.352 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.643 ns ;
- ; N/A ; 186.99 MHz ( period = 5.348 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.639 ns ;
- ; N/A ; 187.16 MHz ( period = 5.343 ns ) ; Frequency:inst5|CLK:Count2[7] ; Frequency:inst5|CLK:Count2[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.634 ns ;
- ; N/A ; 187.27 MHz ( period = 5.340 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.631 ns ;
- ; N/A ; 187.48 MHz ( period = 5.334 ns ) ; Frequency:inst5|CLK:Count2[7] ; Frequency:inst5|CLK:Count2[5] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.625 ns ;
- ; N/A ; 187.65 MHz ( period = 5.329 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.620 ns ;
- ; N/A ; 187.76 MHz ( period = 5.326 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|ClockScan ; GCLKP1 ; GCLKP1 ; None ; None ; 4.617 ns ;
- ; N/A ; 187.76 MHz ( period = 5.326 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.617 ns ;
- ; N/A ; 188.04 MHz ( period = 5.318 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.609 ns ;
- ; N/A ; 188.04 MHz ( period = 5.318 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.609 ns ;
- ; N/A ; 188.08 MHz ( period = 5.317 ns ) ; Frequency:inst5|CLK:Count2[6] ; Frequency:inst5|CLK:Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.608 ns ;
- ; N/A ; 188.29 MHz ( period = 5.311 ns ) ; Frequency:inst5|CLK:Count1[7] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.602 ns ;
- ; N/A ; 188.54 MHz ( period = 5.304 ns ) ; Frequency:inst5|CLK:Count2[1] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.595 ns ;
- ; N/A ; 189.50 MHz ( period = 5.277 ns ) ; Frequency:inst5|CLK:Count1[8] ; Frequency:inst5|CLK:Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.568 ns ;
- ; N/A ; 192.72 MHz ( period = 5.189 ns ) ; Frequency:inst5|CLK:Count1[3] ; Frequency:inst5|CLK:Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.480 ns ;
- ; N/A ; 193.27 MHz ( period = 5.174 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.465 ns ;
- ; N/A ; 193.31 MHz ( period = 5.173 ns ) ; Frequency:inst5|CLK:Count1[4] ; Frequency:inst5|CLK:Count1[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.464 ns ;
- ; N/A ; 193.80 MHz ( period = 5.160 ns ) ; Frequency:inst5|CLK:Count2[5] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.451 ns ;
- ; N/A ; 195.43 MHz ( period = 5.117 ns ) ; Frequency:inst5|CLK:Count1[9] ; Frequency:inst5|CLK:Count1[3] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.408 ns ;
- ; N/A ; 195.47 MHz ( period = 5.116 ns ) ; Frequency:inst5|CLK:Count1[9] ; Frequency:inst5|CLK:Count1[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.407 ns ;
- ; N/A ; 198.89 MHz ( period = 5.028 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.319 ns ;
- ; N/A ; 202.39 MHz ( period = 4.941 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[9] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.232 ns ;
- ; N/A ; 203.83 MHz ( period = 4.906 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|ClockScan ; GCLKP1 ; GCLKP1 ; None ; None ; 4.197 ns ;
- ; N/A ; 204.00 MHz ( period = 4.902 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|ClockScan ; GCLKP1 ; GCLKP1 ; None ; None ; 4.193 ns ;
- ; N/A ; 204.21 MHz ( period = 4.897 ns ) ; Frequency:inst5|CLK:Count2[3] ; Frequency:inst5|CLK:Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.188 ns ;
- ; N/A ; 204.37 MHz ( period = 4.893 ns ) ; Frequency:inst5|CLK:Count2[2] ; Frequency:inst5|CLK:Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.184 ns ;
- ; N/A ; 204.92 MHz ( period = 4.880 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|ClockScan ; GCLKP1 ; GCLKP1 ; None ; None ; 4.171 ns ;
- ; N/A ; 205.30 MHz ( period = 4.871 ns ) ; Frequency:inst5|CLK:Count2[8] ; Frequency:inst5|CLK:Count2[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.162 ns ;
- ; N/A ; 206.95 MHz ( period = 4.832 ns ) ; Frequency:inst5|CLK:Count1[5] ; Frequency:inst5|CLK:Count1[0] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.123 ns ;
- ; N/A ; 207.34 MHz ( period = 4.823 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[4] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.114 ns ;
- ; N/A ; 207.81 MHz ( period = 4.812 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[7] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.103 ns ;
- ; N/A ; 207.94 MHz ( period = 4.809 ns ) ; Frequency:inst5|CLK:Count2[9] ; Frequency:inst5|CLK:Count2[2] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.100 ns ;
- ; N/A ; 208.29 MHz ( period = 4.801 ns ) ; Frequency:inst5|CLK:Count2[7] ; Frequency:inst5|CLK:Count2[1] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.092 ns ;
- ; N/A ; 208.55 MHz ( period = 4.795 ns ) ; Frequency:inst5|CLK:Count1[9] ; Frequency:inst5|CLK:Count1[6] ; GCLKP1 ; GCLKP1 ; None ; None ; 4.086 ns ;
- ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
- +-----------------------------------------+-----------------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
- +---------------------------------------------------------------------------------+
- ; tsu ;
- +-------+--------------+------------+--------+-------------------------+----------+
- ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
- +-------+--------------+------------+--------+-------------------------+----------+
- ; N/A ; None ; -0.248 ns ; KBDATA ; PS2VHDL:inst2|spdata[1] ; KBCLK ;
- ; N/A ; None ; -0.254 ns ; KBDATA ; PS2VHDL:inst2|spdata[8] ; KBCLK ;
- ; N/A ; None ; -0.255 ns ; KBDATA ; PS2VHDL:inst2|spdata[5] ; KBCLK ;
- ; N/A ; None ; -0.532 ns ; KBDATA ; PS2VHDL:inst2|spdata[3] ; KBCLK ;
- ; N/A ; None ; -0.534 ns ; KBDATA ; PS2VHDL:inst2|spdata[7] ; KBCLK ;
- ; N/A ; None ; -0.539 ns ; KBDATA ; PS2VHDL:inst2|spdata[6] ; KBCLK ;
- ; N/A ; None ; -0.539 ns ; KBDATA ; PS2VHDL:inst2|spdata[2] ; KBCLK ;
- ; N/A ; None ; -0.540 ns ; KBDATA ; PS2VHDL:inst2|spdata[4] ; KBCLK ;
- +-------+--------------+------------+--------+-------------------------+----------+
- +--------------------------------------------------------------------------------------+
- ; tco ;
- +-------+--------------+------------+-------------------------+-----------+------------+
- ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
- +-------+--------------+------------+-------------------------+-----------+------------+
- ; N/A ; None ; 29.186 ns ; LED4:inst|Refresh[1] ; LEDOUT[6] ; GCLKP1 ;
- ; N/A ; None ; 29.028 ns ; LED4:inst|Refresh[0] ; LEDOUT[6] ; GCLKP1 ;
- ; N/A ; None ; 28.695 ns ; LED4:inst|Refresh[1] ; LEDOUT[1] ; GCLKP1 ;
- ; N/A ; None ; 28.541 ns ; LED4:inst|Refresh[0] ; LEDOUT[1] ; GCLKP1 ;
- ; N/A ; None ; 28.424 ns ; LED4:inst|Refresh[1] ; LEDOUT[2] ; GCLKP1 ;
- ; N/A ; None ; 28.422 ns ; LED4:inst|Refresh[1] ; LEDOUT[4] ; GCLKP1 ;
- ; N/A ; None ; 28.417 ns ; LED4:inst|Refresh[1] ; LEDOUT[3] ; GCLKP1 ;
- ; N/A ; None ; 28.354 ns ; LED4:inst|Refresh[1] ; LEDOUT[5] ; GCLKP1 ;
- ; N/A ; None ; 28.289 ns ; LED4:inst|Refresh[1] ; LEDOUT[0] ; GCLKP1 ;
- ; N/A ; None ; 28.270 ns ; LED4:inst|Refresh[0] ; LEDOUT[2] ; GCLKP1 ;
- ; N/A ; None ; 28.268 ns ; LED4:inst|Refresh[0] ; LEDOUT[4] ; GCLKP1 ;
- ; N/A ; None ; 28.263 ns ; LED4:inst|Refresh[0] ; LEDOUT[3] ; GCLKP1 ;
- ; N/A ; None ; 28.196 ns ; LED4:inst|Refresh[0] ; LEDOUT[5] ; GCLKP1 ;
- ; N/A ; None ; 28.135 ns ; LED4:inst|Refresh[0] ; LEDOUT[0] ; GCLKP1 ;
- ; N/A ; None ; 27.823 ns ; LED4:inst|Refresh[0] ; SELECT[0] ; GCLKP1 ;
- ; N/A ; None ; 27.801 ns ; LED4:inst|Refresh[0] ; SELECT[3] ; GCLKP1 ;
- ; N/A ; None ; 27.787 ns ; LED4:inst|Refresh[0] ; SELECT[1] ; GCLKP1 ;
- ; N/A ; None ; 27.734 ns ; LED4:inst|Refresh[0] ; SELECT[2] ; GCLKP1 ;
- ; N/A ; None ; 27.540 ns ; LED4:inst|Refresh[1] ; SELECT[0] ; GCLKP1 ;
- ; N/A ; None ; 27.519 ns ; LED4:inst|Refresh[1] ; SELECT[3] ; GCLKP1 ;
- ; N/A ; None ; 27.506 ns ; LED4:inst|Refresh[1] ; SELECT[1] ; GCLKP1 ;
- ; N/A ; None ; 27.451 ns ; LED4:inst|Refresh[1] ; SELECT[2] ; GCLKP1 ;
- ; N/A ; None ; 19.143 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 18.608 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 18.312 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 18.308 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 18.036 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 18.030 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 18.027 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 17.960 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 17.899 ns ; PS2VHDL:inst2|spdata[2] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 17.887 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 17.801 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 17.794 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 17.776 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 17.688 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 17.683 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 17.683 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 17.681 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 17.636 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 17.611 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 17.575 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[6] ; KBCLK ;
- ; N/A ; None ; 17.551 ns ; PS2VHDL:inst2|spdata[8] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 17.534 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 17.510 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 17.508 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 17.489 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 17.399 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 17.373 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 17.328 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 17.222 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 17.198 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 17.196 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 17.146 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 17.102 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 17.100 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 17.095 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 17.087 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 17.057 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 17.055 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 17.050 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 16.967 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 16.962 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 16.922 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 16.874 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 16.869 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 16.869 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 16.848 ns ; PS2VHDL:inst2|spdata[3] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 16.803 ns ; PS2VHDL:inst2|spdata[7] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 16.780 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 16.776 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[1] ; KBCLK ;
- ; N/A ; None ; 16.737 ns ; PS2VHDL:inst2|spdata[4] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 16.627 ns ; PS2VHDL:inst2|spdata[1] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 16.504 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[4] ; KBCLK ;
- ; N/A ; None ; 16.498 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[3] ; KBCLK ;
- ; N/A ; None ; 16.495 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[2] ; KBCLK ;
- ; N/A ; None ; 16.367 ns ; PS2VHDL:inst2|spdata[6] ; LEDOUT[0] ; KBCLK ;
- ; N/A ; None ; 16.315 ns ; PS2VHDL:inst2|spdata[5] ; LEDOUT[5] ; KBCLK ;
- ; N/A ; None ; 13.064 ns ; PS2VHDL:inst2|spdata[8] ; LIGHT[7] ; KBCLK ;
- ; N/A ; None ; 12.910 ns ; PS2VHDL:inst2|spdata[2] ; LIGHT[1] ; KBCLK ;
- ; N/A ; None ; 12.547 ns ; PS2VHDL:inst2|spdata[1] ; LIGHT[0] ; KBCLK ;
- ; N/A ; None ; 12.457 ns ; PS2VHDL:inst2|spdata[6] ; LIGHT[5] ; KBCLK ;
- ; N/A ; None ; 12.368 ns ; PS2VHDL:inst2|spdata[5] ; LIGHT[4] ; KBCLK ;
- ; N/A ; None ; 12.310 ns ; PS2VHDL:inst2|spdata[7] ; LIGHT[6] ; KBCLK ;
- ; N/A ; None ; 11.778 ns ; PS2VHDL:inst2|spdata[4] ; LIGHT[3] ; KBCLK ;
- ; N/A ; None ; 11.777 ns ; PS2VHDL:inst2|spdata[3] ; LIGHT[2] ; KBCLK ;
- +-------+--------------+------------+-------------------------+-----------+------------+
- +---------------------------------------------------------------------------------------+
- ; th ;
- +---------------+-------------+-----------+--------+-------------------------+----------+
- ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
- +---------------+-------------+-----------+--------+-------------------------+----------+
- ; N/A ; None ; 1.094 ns ; KBDATA ; PS2VHDL:inst2|spdata[4] ; KBCLK ;
- ; N/A ; None ; 1.093 ns ; KBDATA ; PS2VHDL:inst2|spdata[6] ; KBCLK ;
- ; N/A ; None ; 1.093 ns ; KBDATA ; PS2VHDL:inst2|spdata[2] ; KBCLK ;
- ; N/A ; None ; 1.088 ns ; KBDATA ; PS2VHDL:inst2|spdata[7] ; KBCLK ;
- ; N/A ; None ; 1.086 ns ; KBDATA ; PS2VHDL:inst2|spdata[3] ; KBCLK ;
- ; N/A ; None ; 0.809 ns ; KBDATA ; PS2VHDL:inst2|spdata[5] ; KBCLK ;
- ; N/A ; None ; 0.808 ns ; KBDATA ; PS2VHDL:inst2|spdata[8] ; KBCLK ;
- ; N/A ; None ; 0.802 ns ; KBDATA ; PS2VHDL:inst2|spdata[1] ; KBCLK ;
- +---------------+-------------+-----------+--------+-------------------------+----------+
- +--------------------------+
- ; Timing Analyzer Messages ;
- +--------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Classic Timing Analyzer
- Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
- Info: Processing started: Thu Jun 11 23:51:40 2009
- Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PS2 -c PS2
- Info: Started post-fitting delay annotation
- Info: Delay annotation completed successfully
- Warning: Found pins functioning as undefined clocks and/or memory enables
- Info: Assuming node "KBCLK" is an undefined clock
- Info: Assuming node "GCLKP1" is an undefined clock
- Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
- Info: Detected ripple clock "Frequency:inst5|Period1uS" as buffer
- Info: Detected ripple clock "Frequency:inst5|Period1mS" as buffer
- Info: Detected ripple clock "Frequency:inst5|ClockScan" as buffer
- Info: Clock "KBCLK" has Internal fmax of 207.77 MHz between source register "PS2VHDL:inst2|cnt8[2]" and destination register "PS2VHDL:inst2|spdata[6]" (period= 4.813 ns)
- Info: + Longest register to register delay is 4.104 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y5_N3; Fanout = 12; REG Node = 'PS2VHDL:inst2|cnt8[2]'
- Info: 2: + IC(2.065 ns) + CELL(0.914 ns) = 2.979 ns; Loc. = LC_X6_Y5_N4; Fanout = 1; COMB Node = 'PS2VHDL:inst2|Decoder0~218'
- Info: 3: + IC(0.534 ns) + CELL(0.591 ns) = 4.104 ns; Loc. = LC_X6_Y5_N5; Fanout = 3; REG Node = 'PS2VHDL:inst2|spdata[6]'
- Info: Total cell delay = 1.505 ns ( 36.67 % )
- Info: Total interconnect delay = 2.599 ns ( 63.33 % )
- Info: - Smallest clock skew is 0.000 ns
- Info: + Shortest clock path from clock "KBCLK" to destination register is 7.002 ns
- Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 12; CLK Node = 'KBCLK'
- Info: 2: + IC(4.952 ns) + CELL(0.918 ns) = 7.002 ns; Loc. = LC_X6_Y5_N5; Fanout = 3; REG Node = 'PS2VHDL:inst2|spdata[6]'
- Info: Total cell delay = 2.050 ns ( 29.28 % )
- Info: Total interconnect delay = 4.952 ns ( 70.72 % )
- Info: - Longest clock path from clock "KBCLK" to source register is 7.002 ns
- Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 12; CLK Node = 'KBCLK'
- Info: 2: + IC(4.952 ns) + CELL(0.918 ns) = 7.002 ns; Loc. = LC_X10_Y5_N3; Fanout = 12; REG Node = 'PS2VHDL:inst2|cnt8[2]'
- Info: Total cell delay = 2.050 ns ( 29.28 % )
- Info: Total interconnect delay = 4.952 ns ( 70.72 % )
- Info: + Micro clock to output delay of source is 0.376 ns
- Info: + Micro setup delay of destination is 0.333 ns
- Info: Clock "GCLKP1" has Internal fmax of 119.08 MHz between source register "Frequency:inst5|CLK:Count1[0]" and destination register "Frequency:inst5|CLK:Count1[9]" (period= 8.398 ns)
- Info: + Longest register to register delay is 7.689 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y5_N7; Fanout = 4; REG Node = 'Frequency:inst5|CLK:Count1[0]'
- Info: 2: + IC(2.130 ns) + CELL(0.747 ns) = 2.877 ns; Loc. = LC_X10_Y6_N0; Fanout = 2; COMB Node = 'Frequency:inst5|Add1~660'
- Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.000 ns; Loc. = LC_X10_Y6_N1; Fanout = 2; COMB Node = 'Frequency:inst5|Add1~657'
- Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.123 ns; Loc. = LC_X10_Y6_N2; Fanout = 2; COMB Node = 'Frequency:inst5|Add1~654'
- Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 3.246 ns; Loc. = LC_X10_Y6_N3; Fanout = 2; COMB Node = 'Frequency:inst5|Add1~648'
- Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 3.507 ns; Loc. = LC_X10_Y6_N4; Fanout = 5; COMB Node = 'Frequency:inst5|Add1~651'
- Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 4.482 ns; Loc. = LC_X10_Y6_N9; Fanout = 2; COMB Node = 'Frequency:inst5|Add1~632'
- Info: 8: + IC(1.950 ns) + CELL(0.200 ns) = 6.632 ns; Loc. = LC_X9_Y5_N4; Fanout = 1; COMB Node = 'Frequency:inst5|Add1~634'
- Info: 9: + IC(0.777 ns) + CELL(0.280 ns) = 7.689 ns; Loc. = LC_X9_Y5_N9; Fanout = 2; REG Node = 'Frequency:inst5|CLK:Count1[9]'
- Info: Total cell delay = 2.832 ns ( 36.83 % )
- Info: Total interconnect delay = 4.857 ns ( 63.17 % )
- Info: - Smallest clock skew is 0.000 ns
- Info: + Shortest clock path from clock "GCLKP1" to destination register is 9.164 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 11; REG Node = 'Frequency:inst5|Period1uS'
- Info: 3: + IC(4.189 ns) + CELL(0.918 ns) = 9.164 ns; Loc. = LC_X9_Y5_N9; Fanout = 2; REG Node = 'Frequency:inst5|CLK:Count1[9]'
- Info: Total cell delay = 3.375 ns ( 36.83 % )
- Info: Total interconnect delay = 5.789 ns ( 63.17 % )
- Info: - Longest clock path from clock "GCLKP1" to source register is 9.164 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 11; REG Node = 'Frequency:inst5|Period1uS'
- Info: 3: + IC(4.189 ns) + CELL(0.918 ns) = 9.164 ns; Loc. = LC_X9_Y5_N7; Fanout = 4; REG Node = 'Frequency:inst5|CLK:Count1[0]'
- Info: Total cell delay = 3.375 ns ( 36.83 % )
- Info: Total interconnect delay = 5.789 ns ( 63.17 % )
- Info: + Micro clock to output delay of source is 0.376 ns
- Info: + Micro setup delay of destination is 0.333 ns
- Info: tsu for register "PS2VHDL:inst2|spdata[1]" (data pin = "KBDATA", clock pin = "KBCLK") is -0.248 ns
- Info: + Longest pin to register delay is 6.421 ns
- Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'KBDATA'
- Info: 2: + IC(4.485 ns) + CELL(0.804 ns) = 6.421 ns; Loc. = LC_X10_Y5_N6; Fanout = 3; REG Node = 'PS2VHDL:inst2|spdata[1]'
- Info: Total cell delay = 1.936 ns ( 30.15 % )
- Info: Total interconnect delay = 4.485 ns ( 69.85 % )
- Info: + Micro setup delay of destination is 0.333 ns
- Info: - Shortest clock path from clock "KBCLK" to destination register is 7.002 ns
- Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 12; CLK Node = 'KBCLK'
- Info: 2: + IC(4.952 ns) + CELL(0.918 ns) = 7.002 ns; Loc. = LC_X10_Y5_N6; Fanout = 3; REG Node = 'PS2VHDL:inst2|spdata[1]'
- Info: Total cell delay = 2.050 ns ( 29.28 % )
- Info: Total interconnect delay = 4.952 ns ( 70.72 % )
- Info: tco from clock "GCLKP1" to destination pin "LEDOUT[6]" through register "LED4:inst|Refresh[1]" is 29.186 ns
- Info: + Longest clock path from clock "GCLKP1" to source register is 19.462 ns
- Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'GCLKP1'
- Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 11; REG Node = 'Frequency:inst5|Period1uS'
- Info: 3: + IC(4.189 ns) + CELL(1.294 ns) = 9.540 ns; Loc. = LC_X9_Y5_N4; Fanout = 11; REG Node = 'Frequency:inst5|Period1mS'
- Info: 4: + IC(4.656 ns) + CELL(1.294 ns) = 15.490 ns; Loc. = LC_X12_Y5_N5; Fanout = 2; REG Node = 'Frequency:inst5|ClockScan'
- Info: 5: + IC(3.054 ns) + CELL(0.918 ns) = 19.462 ns; Loc. = LC_X6_Y6_N8; Fanout = 16; REG Node = 'LED4:inst|Refresh[1]'
- Info: Total cell delay = 5.963 ns ( 30.64 % )
- Info: Total interconnect delay = 13.499 ns ( 69.36 % )
- Info: + Micro clock to output delay of source is 0.376 ns
- Info: + Longest register to pin delay is 9.348 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y6_N8; Fanout = 16; REG Node = 'LED4:inst|Refresh[1]'
- Info: 2: + IC(1.510 ns) + CELL(0.200 ns) = 1.710 ns; Loc. = LC_X6_Y6_N6; Fanout = 7; COMB Node = 'LED4:inst|LED[3]~147'
- Info: 3: + IC(0.746 ns) + CELL(0.914 ns) = 3.370 ns; Loc. = LC_X6_Y6_N4; Fanout = 1; COMB Node = 'LED4:inst|Mux0~29'
- Info: 4: + IC(0.796 ns) + CELL(0.511 ns) = 4.677 ns; Loc. = LC_X6_Y6_N0; Fanout = 1; COMB Node = 'LED4:inst|LEDOut[6]~35'
- Info: 5: + IC(2.349 ns) + CELL(2.322 ns) = 9.348 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'LEDOUT[6]'
- Info: Total cell delay = 3.947 ns ( 42.22 % )
- Info: Total interconnect delay = 5.401 ns ( 57.78 % )
- Info: th for register "PS2VHDL:inst2|spdata[4]" (data pin = "KBDATA", clock pin = "KBCLK") is 1.094 ns
- Info: + Longest clock path from clock "KBCLK" to destination register is 7.002 ns
- Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 12; CLK Node = 'KBCLK'
- Info: 2: + IC(4.952 ns) + CELL(0.918 ns) = 7.002 ns; Loc. = LC_X6_Y5_N7; Fanout = 3; REG Node = 'PS2VHDL:inst2|spdata[4]'
- Info: Total cell delay = 2.050 ns ( 29.28 % )
- Info: Total interconnect delay = 4.952 ns ( 70.72 % )
- Info: + Micro hold delay of destination is 0.221 ns
- Info: - Shortest pin to register delay is 6.129 ns
- Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'KBDATA'
- Info: 2: + IC(3.936 ns) + CELL(1.061 ns) = 6.129 ns; Loc. = LC_X6_Y5_N7; Fanout = 3; REG Node = 'PS2VHDL:inst2|spdata[4]'
- Info: Total cell delay = 2.193 ns ( 35.78 % )
- Info: Total interconnect delay = 3.936 ns ( 64.22 % )
- Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 121 megabytes
- Info: Processing ended: Thu Jun 11 23:51:41 2009
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
