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pipe_id.acf
资源名称：mips.rar　[点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：15k
源码类别：

VHDL/FPGA/Verilog

开发平台：

VHDL

pipe_id.acf：源码内容
  1. --
  2. --  Copyright (C) 1988-2000 Altera Corporation
  3. --  Any megafunction design, and related net list (encrypted or decrypted),
  4. --  support information, device programming or simulation file, and any other
  5. --  associated documentation or information provided by Altera or a partner
  6. --  under Altera's Megafunction Partnership Program may be used only to
  7. --  program PLD devices (but not masked PLD devices) from Altera.  Any other
  8. --  use of such megafunction design, net list, support information, device
  9. --  programming or simulation file, or any other related documentation or
  10. --  information is prohibited for any other purpose, including, but not
  11. --  limited to modification, reverse engineering, de-compiling, or use with
  12. --  any other silicon devices, unless such use is explicitly licensed under
  13. --  a separate agreement with Altera or a megafunction partner.  Title to
  14. --  the intellectual property, including patents, copyrights, trademarks,
  15. --  trade secrets, or maskworks, embodied in any such megafunction design,
  16. --  net list, support information, device programming or simulation file, or
  17. --  any other related documentation or information provided by Altera or a
  18. --  megafunction partner, remains with Altera, the megafunction partner, or
  19. --  their respective licensors.  No other licenses, including any licenses
  20. --  needed under any third party's intellectual property, are provided herein.
  21. --
  22. DEFAULT_DEVICES
  23. BEGIN
  24. ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
  25. AUTO_DEVICE = EPF10K10LC84-3;
  26. AUTO_DEVICE = EPF10K10TC144-3;
  27. AUTO_DEVICE = EPF10K10QC208-3;
  28. AUTO_DEVICE = EPF10K20TC144-3;
  29. AUTO_DEVICE = EPF10K20RC208-3;
  30. AUTO_DEVICE = EPF10K20RC240-3;
  31. AUTO_DEVICE = EPF10K30RC208-3;
  32. AUTO_DEVICE = EPF10K30RC240-3;
  33. AUTO_DEVICE = EPF10K30BC356-3;
  34. AUTO_DEVICE = EPF10K40RC208-3;
  35. AUTO_DEVICE = EPF10K40RC240-3;
  36. AUTO_DEVICE = EPF10K50RC240-3;
  37. AUTO_DEVICE = EPF10K50BC356-3;
  38. AUTO_DEVICE = EPF10K70RC240-2;
  39. END;
  41. TIMING_POINT
  42. BEGIN
  43. DEVICE_FOR_TIMING_SYNTHESIS = FLEX10K;
  44. CUT_ALL_BIDIR = ON;
  45. CUT_ALL_CLEAR_PRESET = ON;
  46. MAINTAIN_STABLE_SYNTHESIS = OFF;
  47. END;
  49. IGNORED_ASSIGNMENTS
  50. BEGIN
  51. IGNORE_CLIQUE_ASSIGNMENTS = OFF;
  52. IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
  53. IGNORE_TIMING_ASSIGNMENTS = OFF;
  54. IGNORE_CHIP_ASSIGNMENTS = OFF;
  55. IGNORE_PIN_ASSIGNMENTS = OFF;
  56. IGNORE_LC_ASSIGNMENTS = OFF;
  57. IGNORE_DEVICE_ASSIGNMENTS = OFF;
  58. IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
  59. DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
  60. FIT_IGNORE_TIMING = ON;
  61. END;
  63. GLOBAL_PROJECT_DEVICE_OPTIONS
  64. BEGIN
  65. RESERVED_LCELLS_PERCENT = 0;
  66. RESERVED_PINS_PERCENT = 0;
  67. SECURITY_BIT = OFF;
  68. USER_CLOCK = OFF;
  69. AUTO_RESTART = OFF;
  70. RELEASE_CLEARS = OFF;
  71. ENABLE_DCLK_OUTPUT = OFF;
  72. DISABLE_TIME_OUT = OFF;
  73. CONFIG_SCHEME = ACTIVE_SERIAL;
  74. FLEX8000_ENABLE_JTAG = OFF;
  75. DATA0 = RESERVED_TRI_STATED;
  76. DATA1_TO_DATA7 = UNRESERVED;
  77. nWS_nRS_nCS_CS = UNRESERVED;
  78. RDYnBUSY = UNRESERVED;
  79. RDCLK = UNRESERVED;
  80. SDOUT = RESERVED_DRIVES_OUT;
  81. ADD0_TO_ADD12 = UNRESERVED;
  82. ADD13 = UNRESERVED;
  83. ADD14 = UNRESERVED;
  84. ADD15 = UNRESERVED;
  85. ADD16 = UNRESERVED;
  86. ADD17 = UNRESERVED;
  87. CLKUSR = UNRESERVED;
  88. nCEO = UNRESERVED;
  89. ENABLE_CHIP_WIDE_RESET = OFF;
  90. ENABLE_CHIP_WIDE_OE = OFF;
  91. ENABLE_INIT_DONE_OUTPUT = OFF;
  92. FLEX10K_JTAG_USER_CODE = 7F;
  93. CONFIG_SCHEME_10K = PASSIVE_SERIAL;
  94. MAX7000S_USER_CODE = FFFF;
  95. FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
  96. MAX7000S_ENABLE_JTAG = ON;
  97. MULTIVOLT_IO = OFF;
  98. CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
  99. FLEX6000_ENABLE_JTAG = OFF;
  100. FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  101. FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
  102. FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  103. MAX7000AE_USER_CODE = FFFFFFFF;
  104. MAX7000AE_ENABLE_JTAG = ON;
  105. FLEX_CONFIGURATION_EPROM = AUTO;
  106. CONFIG_EPROM_USER_CODE = FFFFFFFF;
  107. CONFIG_EPROM_PULLUP_RESISTOR = ON;
  108. MAX7000B_VCCIO_IOBANK1 = 3.3V;
  109. MAX7000B_VCCIO_IOBANK2 = 3.3V;
  110. MAX7000B_ENABLE_VREFA = OFF;
  111. MAX7000B_ENABLE_VREFB = OFF;
  112. END;
  114. GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
  115. BEGIN
  116. OPTIMIZE_FOR_SPEED = 5;
  117. MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
  118. AUTO_GLOBAL_CLOCK = ON;
  119. AUTO_GLOBAL_CLEAR = ON;
  120. AUTO_GLOBAL_PRESET = ON;
  121. AUTO_GLOBAL_OE = ON;
  122. AUTO_FAST_IO = OFF;
  123. STYLE = NORMAL;
  124. DEVICE_FAMILY = FLEX10K;
  125. AUTO_REGISTER_PACKING = OFF;
  126. ONE_HOT_STATE_MACHINE_ENCODING = OFF;
  127. AUTO_OPEN_DRAIN_PINS = ON;
  128. AUTO_IMPLEMENT_IN_EAB = OFF;
  129. MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
  130. END;
  132. COMPILER_PROCESSING_CONFIGURATION
  133. BEGIN
  134. DESIGN_DOCTOR = OFF;
  135. DESIGN_DOCTOR_RULES = EPLD;
  136. FUNCTIONAL_SNF_EXTRACTOR = OFF;
  137. TIMING_SNF_EXTRACTOR = ON;
  138. OPTIMIZE_TIMING_SNF = OFF;
  139. LINKED_SNF_EXTRACTOR = OFF;
  140. RPT_FILE_EQUATIONS = ON;
  141. RPT_FILE_HIERARCHY = ON;
  142. RPT_FILE_LCELL_INTERCONNECT = ON;
  143. RPT_FILE_USER_ASSIGNMENTS = ON;
  144. GENERATE_AHDL_TDO_FILE = OFF;
  145. SMART_RECOMPILE = OFF;
  146. FITTER_SETTINGS = NORMAL;
  147. PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
  148. END;
  150. COMPILER_INTERFACES_CONFIGURATION
  151. BEGIN
  152. NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
  153. EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
  154. EDIF_BUS_DELIMITERS = [];
  155. EDIF_FLATTEN_BUS = OFF;
  156. EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
  157. EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
  158. EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
  159. EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
  160. EDIF_OUTPUT_USE_EDC = OFF;
  161. EDIF_INPUT_USE_LMF2 = OFF;
  162. EDIF_INPUT_USE_LMF1 = OFF;
  163. EDIF_OUTPUT_GND = GND;
  164. EDIF_OUTPUT_VCC = VCC;
  165. EDIF_INPUT_GND = GND;
  166. EDIF_INPUT_VCC = VCC;
  167. EDIF_OUTPUT_EDC_FILE = *.edc;
  168. EDIF_INPUT_LMF2 = *.lmf;
  169. EDIF_INPUT_LMF1 = *.lmf;
  170. VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
  171. VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
  172. VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
  173. VHDL_FLATTEN_BUS = OFF;
  174. VERILOG_FLATTEN_BUS = OFF;
  175. EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
  176. VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
  177. VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
  178. VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
  179. EDIF_NETLIST_WRITER = OFF;
  180. EDIF_OUTPUT_VERSION = 200;
  181. XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
  182. XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
  183. XNF_GENERATE_AHDL_TDX_FILE = ON;
  184. VERILOG_NETLIST_WRITER = OFF;
  185. VHDL_NETLIST_WRITER = OFF;
  186. USE_SYNOPSYS_SYNTHESIS = OFF;
  187. SYNOPSYS_COMPILER = DESIGN;
  188. SYNOPSYS_DESIGNWARE = OFF;
  189. SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
  190. SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
  191. SYNOPSYS_MAPPING_EFFORT = MEDIUM;
  192. VHDL_READER_VERSION = VHDL93;
  193. VHDL_WRITER_VERSION = VHDL93;
  194. END;
  196. CUSTOM_DESIGN_DOCTOR_RULES
  197. BEGIN
  198. RIPPLE_CLOCKS = ON;
  199. GATED_CLOCKS = ON;
  200. MULTI_LEVEL_CLOCKS = ON;
  201. MULTI_CLOCK_NETWORKS = ON;
  202. STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
  203. STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
  204. PRESET_CLEAR_NETWORKS = ON;
  205. ASYNCHRONOUS_INPUTS = ON;
  206. DELAY_CHAINS = ON;
  207. RACE_CONDITIONS = ON;
  208. EXPANDER_NETWORKS = ON;
  209. MASTER_RESET = OFF;
  210. END;
  212. SIMULATOR_CONFIGURATION
  213. BEGIN
  214. USE_DEVICE = OFF;
  215. SETUP_HOLD = OFF;
  216. CHECK_OUTPUTS = OFF;
  217. OSCILLATION = OFF;
  218. OSCILLATION_TIME = 0.0ns;
  219. GLITCH = OFF;
  220. GLITCH_TIME = 0.0ns;
  221. START_TIME = 0.0ns;
  222. END_TIME = 0.0ns;
  223. BIDIR_PIN = STRONG;
  224. END;
  226. TIMING_ANALYZER_CONFIGURATION
  227. BEGIN
  228. ANALYSIS_MODE = DELAY_MATRIX;
  229. AUTO_RECALCULATE = OFF;
  230. CUT_OFF_IO_PIN_FEEDBACK = ON;
  231. CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
  232. LIST_ONLY_LONGEST_PATH = ON;
  233. CELL_WIDTH = 18;
  234. DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
  235. INCLUDE_PATHS_GREATER_THAN = OFF;
  236. INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
  237. INCLUDE_PATHS_LESS_THAN = OFF;
  238. INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
  239. REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
  240. LIST_PATH_COUNT = 10;
  241. LIST_PATH_FREQUENCY = 10MHz;
  242. CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
  243. END;
  245. OTHER_CONFIGURATION
  246. BEGIN
  247. EXPLICIT_FAMILY = 1;
  248. COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
  249. ORIGINAL_MAXPLUS2_VERSION = 10.0;
  250. ROW_PINS_PERCENT = 50;
  251. EXP_PER_LCELL_PERCENT = 100;
  252. FAN_IN_PER_LCELL_PERCENT = 100;
  253. LCELLS_PER_ROW_PERCENT = 100;
  254. LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
  255. DEFAULT_9K_EXP_PER_LCELL = 1/2;
  256. FLEX_10K_52_COLUMNS = 40;
  257. LAST_MAXPLUS2_VERSION = 10.0;
  258. END;
  260. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
  261. BEGIN
  262. CASCADE_CHAIN = IGNORE;
  263. CASCADE_CHAIN_LENGTH = -1;
  264. CARRY_CHAIN = IGNORE;
  265. CARRY_CHAIN_LENGTH = -1;
  266. MINIMIZATION = FULL;
  267. SLOW_SLEW_RATE = OFF;
  268. XOR_SYNTHESIS = ON;
  269. TURBO_BIT = OFF;
  270. PARALLEL_EXPANDERS = OFF;
  271. IGNORE_SOFT_BUFFERS = OFF;
  272. FAST_IO = OFF;
  273. SOFT_BUFFER_INSERTION = ON;
  274. DECOMPOSE_GATES = ON;
  275. REDUCE_LOGIC = ON;
  276. DUPLICATE_LOGIC_EXTRACTION = ON;
  277. NOT_GATE_PUSH_BACK = ON;
  278. REFACTORIZATION = ON;
  279. SUBFACTOR_EXTRACTION = ON;
  280. MULTI_LEVEL_FACTORING = ON;
  281. RESYNTHESIZE_NETWORK = ON;
  282. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  283. REGISTER_OPTIMIZATION = ON;
  284. END;
  286. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
  287. BEGIN
  288. CASCADE_CHAIN = IGNORE;
  289. CASCADE_CHAIN_LENGTH = -1;
  290. CARRY_CHAIN = IGNORE;
  291. CARRY_CHAIN_LENGTH = -1;
  292. MINIMIZATION = FULL;
  293. SLOW_SLEW_RATE = OFF;
  294. XOR_SYNTHESIS = ON;
  295. TURBO_BIT = ON;
  296. PARALLEL_EXPANDERS = OFF;
  297. IGNORE_SOFT_BUFFERS = OFF;
  298. FAST_IO = OFF;
  299. SOFT_BUFFER_INSERTION = ON;
  300. DECOMPOSE_GATES = ON;
  301. REDUCE_LOGIC = ON;
  302. DUPLICATE_LOGIC_EXTRACTION = ON;
  303. NOT_GATE_PUSH_BACK = ON;
  304. REFACTORIZATION = ON;
  305. SUBFACTOR_EXTRACTION = ON;
  306. MULTI_LEVEL_FACTORING = ON;
  307. RESYNTHESIZE_NETWORK = ON;
  308. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  309. REGISTER_OPTIMIZATION = ON;
  310. END;
  312. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
  313. BEGIN
  314. CASCADE_CHAIN = IGNORE;
  315. CASCADE_CHAIN_LENGTH = -1;
  316. CARRY_CHAIN = IGNORE;
  317. CARRY_CHAIN_LENGTH = -1;
  318. MINIMIZATION = FULL;
  319. SLOW_SLEW_RATE = OFF;
  320. XOR_SYNTHESIS = OFF;
  321. TURBO_BIT = ON;
  322. PARALLEL_EXPANDERS = OFF;
  323. IGNORE_SOFT_BUFFERS = OFF;
  324. FAST_IO = OFF;
  325. SOFT_BUFFER_INSERTION = ON;
  326. DECOMPOSE_GATES = ON;
  327. REDUCE_LOGIC = OFF;
  328. DUPLICATE_LOGIC_EXTRACTION = OFF;
  329. NOT_GATE_PUSH_BACK = ON;
  330. REFACTORIZATION = OFF;
  331. SUBFACTOR_EXTRACTION = OFF;
  332. MULTI_LEVEL_FACTORING = OFF;
  333. RESYNTHESIZE_NETWORK = ON;
  334. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  335. REGISTER_OPTIMIZATION = OFF;
  336. END;
  338. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
  339. BEGIN
  340. CASCADE_CHAIN = IGNORE;
  341. CASCADE_CHAIN_LENGTH = 2;
  342. CARRY_CHAIN = IGNORE;
  343. CARRY_CHAIN_LENGTH = 32;
  344. MINIMIZATION = FULL;
  345. SLOW_SLEW_RATE = OFF;
  346. XOR_SYNTHESIS = OFF;
  347. TURBO_BIT = OFF;
  348. PARALLEL_EXPANDERS = OFF;
  349. IGNORE_SOFT_BUFFERS = ON;
  350. SOFT_BUFFER_INSERTION = ON;
  351. DECOMPOSE_GATES = ON;
  352. REDUCE_LOGIC = ON;
  353. DUPLICATE_LOGIC_EXTRACTION = ON;
  354. NOT_GATE_PUSH_BACK = ON;
  355. REFACTORIZATION = ON;
  356. SUBFACTOR_EXTRACTION = ON;
  357. MULTI_LEVEL_FACTORING = ON;
  358. RESYNTHESIZE_NETWORK = ON;
  359. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  360. REGISTER_OPTIMIZATION = ON;
  361. END;
  363. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
  364. BEGIN
  365. CASCADE_CHAIN = IGNORE;
  366. CASCADE_CHAIN_LENGTH = -1;
  367. CARRY_CHAIN = IGNORE;
  368. CARRY_CHAIN_LENGTH = -1;
  369. MINIMIZATION = FULL;
  370. SLOW_SLEW_RATE = OFF;
  371. XOR_SYNTHESIS = ON;
  372. TURBO_BIT = OFF;
  373. PARALLEL_EXPANDERS = OFF;
  374. IGNORE_SOFT_BUFFERS = OFF;
  375. FAST_IO = OFF;
  376. SOFT_BUFFER_INSERTION = ON;
  377. DECOMPOSE_GATES = ON;
  378. REDUCE_LOGIC = ON;
  379. DUPLICATE_LOGIC_EXTRACTION = ON;
  380. NOT_GATE_PUSH_BACK = ON;
  381. REFACTORIZATION = OFF;
  382. SUBFACTOR_EXTRACTION = OFF;
  383. MULTI_LEVEL_FACTORING = ON;
  384. RESYNTHESIZE_NETWORK = ON;
  385. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  386. REGISTER_OPTIMIZATION = ON;
  387. END;
  389. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
  390. BEGIN
  391. CASCADE_CHAIN = IGNORE;
  392. CASCADE_CHAIN_LENGTH = -1;
  393. CARRY_CHAIN = IGNORE;
  394. CARRY_CHAIN_LENGTH = -1;
  395. MINIMIZATION = FULL;
  396. SLOW_SLEW_RATE = OFF;
  397. XOR_SYNTHESIS = ON;
  398. TURBO_BIT = ON;
  399. PARALLEL_EXPANDERS = ON;
  400. IGNORE_SOFT_BUFFERS = OFF;
  401. FAST_IO = OFF;
  402. SOFT_BUFFER_INSERTION = ON;
  403. DECOMPOSE_GATES = ON;
  404. REDUCE_LOGIC = ON;
  405. DUPLICATE_LOGIC_EXTRACTION = ON;
  406. NOT_GATE_PUSH_BACK = ON;
  407. REFACTORIZATION = OFF;
  408. SUBFACTOR_EXTRACTION = OFF;
  409. MULTI_LEVEL_FACTORING = ON;
  410. RESYNTHESIZE_NETWORK = ON;
  411. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  412. REGISTER_OPTIMIZATION = ON;
  413. END;
  415. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
  416. BEGIN
  417. CASCADE_CHAIN = IGNORE;
  418. CASCADE_CHAIN_LENGTH = -1;
  419. CARRY_CHAIN = IGNORE;
  420. CARRY_CHAIN_LENGTH = -1;
  421. MINIMIZATION = FULL;
  422. SLOW_SLEW_RATE = OFF;
  423. XOR_SYNTHESIS = OFF;
  424. TURBO_BIT = ON;
  425. PARALLEL_EXPANDERS = OFF;
  426. IGNORE_SOFT_BUFFERS = OFF;
  427. FAST_IO = OFF;
  428. SOFT_BUFFER_INSERTION = ON;
  429. DECOMPOSE_GATES = ON;
  430. REDUCE_LOGIC = OFF;
  431. DUPLICATE_LOGIC_EXTRACTION = OFF;
  432. NOT_GATE_PUSH_BACK = ON;
  433. REFACTORIZATION = OFF;
  434. SUBFACTOR_EXTRACTION = OFF;
  435. MULTI_LEVEL_FACTORING = OFF;
  436. RESYNTHESIZE_NETWORK = ON;
  437. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  438. REGISTER_OPTIMIZATION = OFF;
  439. END;
  441. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
  442. BEGIN
  443. CASCADE_CHAIN = AUTO;
  444. CASCADE_CHAIN_LENGTH = 2;
  445. CARRY_CHAIN = AUTO;
  446. CARRY_CHAIN_LENGTH = 32;
  447. MINIMIZATION = FULL;
  448. SLOW_SLEW_RATE = OFF;
  449. XOR_SYNTHESIS = OFF;
  450. TURBO_BIT = OFF;
  451. PARALLEL_EXPANDERS = OFF;
  452. IGNORE_SOFT_BUFFERS = ON;
  453. SOFT_BUFFER_INSERTION = ON;
  454. DECOMPOSE_GATES = ON;
  455. REDUCE_LOGIC = ON;
  456. DUPLICATE_LOGIC_EXTRACTION = ON;
  457. NOT_GATE_PUSH_BACK = ON;
  458. REFACTORIZATION = OFF;
  459. SUBFACTOR_EXTRACTION = OFF;
  460. MULTI_LEVEL_FACTORING = ON;
  461. RESYNTHESIZE_NETWORK = ON;
  462. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  463. REGISTER_OPTIMIZATION = ON;
  464. END;
  466. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
  467. BEGIN
  468. CASCADE_CHAIN = IGNORE;
  469. CASCADE_CHAIN_LENGTH = -1;
  470. CARRY_CHAIN = IGNORE;
  471. CARRY_CHAIN_LENGTH = -1;
  472. MINIMIZATION = PARTIAL;
  473. SLOW_SLEW_RATE = OFF;
  474. XOR_SYNTHESIS = OFF;
  475. TURBO_BIT = OFF;
  476. PARALLEL_EXPANDERS = OFF;
  477. IGNORE_SOFT_BUFFERS = OFF;
  478. FAST_IO = OFF;
  479. SOFT_BUFFER_INSERTION = OFF;
  480. DECOMPOSE_GATES = OFF;
  481. REDUCE_LOGIC = OFF;
  482. DUPLICATE_LOGIC_EXTRACTION = OFF;
  483. NOT_GATE_PUSH_BACK = ON;
  484. REFACTORIZATION = OFF;
  485. SUBFACTOR_EXTRACTION = OFF;
  486. MULTI_LEVEL_FACTORING = OFF;
  487. RESYNTHESIZE_NETWORK = OFF;
  488. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  489. REGISTER_OPTIMIZATION = OFF;
  490. END;
  492. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
  493. BEGIN
  494. CASCADE_CHAIN = IGNORE;
  495. CASCADE_CHAIN_LENGTH = -1;
  496. CARRY_CHAIN = IGNORE;
  497. CARRY_CHAIN_LENGTH = -1;
  498. MINIMIZATION = PARTIAL;
  499. SLOW_SLEW_RATE = OFF;
  500. XOR_SYNTHESIS = OFF;
  501. TURBO_BIT = ON;
  502. PARALLEL_EXPANDERS = OFF;
  503. IGNORE_SOFT_BUFFERS = OFF;
  504. FAST_IO = OFF;
  505. SOFT_BUFFER_INSERTION = OFF;
  506. DECOMPOSE_GATES = OFF;
  507. REDUCE_LOGIC = OFF;
  508. DUPLICATE_LOGIC_EXTRACTION = OFF;
  509. NOT_GATE_PUSH_BACK = ON;
  510. REFACTORIZATION = OFF;
  511. SUBFACTOR_EXTRACTION = OFF;
  512. MULTI_LEVEL_FACTORING = OFF;
  513. RESYNTHESIZE_NETWORK = OFF;
  514. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  515. REGISTER_OPTIMIZATION = OFF;
  516. END;
  518. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
  519. BEGIN
  520. CASCADE_CHAIN = IGNORE;
  521. CASCADE_CHAIN_LENGTH = -1;
  522. CARRY_CHAIN = IGNORE;
  523. CARRY_CHAIN_LENGTH = -1;
  524. MINIMIZATION = PARTIAL;
  525. SLOW_SLEW_RATE = OFF;
  526. XOR_SYNTHESIS = OFF;
  527. TURBO_BIT = ON;
  528. PARALLEL_EXPANDERS = OFF;
  529. IGNORE_SOFT_BUFFERS = OFF;
  530. FAST_IO = OFF;
  531. SOFT_BUFFER_INSERTION = OFF;
  532. DECOMPOSE_GATES = ON;
  533. REDUCE_LOGIC = OFF;
  534. DUPLICATE_LOGIC_EXTRACTION = OFF;
  535. NOT_GATE_PUSH_BACK = ON;
  536. REFACTORIZATION = OFF;
  537. SUBFACTOR_EXTRACTION = OFF;
  538. MULTI_LEVEL_FACTORING = OFF;
  539. RESYNTHESIZE_NETWORK = ON;
  540. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  541. REGISTER_OPTIMIZATION = OFF;
  542. END;
  544. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
  545. BEGIN
  546. CASCADE_CHAIN = MANUAL;
  547. CASCADE_CHAIN_LENGTH = 2;
  548. CARRY_CHAIN = MANUAL;
  549. CARRY_CHAIN_LENGTH = 32;
  550. MINIMIZATION = PARTIAL;
  551. SLOW_SLEW_RATE = OFF;
  552. XOR_SYNTHESIS = OFF;
  553. TURBO_BIT = OFF;
  554. PARALLEL_EXPANDERS = OFF;
  555. IGNORE_SOFT_BUFFERS = ON;
  556. SOFT_BUFFER_INSERTION = ON;
  557. DECOMPOSE_GATES = OFF;
  558. REDUCE_LOGIC = OFF;
  559. DUPLICATE_LOGIC_EXTRACTION = OFF;
  560. NOT_GATE_PUSH_BACK = ON;
  561. REFACTORIZATION = OFF;
  562. SUBFACTOR_EXTRACTION = OFF;
  563. MULTI_LEVEL_FACTORING = OFF;
  564. RESYNTHESIZE_NETWORK = OFF;
  565. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  566. REGISTER_OPTIMIZATION = OFF;
  567. END;