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equ.rpt
资源名称：mips.rar [点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：18k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Project Information e:doucumentsprojectsmips__1080379086equ.rpt
- MAX+plus II Compiler Report File
- Version 10.0 9/14/2000
- Compiled: 12/12/2008 22:38:36
- Copyright (C) 1988-2000 Altera Corporation
- Any megafunction design, and related net list (encrypted or decrypted),
- support information, device programming or simulation file, and any other
- associated documentation or information provided by Altera or a partner
- under Altera's Megafunction Partnership Program may be used only to
- program PLD devices (but not masked PLD devices) from Altera. Any other
- use of such megafunction design, net list, support information, device
- programming or simulation file, or any other related documentation or
- information is prohibited for any other purpose, including, but not
- limited to modification, reverse engineering, de-compiling, or use with
- any other silicon devices, unless such use is explicitly licensed under
- a separate agreement with Altera or a megafunction partner. Title to
- the intellectual property, including patents, copyrights, trademarks,
- trade secrets, or maskworks, embodied in any such megafunction design,
- net list, support information, device programming or simulation file, or
- any other related documentation or information provided by Altera or a
- megafunction partner, remains with Altera, the megafunction partner, or
- their respective licensors. No other licenses, including any licenses
- needed under any third party's intellectual property, are provided herein.
- ***** Project compilation was successful
- ** DEVICE SUMMARY **
- Chip/ Input Output Bidir Memory Memory LCs
- POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
- equ EPF10K10LC84-3 4 1 0 0 0 % 1 0 %
- User Pins: 4 1 0
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ***** Logic for device 'equ' compiled without errors.
- Device: EPF10K10LC84-3
- FLEX 10K Configuration Scheme: Passive Serial
- Device Options:
- User-Supplied Start-Up Clock = OFF
- Auto-Restart Configuration on Frame Error = OFF
- Release Clears Before Tri-States = OFF
- Enable Chip_Wide Reset = OFF
- Enable Chip-Wide Output Enable = OFF
- Enable INIT_DONE Output = OFF
- JTAG User Code = 7f
- ^
- C
- R R R R R R R R R R R R R O
- E E E E E E E E E E E E E N
- S S S S S S S V S G S G S S S S F
- E E E E E E E C E N E N E E E E _ ^
- R R R R R R R C R D R D R R R R # D n
- V V V V V V V I V a I a V I V V V V T O C
- E E E E E E E N E 2 N 1 E N E E E E C N E
- D D D D D D D T D 1 T 0 D T D D D D K E O
- -----------------------------------------------------------------_
- / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
- ^DATA0 | 12 74 | #TDO
- ^DCLK | 13 73 | RESERVED
- ^nCE | 14 72 | RESERVED
- #TDI | 15 71 | RESERVED
- RESERVED | 16 70 | RESERVED
- RESERVED | 17 69 | RESERVED
- RESERVED | 18 68 | GNDINT
- RESERVED | 19 67 | RESERVED
- VCCINT | 20 66 | RESERVED
- RESERVED | 21 65 | equ
- RESERVED | 22 EPF10K10LC84-3 64 | RESERVED
- RESERVED | 23 63 | VCCINT
- RESERVED | 24 62 | RESERVED
- RESERVED | 25 61 | RESERVED
- GNDINT | 26 60 | RESERVED
- RESERVED | 27 59 | RESERVED
- RESERVED | 28 58 | RESERVED
- RESERVED | 29 57 | #TMS
- RESERVED | 30 56 | #TRST
- ^MSEL0 | 31 55 | ^nSTATUS
- ^MSEL1 | 32 54 | RESERVED
- |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
- ------------------------------------------------------------------
- V ^ R R R R R V G a G a V G R R R R R R R
- C n E E E E E C N 1 N 2 C N E E E E E E E
- C C S S S S S C D 1 D 0 C D S S S S S S S
- I O E E E E E I I I I I E E E E E E E
- N N R R R R R N N N N N R R R R R R R
- T F V V V V V T T T T T V V V V V V V
- I E E E E E E E E E E E E
- G D D D D D D D D D D D D
- N.C. = No Connect. This pin has no internal connection to the device.
- VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
- GNDIO = Dedicated ground pin, which MUST be connected to GND.
- RESERVED = Unused I/O pin, which MUST be left unconnected.
- ^ = Dedicated configuration pin.
- + = Reserved configuration pin, which is tri-stated during user mode.
- * = Reserved configuration pin, which drives out in user mode.
- PDn = Power Down pin.
- @ = Special-purpose pin.
- # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
- & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ** RESOURCE USAGE **
- Logic Column Row
- Array Interconnect Interconnect Clears/ External
- Block Logic Cells Driven Driven Clocks Presets Interconnect
- B14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
- Embedded Column Row
- Array Embedded Interconnect Interconnect Read/ External
- Block Cells Driven Driven Clocks Write Interconnect
- Total dedicated input pins used: 4/6 ( 66%)
- Total I/O pins used: 1/53 ( 1%)
- Total logic cells used: 1/576 ( 0%)
- Total embedded cells used: 0/24 ( 0%)
- Total EABs used: 0/3 ( 0%)
- Average fan-in: 4.00/4 (100%)
- Total fan-in: 4/2304 ( 0%)
- Total input pins required: 4
- Total input I/O cell registers required: 0
- Total output pins required: 1
- Total output I/O cell registers required: 0
- Total buried I/O cell registers required: 0
- Total bidirectional pins required: 0
- Total reserved pins required 0
- Total logic cells required: 1
- Total flipflops required: 0
- Total packed registers required: 0
- Total logic cells in carry chains: 0
- Total number of carry chains: 0
- Total logic cells in cascade chains: 0
- Total number of cascade chains: 0
- Total single-pin Clock Enables required: 0
- Total single-pin Output Enables required: 0
- Synthesized logic cells: 0/ 576 ( 0%)
- Logic Cell and Embedded Cell Counts
- Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
- A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
- B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1/0
- C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
- Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1/0
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ** INPUTS **
- Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 84 - - - -- INPUT 0 0 0 1 a10
- 42 - - - -- INPUT 0 0 0 1 a11
- 44 - - - -- INPUT 0 0 0 1 a20
- 2 - - - -- INPUT 0 0 0 1 a21
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ** OUTPUTS **
- Fed By Fed By Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 65 - - B -- OUTPUT 0 1 0 0 equ
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ** BURIED LOGIC **
- Fan-In Fan-Out
- IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 8 - B 14 OR2 4 0 1 0 :7
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- p = Packed register
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ** FASTTRACK INTERCONNECT UTILIZATION **
- Row FastTrack Interconnect:
- Global Left Half- Right Half-
- FastTrack FastTrack FastTrack
- Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
- A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
- B: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
- C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
- Column FastTrack Interconnect:
- FastTrack
- Column Interconnect Input Pins Output Pins Bidir Pins
- 01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- Device-Specific Information: e:doucumentsprojectsmips__1080379086equ.rpt
- equ
- ** EQUATIONS **
- a10 : INPUT;
- a11 : INPUT;
- a20 : INPUT;
- a21 : INPUT;
- -- Node name is 'equ'
- -- Equation name is 'equ', type is output
- equ = _LC8_B14;
- -- Node name is ':7'
- -- Equation name is '_LC8_B14', type is buried
- _LC8_B14 = LCELL( _EQ001);
- _EQ001 = a10 & a11 & a20 & a21
- # !a10 & a11 & !a20 & a21
- # a10 & !a11 & a20 & !a21
- # !a10 & !a11 & !a20 & !a21;
- Project Information e:doucumentsprojectsmips__1080379086equ.rpt
- ** COMPILATION SETTINGS & TIMES **
- Processing Menu Commands
- ------------------------
- Design Doctor = off
- Logic Synthesis:
- Synthesis Type Used = Multi-Level
- Default Synthesis Style = NORMAL
- Logic option settings in 'NORMAL' style for 'FLEX10K' family
- CARRY_CHAIN = ignore
- CARRY_CHAIN_LENGTH = 32
- CASCADE_CHAIN = ignore
- CASCADE_CHAIN_LENGTH = 2
- DECOMPOSE_GATES = on
- DUPLICATE_LOGIC_EXTRACTION = on
- MINIMIZATION = full
- MULTI_LEVEL_FACTORING = on
- NOT_GATE_PUSH_BACK = on
- REDUCE_LOGIC = on
- REFACTORIZATION = on
- REGISTER_OPTIMIZATION = on
- RESYNTHESIZE_NETWORK = on
- SLOW_SLEW_RATE = off
- SUBFACTOR_EXTRACTION = on
- IGNORE_SOFT_BUFFERS = on
- USE_LPM_FOR_AHDL_OPERATORS = off
- Other logic synthesis settings:
- Automatic Global Clock = on
- Automatic Global Clear = on
- Automatic Global Preset = on
- Automatic Global Output Enable = on
- Automatic Fast I/O = off
- Automatic Register Packing = off
- Automatic Open-Drain Pins = on
- Automatic Implement in EAB = off
- Optimize = 5
- Default Timing Specifications: None
- Cut All Bidir Feedback Timing Paths = on
- Cut All Clear & Preset Timing Paths = on
- Ignore Timing Assignments = on
- Functional SNF Extractor = off
- Linked SNF Extractor = off
- Timing SNF Extractor = on
- Optimize Timing SNF = off
- Generate AHDL TDO File = off
- Fitter Settings = NORMAL
- Use Quartus Fitter = on
- Smart Recompile = off
- Total Recompile = off
- Interfaces Menu Commands
- ------------------------
- EDIF Netlist Writer = off
- Verilog Netlist Writer = off
- VHDL Netlist Writer = off
- Compilation Times
- -----------------
- Compiler Netlist Extractor 00:00:00
- Database Builder 00:00:00
- Logic Synthesizer 00:00:00
- Partitioner 00:00:00
- Fitter 00:00:01
- Timing SNF Extractor 00:00:00
- Assembler 00:00:00
- -------------------------- --------
- Total Time 00:00:01
- Memory Allocated
- -----------------
- Peak memory allocated during compilation = 9,384K
