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dffe8.acf
资源名称：mips.rar　[点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：14k
源码类别：

VHDL/FPGA/Verilog

开发平台：

VHDL

dffe8.acf：源码内容
  1. --
  2. --  Copyright (C) 1988-2000 Altera Corporation
  3. --  Any megafunction design, and related net list (encrypted or decrypted),
  4. --  support information, device programming or simulation file, and any other
  5. --  associated documentation or information provided by Altera or a partner
  6. --  under Altera's Megafunction Partnership Program may be used only to
  7. --  program PLD devices (but not masked PLD devices) from Altera.  Any other
  8. --  use of such megafunction design, net list, support information, device
  9. --  programming or simulation file, or any other related documentation or
  10. --  information is prohibited for any other purpose, including, but not
  11. --  limited to modification, reverse engineering, de-compiling, or use with
  12. --  any other silicon devices, unless such use is explicitly licensed under
  13. --  a separate agreement with Altera or a megafunction partner.  Title to
  14. --  the intellectual property, including patents, copyrights, trademarks,
  15. --  trade secrets, or maskworks, embodied in any such megafunction design,
  16. --  net list, support information, device programming or simulation file, or
  17. --  any other related documentation or information provided by Altera or a
  18. --  megafunction partner, remains with Altera, the megafunction partner, or
  19. --  their respective licensors.  No other licenses, including any licenses
  20. --  needed under any third party's intellectual property, are provided herein.
  21. --
  22. DEFAULT_DEVICES
  23. BEGIN
  24. ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
  25. AUTO_DEVICE = EPF10K10LC84-3;
  26. AUTO_DEVICE = EPF10K10TC144-3;
  27. AUTO_DEVICE = EPF10K10QC208-3;
  28. AUTO_DEVICE = EPF10K20TC144-3;
  29. AUTO_DEVICE = EPF10K20RC208-3;
  30. AUTO_DEVICE = EPF10K20RC240-3;
  31. AUTO_DEVICE = EPF10K30RC208-3;
  32. AUTO_DEVICE = EPF10K30RC240-3;
  33. AUTO_DEVICE = EPF10K30BC356-3;
  34. AUTO_DEVICE = EPF10K40RC208-3;
  35. AUTO_DEVICE = EPF10K40RC240-3;
  36. AUTO_DEVICE = EPF10K50RC240-3;
  37. AUTO_DEVICE = EPF10K50BC356-3;
  38. AUTO_DEVICE = EPF10K70RC240-2;
  39. END;
  41. TIMING_POINT
  42. BEGIN
  43. CUT_ALL_BIDIR = ON;
  44. CUT_ALL_CLEAR_PRESET = ON;
  45. MAINTAIN_STABLE_SYNTHESIS = OFF;
  46. END;
  48. IGNORED_ASSIGNMENTS
  49. BEGIN
  50. IGNORE_CLIQUE_ASSIGNMENTS = OFF;
  51. IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
  52. IGNORE_TIMING_ASSIGNMENTS = OFF;
  53. IGNORE_CHIP_ASSIGNMENTS = OFF;
  54. IGNORE_PIN_ASSIGNMENTS = OFF;
  55. IGNORE_LC_ASSIGNMENTS = OFF;
  56. IGNORE_DEVICE_ASSIGNMENTS = OFF;
  57. IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
  58. DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
  59. FIT_IGNORE_TIMING = ON;
  60. END;
  62. GLOBAL_PROJECT_DEVICE_OPTIONS
  63. BEGIN
  64. RESERVED_LCELLS_PERCENT = 0;
  65. RESERVED_PINS_PERCENT = 0;
  66. SECURITY_BIT = OFF;
  67. USER_CLOCK = OFF;
  68. AUTO_RESTART = OFF;
  69. RELEASE_CLEARS = OFF;
  70. ENABLE_DCLK_OUTPUT = OFF;
  71. DISABLE_TIME_OUT = OFF;
  72. CONFIG_SCHEME = ACTIVE_SERIAL;
  73. FLEX8000_ENABLE_JTAG = OFF;
  74. DATA0 = RESERVED_TRI_STATED;
  75. DATA1_TO_DATA7 = UNRESERVED;
  76. nWS_nRS_nCS_CS = UNRESERVED;
  77. RDYnBUSY = UNRESERVED;
  78. RDCLK = UNRESERVED;
  79. SDOUT = RESERVED_DRIVES_OUT;
  80. ADD0_TO_ADD12 = UNRESERVED;
  81. ADD13 = UNRESERVED;
  82. ADD14 = UNRESERVED;
  83. ADD15 = UNRESERVED;
  84. ADD16 = UNRESERVED;
  85. ADD17 = UNRESERVED;
  86. CLKUSR = UNRESERVED;
  87. nCEO = UNRESERVED;
  88. ENABLE_CHIP_WIDE_RESET = OFF;
  89. ENABLE_CHIP_WIDE_OE = OFF;
  90. ENABLE_INIT_DONE_OUTPUT = OFF;
  91. FLEX10K_JTAG_USER_CODE = 7F;
  92. CONFIG_SCHEME_10K = PASSIVE_SERIAL;
  93. MAX7000S_USER_CODE = FFFF;
  94. FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
  95. MAX7000S_ENABLE_JTAG = ON;
  96. MULTIVOLT_IO = OFF;
  97. CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
  98. FLEX6000_ENABLE_JTAG = OFF;
  99. FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  100. FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
  101. FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  102. MAX7000AE_USER_CODE = FFFFFFFF;
  103. MAX7000AE_ENABLE_JTAG = ON;
  104. FLEX_CONFIGURATION_EPROM = AUTO;
  105. CONFIG_EPROM_USER_CODE = FFFFFFFF;
  106. CONFIG_EPROM_PULLUP_RESISTOR = ON;
  107. MAX7000B_VCCIO_IOBANK1 = 3.3V;
  108. MAX7000B_VCCIO_IOBANK2 = 3.3V;
  109. MAX7000B_ENABLE_VREFA = OFF;
  110. MAX7000B_ENABLE_VREFB = OFF;
  111. END;
  113. GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
  114. BEGIN
  115. OPTIMIZE_FOR_SPEED = 5;
  116. MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
  117. AUTO_GLOBAL_CLOCK = ON;
  118. AUTO_GLOBAL_CLEAR = ON;
  119. AUTO_GLOBAL_PRESET = ON;
  120. AUTO_GLOBAL_OE = ON;
  121. AUTO_FAST_IO = OFF;
  122. STYLE = NORMAL;
  123. DEVICE_FAMILY = FLEX10K;
  124. AUTO_REGISTER_PACKING = OFF;
  125. ONE_HOT_STATE_MACHINE_ENCODING = OFF;
  126. AUTO_OPEN_DRAIN_PINS = ON;
  127. AUTO_IMPLEMENT_IN_EAB = OFF;
  128. MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
  129. END;
  131. COMPILER_PROCESSING_CONFIGURATION
  132. BEGIN
  133. DESIGN_DOCTOR = OFF;
  134. DESIGN_DOCTOR_RULES = EPLD;
  135. FUNCTIONAL_SNF_EXTRACTOR = OFF;
  136. TIMING_SNF_EXTRACTOR = ON;
  137. OPTIMIZE_TIMING_SNF = OFF;
  138. LINKED_SNF_EXTRACTOR = OFF;
  139. RPT_FILE_EQUATIONS = ON;
  140. RPT_FILE_HIERARCHY = ON;
  141. RPT_FILE_LCELL_INTERCONNECT = ON;
  142. RPT_FILE_USER_ASSIGNMENTS = ON;
  143. GENERATE_AHDL_TDO_FILE = OFF;
  144. SMART_RECOMPILE = OFF;
  145. FITTER_SETTINGS = NORMAL;
  146. PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
  147. END;
  149. COMPILER_INTERFACES_CONFIGURATION
  150. BEGIN
  151. EDIF_NETLIST_WRITER = OFF;
  152. EDIF_OUTPUT_VERSION = 200;
  153. XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
  154. XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
  155. XNF_GENERATE_AHDL_TDX_FILE = ON;
  156. VERILOG_NETLIST_WRITER = OFF;
  157. VHDL_NETLIST_WRITER = OFF;
  158. USE_SYNOPSYS_SYNTHESIS = OFF;
  159. SYNOPSYS_COMPILER = DESIGN;
  160. SYNOPSYS_DESIGNWARE = OFF;
  161. SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
  162. SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
  163. SYNOPSYS_MAPPING_EFFORT = MEDIUM;
  164. VHDL_READER_VERSION = VHDL93;
  165. VHDL_WRITER_VERSION = VHDL93;
  166. END;
  168. CUSTOM_DESIGN_DOCTOR_RULES
  169. BEGIN
  170. RIPPLE_CLOCKS = ON;
  171. GATED_CLOCKS = ON;
  172. MULTI_LEVEL_CLOCKS = ON;
  173. MULTI_CLOCK_NETWORKS = ON;
  174. STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
  175. STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
  176. PRESET_CLEAR_NETWORKS = ON;
  177. ASYNCHRONOUS_INPUTS = ON;
  178. DELAY_CHAINS = ON;
  179. RACE_CONDITIONS = ON;
  180. EXPANDER_NETWORKS = ON;
  181. MASTER_RESET = OFF;
  182. END;
  184. SIMULATOR_CONFIGURATION
  185. BEGIN
  186. USE_DEVICE = OFF;
  187. SETUP_HOLD = OFF;
  188. CHECK_OUTPUTS = OFF;
  189. OSCILLATION = OFF;
  190. OSCILLATION_TIME = 0.0ns;
  191. GLITCH = OFF;
  192. GLITCH_TIME = 0.0ns;
  193. START_TIME = 0.0ns;
  194. END_TIME = 0.0ns;
  195. BIDIR_PIN = STRONG;
  196. END;
  198. TIMING_ANALYZER_CONFIGURATION
  199. BEGIN
  200. ANALYSIS_MODE = DELAY_MATRIX;
  201. AUTO_RECALCULATE = OFF;
  202. CUT_OFF_IO_PIN_FEEDBACK = ON;
  203. CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
  204. LIST_ONLY_LONGEST_PATH = ON;
  205. CELL_WIDTH = 18;
  206. DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
  207. INCLUDE_PATHS_GREATER_THAN = OFF;
  208. INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
  209. INCLUDE_PATHS_LESS_THAN = OFF;
  210. INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
  211. REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
  212. LIST_PATH_COUNT = 10;
  213. LIST_PATH_FREQUENCY = 10MHz;
  214. CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
  215. END;
  217. OTHER_CONFIGURATION
  218. BEGIN
  219. EXPLICIT_FAMILY = OFF;
  220. COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
  221. ORIGINAL_MAXPLUS2_VERSION = 10.0;
  222. ROW_PINS_PERCENT = 50;
  223. EXP_PER_LCELL_PERCENT = 100;
  224. FAN_IN_PER_LCELL_PERCENT = 100;
  225. LCELLS_PER_ROW_PERCENT = 100;
  226. LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
  227. DEFAULT_9K_EXP_PER_LCELL = 1/2;
  228. FLEX_10K_52_COLUMNS = 40;
  229. LAST_MAXPLUS2_VERSION = 10.0;
  230. END;
  232. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
  233. BEGIN
  234. CASCADE_CHAIN = IGNORE;
  235. CASCADE_CHAIN_LENGTH = -1;
  236. CARRY_CHAIN = IGNORE;
  237. CARRY_CHAIN_LENGTH = -1;
  238. MINIMIZATION = FULL;
  239. SLOW_SLEW_RATE = OFF;
  240. XOR_SYNTHESIS = ON;
  241. TURBO_BIT = OFF;
  242. PARALLEL_EXPANDERS = OFF;
  243. IGNORE_SOFT_BUFFERS = OFF;
  244. FAST_IO = OFF;
  245. SOFT_BUFFER_INSERTION = ON;
  246. DECOMPOSE_GATES = ON;
  247. REDUCE_LOGIC = ON;
  248. DUPLICATE_LOGIC_EXTRACTION = ON;
  249. NOT_GATE_PUSH_BACK = ON;
  250. REFACTORIZATION = ON;
  251. SUBFACTOR_EXTRACTION = ON;
  252. MULTI_LEVEL_FACTORING = ON;
  253. RESYNTHESIZE_NETWORK = ON;
  254. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  255. REGISTER_OPTIMIZATION = ON;
  256. END;
  258. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
  259. BEGIN
  260. CASCADE_CHAIN = IGNORE;
  261. CASCADE_CHAIN_LENGTH = -1;
  262. CARRY_CHAIN = IGNORE;
  263. CARRY_CHAIN_LENGTH = -1;
  264. MINIMIZATION = FULL;
  265. SLOW_SLEW_RATE = OFF;
  266. XOR_SYNTHESIS = ON;
  267. TURBO_BIT = ON;
  268. PARALLEL_EXPANDERS = OFF;
  269. IGNORE_SOFT_BUFFERS = OFF;
  270. FAST_IO = OFF;
  271. SOFT_BUFFER_INSERTION = ON;
  272. DECOMPOSE_GATES = ON;
  273. REDUCE_LOGIC = ON;
  274. DUPLICATE_LOGIC_EXTRACTION = ON;
  275. NOT_GATE_PUSH_BACK = ON;
  276. REFACTORIZATION = ON;
  277. SUBFACTOR_EXTRACTION = ON;
  278. MULTI_LEVEL_FACTORING = ON;
  279. RESYNTHESIZE_NETWORK = ON;
  280. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  281. REGISTER_OPTIMIZATION = ON;
  282. END;
  284. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
  285. BEGIN
  286. CASCADE_CHAIN = IGNORE;
  287. CASCADE_CHAIN_LENGTH = -1;
  288. CARRY_CHAIN = IGNORE;
  289. CARRY_CHAIN_LENGTH = -1;
  290. MINIMIZATION = FULL;
  291. SLOW_SLEW_RATE = OFF;
  292. XOR_SYNTHESIS = OFF;
  293. TURBO_BIT = ON;
  294. PARALLEL_EXPANDERS = OFF;
  295. IGNORE_SOFT_BUFFERS = OFF;
  296. FAST_IO = OFF;
  297. SOFT_BUFFER_INSERTION = ON;
  298. DECOMPOSE_GATES = ON;
  299. REDUCE_LOGIC = OFF;
  300. DUPLICATE_LOGIC_EXTRACTION = OFF;
  301. NOT_GATE_PUSH_BACK = ON;
  302. REFACTORIZATION = OFF;
  303. SUBFACTOR_EXTRACTION = OFF;
  304. MULTI_LEVEL_FACTORING = OFF;
  305. RESYNTHESIZE_NETWORK = ON;
  306. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  307. REGISTER_OPTIMIZATION = OFF;
  308. END;
  310. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
  311. BEGIN
  312. CASCADE_CHAIN = IGNORE;
  313. CASCADE_CHAIN_LENGTH = 2;
  314. CARRY_CHAIN = IGNORE;
  315. CARRY_CHAIN_LENGTH = 32;
  316. MINIMIZATION = FULL;
  317. SLOW_SLEW_RATE = OFF;
  318. XOR_SYNTHESIS = OFF;
  319. TURBO_BIT = OFF;
  320. PARALLEL_EXPANDERS = OFF;
  321. IGNORE_SOFT_BUFFERS = ON;
  322. SOFT_BUFFER_INSERTION = ON;
  323. DECOMPOSE_GATES = ON;
  324. REDUCE_LOGIC = ON;
  325. DUPLICATE_LOGIC_EXTRACTION = ON;
  326. NOT_GATE_PUSH_BACK = ON;
  327. REFACTORIZATION = ON;
  328. SUBFACTOR_EXTRACTION = ON;
  329. MULTI_LEVEL_FACTORING = ON;
  330. RESYNTHESIZE_NETWORK = ON;
  331. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  332. REGISTER_OPTIMIZATION = ON;
  333. END;
  335. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
  336. BEGIN
  337. CASCADE_CHAIN = IGNORE;
  338. CASCADE_CHAIN_LENGTH = -1;
  339. CARRY_CHAIN = IGNORE;
  340. CARRY_CHAIN_LENGTH = -1;
  341. MINIMIZATION = FULL;
  342. SLOW_SLEW_RATE = OFF;
  343. XOR_SYNTHESIS = ON;
  344. TURBO_BIT = OFF;
  345. PARALLEL_EXPANDERS = OFF;
  346. IGNORE_SOFT_BUFFERS = OFF;
  347. FAST_IO = OFF;
  348. SOFT_BUFFER_INSERTION = ON;
  349. DECOMPOSE_GATES = ON;
  350. REDUCE_LOGIC = ON;
  351. DUPLICATE_LOGIC_EXTRACTION = ON;
  352. NOT_GATE_PUSH_BACK = ON;
  353. REFACTORIZATION = OFF;
  354. SUBFACTOR_EXTRACTION = OFF;
  355. MULTI_LEVEL_FACTORING = ON;
  356. RESYNTHESIZE_NETWORK = ON;
  357. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  358. REGISTER_OPTIMIZATION = ON;
  359. END;
  361. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
  362. BEGIN
  363. CASCADE_CHAIN = IGNORE;
  364. CASCADE_CHAIN_LENGTH = -1;
  365. CARRY_CHAIN = IGNORE;
  366. CARRY_CHAIN_LENGTH = -1;
  367. MINIMIZATION = FULL;
  368. SLOW_SLEW_RATE = OFF;
  369. XOR_SYNTHESIS = ON;
  370. TURBO_BIT = ON;
  371. PARALLEL_EXPANDERS = ON;
  372. IGNORE_SOFT_BUFFERS = OFF;
  373. FAST_IO = OFF;
  374. SOFT_BUFFER_INSERTION = ON;
  375. DECOMPOSE_GATES = ON;
  376. REDUCE_LOGIC = ON;
  377. DUPLICATE_LOGIC_EXTRACTION = ON;
  378. NOT_GATE_PUSH_BACK = ON;
  379. REFACTORIZATION = OFF;
  380. SUBFACTOR_EXTRACTION = OFF;
  381. MULTI_LEVEL_FACTORING = ON;
  382. RESYNTHESIZE_NETWORK = ON;
  383. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  384. REGISTER_OPTIMIZATION = ON;
  385. END;
  387. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
  388. BEGIN
  389. CASCADE_CHAIN = IGNORE;
  390. CASCADE_CHAIN_LENGTH = -1;
  391. CARRY_CHAIN = IGNORE;
  392. CARRY_CHAIN_LENGTH = -1;
  393. MINIMIZATION = FULL;
  394. SLOW_SLEW_RATE = OFF;
  395. XOR_SYNTHESIS = OFF;
  396. TURBO_BIT = ON;
  397. PARALLEL_EXPANDERS = OFF;
  398. IGNORE_SOFT_BUFFERS = OFF;
  399. FAST_IO = OFF;
  400. SOFT_BUFFER_INSERTION = ON;
  401. DECOMPOSE_GATES = ON;
  402. REDUCE_LOGIC = OFF;
  403. DUPLICATE_LOGIC_EXTRACTION = OFF;
  404. NOT_GATE_PUSH_BACK = ON;
  405. REFACTORIZATION = OFF;
  406. SUBFACTOR_EXTRACTION = OFF;
  407. MULTI_LEVEL_FACTORING = OFF;
  408. RESYNTHESIZE_NETWORK = ON;
  409. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  410. REGISTER_OPTIMIZATION = OFF;
  411. END;
  413. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
  414. BEGIN
  415. CASCADE_CHAIN = AUTO;
  416. CASCADE_CHAIN_LENGTH = 2;
  417. CARRY_CHAIN = AUTO;
  418. CARRY_CHAIN_LENGTH = 32;
  419. MINIMIZATION = FULL;
  420. SLOW_SLEW_RATE = OFF;
  421. XOR_SYNTHESIS = OFF;
  422. TURBO_BIT = OFF;
  423. PARALLEL_EXPANDERS = OFF;
  424. IGNORE_SOFT_BUFFERS = ON;
  425. SOFT_BUFFER_INSERTION = ON;
  426. DECOMPOSE_GATES = ON;
  427. REDUCE_LOGIC = ON;
  428. DUPLICATE_LOGIC_EXTRACTION = ON;
  429. NOT_GATE_PUSH_BACK = ON;
  430. REFACTORIZATION = OFF;
  431. SUBFACTOR_EXTRACTION = OFF;
  432. MULTI_LEVEL_FACTORING = ON;
  433. RESYNTHESIZE_NETWORK = ON;
  434. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  435. REGISTER_OPTIMIZATION = ON;
  436. END;
  438. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
  439. BEGIN
  440. CASCADE_CHAIN = IGNORE;
  441. CASCADE_CHAIN_LENGTH = -1;
  442. CARRY_CHAIN = IGNORE;
  443. CARRY_CHAIN_LENGTH = -1;
  444. MINIMIZATION = PARTIAL;
  445. SLOW_SLEW_RATE = OFF;
  446. XOR_SYNTHESIS = OFF;
  447. TURBO_BIT = OFF;
  448. PARALLEL_EXPANDERS = OFF;
  449. IGNORE_SOFT_BUFFERS = OFF;
  450. FAST_IO = OFF;
  451. SOFT_BUFFER_INSERTION = OFF;
  452. DECOMPOSE_GATES = OFF;
  453. REDUCE_LOGIC = OFF;
  454. DUPLICATE_LOGIC_EXTRACTION = OFF;
  455. NOT_GATE_PUSH_BACK = ON;
  456. REFACTORIZATION = OFF;
  457. SUBFACTOR_EXTRACTION = OFF;
  458. MULTI_LEVEL_FACTORING = OFF;
  459. RESYNTHESIZE_NETWORK = OFF;
  460. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  461. REGISTER_OPTIMIZATION = OFF;
  462. END;
  464. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
  465. BEGIN
  466. CASCADE_CHAIN = IGNORE;
  467. CASCADE_CHAIN_LENGTH = -1;
  468. CARRY_CHAIN = IGNORE;
  469. CARRY_CHAIN_LENGTH = -1;
  470. MINIMIZATION = PARTIAL;
  471. SLOW_SLEW_RATE = OFF;
  472. XOR_SYNTHESIS = OFF;
  473. TURBO_BIT = ON;
  474. PARALLEL_EXPANDERS = OFF;
  475. IGNORE_SOFT_BUFFERS = OFF;
  476. FAST_IO = OFF;
  477. SOFT_BUFFER_INSERTION = OFF;
  478. DECOMPOSE_GATES = OFF;
  479. REDUCE_LOGIC = OFF;
  480. DUPLICATE_LOGIC_EXTRACTION = OFF;
  481. NOT_GATE_PUSH_BACK = ON;
  482. REFACTORIZATION = OFF;
  483. SUBFACTOR_EXTRACTION = OFF;
  484. MULTI_LEVEL_FACTORING = OFF;
  485. RESYNTHESIZE_NETWORK = OFF;
  486. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  487. REGISTER_OPTIMIZATION = OFF;
  488. END;
  490. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
  491. BEGIN
  492. CASCADE_CHAIN = IGNORE;
  493. CASCADE_CHAIN_LENGTH = -1;
  494. CARRY_CHAIN = IGNORE;
  495. CARRY_CHAIN_LENGTH = -1;
  496. MINIMIZATION = PARTIAL;
  497. SLOW_SLEW_RATE = OFF;
  498. XOR_SYNTHESIS = OFF;
  499. TURBO_BIT = ON;
  500. PARALLEL_EXPANDERS = OFF;
  501. IGNORE_SOFT_BUFFERS = OFF;
  502. FAST_IO = OFF;
  503. SOFT_BUFFER_INSERTION = OFF;
  504. DECOMPOSE_GATES = ON;
  505. REDUCE_LOGIC = OFF;
  506. DUPLICATE_LOGIC_EXTRACTION = OFF;
  507. NOT_GATE_PUSH_BACK = ON;
  508. REFACTORIZATION = OFF;
  509. SUBFACTOR_EXTRACTION = OFF;
  510. MULTI_LEVEL_FACTORING = OFF;
  511. RESYNTHESIZE_NETWORK = ON;
  512. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  513. REGISTER_OPTIMIZATION = OFF;
  514. END;
  516. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
  517. BEGIN
  518. CASCADE_CHAIN = MANUAL;
  519. CASCADE_CHAIN_LENGTH = 2;
  520. CARRY_CHAIN = MANUAL;
  521. CARRY_CHAIN_LENGTH = 32;
  522. MINIMIZATION = PARTIAL;
  523. SLOW_SLEW_RATE = OFF;
  524. XOR_SYNTHESIS = OFF;
  525. TURBO_BIT = OFF;
  526. PARALLEL_EXPANDERS = OFF;
  527. IGNORE_SOFT_BUFFERS = ON;
  528. SOFT_BUFFER_INSERTION = ON;
  529. DECOMPOSE_GATES = OFF;
  530. REDUCE_LOGIC = OFF;
  531. DUPLICATE_LOGIC_EXTRACTION = OFF;
  532. NOT_GATE_PUSH_BACK = ON;
  533. REFACTORIZATION = OFF;
  534. SUBFACTOR_EXTRACTION = OFF;
  535. MULTI_LEVEL_FACTORING = OFF;
  536. RESYNTHESIZE_NETWORK = OFF;
  537. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  538. REGISTER_OPTIMIZATION = OFF;
  539. END;