pipe_fd_reg.rpt
资源名称:mips.rar [点击查看]
上传用户:huang_5966
上传日期:2022-08-09
资源大小:439k
文件大小:65k
源码类别:
VHDL/FPGA/Verilog
开发平台:
VHDL
- Project Information e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- MAX+plus II Compiler Report File
- Version 10.0 9/14/2000
- Compiled: 12/08/2008 23:27:02
- Copyright (C) 1988-2000 Altera Corporation
- Any megafunction design, and related net list (encrypted or decrypted),
- support information, device programming or simulation file, and any other
- associated documentation or information provided by Altera or a partner
- under Altera's Megafunction Partnership Program may be used only to
- program PLD devices (but not masked PLD devices) from Altera. Any other
- use of such megafunction design, net list, support information, device
- programming or simulation file, or any other related documentation or
- information is prohibited for any other purpose, including, but not
- limited to modification, reverse engineering, de-compiling, or use with
- any other silicon devices, unless such use is explicitly licensed under
- a separate agreement with Altera or a megafunction partner. Title to
- the intellectual property, including patents, copyrights, trademarks,
- trade secrets, or maskworks, embodied in any such megafunction design,
- net list, support information, device programming or simulation file, or
- any other related documentation or information provided by Altera or a
- megafunction partner, remains with Altera, the megafunction partner, or
- their respective licensors. No other licenses, including any licenses
- needed under any third party's intellectual property, are provided herein.
- ***** Project compilation was successful
- ** DEVICE SUMMARY **
- Chip/ Input Output Bidir Memory Memory LCs
- POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
- pipe_fd_reg
- EPF10K10QC208-3 67 64 0 0 0 % 64 11 %
- User Pins: 67 64 0
- Project Information e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- ** FILE HIERARCHY **
- |dffe32:6|
- |dffe32:6|dffe8:5|
- |dffe32:6|dffe8:6|
- |dffe32:6|dffe8:7|
- |dffe32:6|dffe8:8|
- |dffe32:7|
- |dffe32:7|dffe8:5|
- |dffe32:7|dffe8:6|
- |dffe32:7|dffe8:7|
- |dffe32:7|dffe8:8|
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ***** Logic for device 'pipe_fd_reg' compiled without errors.
- Device: EPF10K10QC208-3
- FLEX 10K Configuration Scheme: Passive Serial
- Device Options:
- User-Supplied Start-Up Clock = OFF
- Auto-Restart Configuration on Frame Error = OFF
- Release Clears Before Tri-States = OFF
- Enable Chip_Wide Reset = OFF
- Enable Chip-Wide Output Enable = OFF
- Enable INIT_DONE Output = OFF
- JTAG User Code = 7f
- MultiVolt I/O = OFF
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** ERROR SUMMARY **
- Info: Chip 'pipe_fd_reg' in device 'EPF10K10QC208-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
- R R R
- E E E
- I S S G V I S I I
- I P N I E G I P P E P P V P I P P I G P I N C P I V I N P P G P E I N V I I P N P
- N C S N P I R N N C C R C C C C N C C N N C N D I I I C C N C N P S P C C N P C R N S C N N C S C I P P
- S 4 T S C N V D S F 4 V F F C 4 S 4 4 S D F S I N N N I 4 S C S C T C 4 4 D C F V S T C S S 4 T 4 N C C
- T 1 2 T F S E I 1 2 1 E 2 1 I 2 1 2 2 T I 3 1 N S S S N 1 3 I 1 4 2 4 3 2 I F 2 E 2 1 I 2 T 2 3 1 S F F
- 7 9 2 8 2 8 D O 1 1 6 D 0 5 O 7 9 1 4 6 O 1 2 T 1 2 0 T 4 0 O 6 4 4 6 0 9 O 4 9 D 6 6 O 3 5 5 1 0 9 3 7
- ----------------------------------------------------------------------------------------------------------_
- / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
- / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
- #TCK | 1 156 | ^DATA0
- ^CONF_DONE | 2 155 | ^DCLK
- ^nCEO | 3 154 | ^nCE
- #TDO | 4 153 | #TDI
- VCCIO | 5 152 | GNDIO
- VCCINT | 6 151 | GNDINT
- N.C. | 7 150 | INST26
- N.C. | 8 149 | INS6
- N.C. | 9 148 | PC431
- INST4 | 10 147 | INST0
- INST11 | 11 146 | VCCIO
- INS31 | 12 145 | VCCINT
- INST28 | 13 144 | PCF23
- N.C. | 14 143 | INST23
- N.C. | 15 142 | PCF17
- INS20 | 16 141 | INS4
- PCF27 | 17 140 | N.C.
- INST20 | 18 139 | N.C.
- INST1 | 19 138 | VCCIO
- GNDIO | 20 137 | VCCINT
- GNDINT | 21 136 | INST14
- VCCIO | 22 135 | PCF0
- VCCINT | 23 134 | INST25
- PCF19 | 24 133 | INS24
- PC41 | 25 132 | INST30
- INST10 | 26 131 | INS25
- INST12 | 27 EPF10K10QC208-3 130 | GNDIO
- INST27 | 28 129 | GNDINT
- PC420 | 29 128 | INS14
- INS27 | 30 127 | PCF14
- INST29 | 31 126 | N.C.
- GNDIO | 32 125 | N.C.
- GNDINT | 33 124 | GNDIO
- VCCIO | 34 123 | GNDINT
- VCCINT | 35 122 | INS3
- N.C. | 36 121 | INST2
- N.C. | 37 120 | PCF12
- PC422 | 38 119 | INS15
- PCF16 | 39 118 | VCCIO
- PC48 | 40 117 | VCCINT
- INST18 | 41 116 | PCF22
- VCCIO | 42 115 | INST15
- VCCINT | 43 114 | N.C.
- PC49 | 44 113 | N.C.
- PCF8 | 45 112 | PCF25
- PCF24 | 46 111 | INS13
- PCF5 | 47 110 | VCCIO
- GNDIO | 48 109 | VCCINT
- GNDINT | 49 108 | ^MSEL0
- #TMS | 50 107 | ^MSEL1
- #TRST | 51 106 | VCCINT
- ^nSTATUS | 52 105 | ^nCONFIG
- | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
- 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
- -----------------------------------------------------------------------------------------------------------
- I P I I I P G I I I P P P V I I P P P G I P P V V C C W G G P V P P P P P P G P I P I I I V P P P P I P
- N C N N N C N N N N C C C C N N C C C N N C C C C L L I N N C C C C C C C C N C N C N N N C C C C C N C
- S 4 S S S F D S S S F 4 4 C S S 4 F 4 D S 4 F C C R K R D D 4 C F 4 4 4 F F D 4 S 4 S S S C F 4 4 F S F
- T 1 2 2 1 2 I 2 1 7 1 5 1 I T 2 2 9 2 I T 1 1 I I N I I 0 I 1 2 2 7 6 1 I 1 T 3 1 5 T I 2 1 1 1 T 3
- 3 1 1 9 8 6 O 2 0 1 5 O 1 8 6 O 2 8 8 N N N N O 3 8 3 O 7 1 7 1 O 8 2 3 0 9 0
- 9 1 T T T T 7 3
- N.C. = No Connect. This pin has no internal connection to the device.
- VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
- GNDIO = Dedicated ground pin, which MUST be connected to GND.
- RESERVED = Unused I/O pin, which MUST be left unconnected.
- ^ = Dedicated configuration pin.
- + = Reserved configuration pin, which is tri-stated during user mode.
- * = Reserved configuration pin, which drives out in user mode.
- PDn = Power Down pin.
- @ = Special-purpose pin.
- # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
- & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** RESOURCE USAGE **
- Logic Column Row
- Array Interconnect Interconnect Clears/ External
- Block Logic Cells Driven Driven Clocks Presets Interconnect
- A1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A14 7/ 8( 87%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
- A16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- A18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- A22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- B20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- B23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- C16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%)
- C23 7/ 8( 87%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
- C24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
- Embedded Column Row
- Array Embedded Interconnect Interconnect Read/ External
- Block Cells Driven Driven Clocks Write Interconnect
- Total dedicated input pins used: 6/6 (100%)
- Total I/O pins used: 125/128 ( 97%)
- Total logic cells used: 64/576 ( 11%)
- Total embedded cells used: 0/24 ( 0%)
- Total EABs used: 0/3 ( 0%)
- Average fan-in: 2.00/4 ( 50%)
- Total fan-in: 128/2304 ( 5%)
- Total input pins required: 67
- Total input I/O cell registers required: 0
- Total output pins required: 64
- Total output I/O cell registers required: 0
- Total buried I/O cell registers required: 0
- Total bidirectional pins required: 0
- Total reserved pins required 0
- Total logic cells required: 64
- Total flipflops required: 64
- Total packed registers required: 0
- Total logic cells in carry chains: 0
- Total number of carry chains: 0
- Total logic cells in cascade chains: 0
- Total number of cascade chains: 0
- Total single-pin Clock Enables required: 0
- Total single-pin Output Enables required: 0
- Synthesized logic cells: 0/ 576 ( 0%)
- Logic Cell and Embedded Cell Counts
- Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
- A: 1 1 1 1 1 1 1 1 1 1 0 1 0 1 7 0 1 0 1 0 1 0 1 0 0 23/0
- B: 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 1 0 20/0
- C: 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 1 7 1 21/0
- Total: 3 2 3 2 3 3 3 2 3 3 2 3 0 3 7 1 2 2 2 1 2 1 2 8 1 64/0
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** INPUTS **
- Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 79 - - - -- INPUT G 0 0 0 0 CLK
- 78 - - - -- INPUT G 0 0 0 0 CLRN
- 182 - - - -- INPUT 0 0 0 1 INS0
- 184 - - - -- INPUT 0 0 0 1 INS1
- 183 - - - -- INPUT 0 0 0 1 INS2
- 122 - - C -- INPUT 0 0 0 1 INS3
- 141 - - A -- INPUT 0 0 0 1 INS4
- 96 - - - 05 INPUT 0 0 0 1 INS5
- 149 - - A -- INPUT 0 0 0 1 INS6
- 62 - - - 19 INPUT 0 0 0 1 INS7
- 203 - - - 21 INPUT 0 0 0 1 INS8
- 159 - - - 02 INPUT 0 0 0 1 INS9
- 61 - - - 20 INPUT 0 0 0 1 INS10
- 200 - - - 20 INPUT 0 0 0 1 INS11
- 186 - - - 13 INPUT 0 0 0 1 INS12
- 111 - - C -- INPUT 0 0 0 1 INS13
- 128 - - B -- INPUT 0 0 0 1 INS14
- 119 - - C -- INPUT 0 0 0 1 INS15
- 177 - - - 11 INPUT 0 0 0 1 INS16
- 95 - - - 06 INPUT 0 0 0 1 INS17
- 57 - - - 22 INPUT 0 0 0 1 INS18
- 192 - - - 16 INPUT 0 0 0 1 INS19
- 16 - - A -- INPUT 0 0 0 1 INS20
- 55 - - - 23 INPUT 0 0 0 1 INS21
- 60 - - - 21 INPUT 0 0 0 1 INS22
- 164 - - - 04 INPUT 0 0 0 1 INS23
- 133 - - B -- INPUT 0 0 0 1 INS24
- 131 - - B -- INPUT 0 0 0 1 INS25
- 167 - - - 06 INPUT 0 0 0 1 INS26
- 30 - - B -- INPUT 0 0 0 1 INS27
- 68 - - - 16 INPUT 0 0 0 1 INS28
- 56 - - - 22 INPUT 0 0 0 1 INS29
- 179 - - - 12 INPUT 0 0 0 1 INS30
- 12 - - A -- INPUT 0 0 0 1 INS31
- 83 - - - 12 INPUT 0 0 0 1 PC40
- 25 - - B -- INPUT 0 0 0 1 PC41
- 71 - - - 14 INPUT 0 0 0 1 PC42
- 94 - - - 07 INPUT 0 0 0 1 PC43
- 176 - - - 11 INPUT 0 0 0 1 PC44
- 64 - - - 18 INPUT 0 0 0 1 PC45
- 174 - - - 09 INPUT 0 0 0 1 PC46
- 88 - - - 10 INPUT 0 0 0 1 PC47
- 40 - - C -- INPUT 0 0 0 1 PC48
- 44 - - C -- INPUT 0 0 0 1 PC49
- 160 - - - 02 INPUT 0 0 0 1 PC410
- 54 - - - 24 INPUT 0 0 0 1 PC411
- 100 - - - 03 INPUT 0 0 0 1 PC412
- 101 - - - 03 INPUT 0 0 0 1 PC413
- 180 - - - 12 INPUT 0 0 0 1 PC414
- 65 - - - 18 INPUT 0 0 0 1 PC415
- 198 - - - 19 INPUT 0 0 0 1 PC416
- 92 - - - 08 INPUT 0 0 0 1 PC417
- 74 - - - 13 INPUT 0 0 0 1 PC418
- 207 - - - 24 INPUT 0 0 0 1 PC419
- 29 - - B -- INPUT 0 0 0 1 PC420
- 191 - - - 15 INPUT 0 0 0 1 PC421
- 38 - - C -- INPUT 0 0 0 1 PC422
- 87 - - - 10 INPUT 0 0 0 1 PC423
- 190 - - - 15 INPUT 0 0 0 1 PC424
- 162 - - - 03 INPUT 0 0 0 1 PC425
- 69 - - - 16 INPUT 0 0 0 1 PC426
- 193 - - - 17 INPUT 0 0 0 1 PC427
- 86 - - - 11 INPUT 0 0 0 1 PC428
- 172 - - - 08 INPUT 0 0 0 1 PC429
- 173 - - - 09 INPUT 0 0 0 1 PC430
- 148 - - A -- INPUT 0 0 0 1 PC431
- 80 - - - -- INPUT 0 0 0 64 WIR
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- G = Global Source. Fan-out destinations counted here do not include destinations
- that are driven using global routing resources. Refer to the Auto Global Signals,
- Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
- Sections of this Report File for information on which signals' fan-outs are used as
- Clock, Clear, Preset, Output Enable, and synchronous Load signals.
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** OUTPUTS **
- Fed By Fed By Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 147 - - A -- OUTPUT 0 1 0 0 INST0
- 19 - - A -- OUTPUT 0 1 0 0 INST1
- 121 - - C -- OUTPUT 0 1 0 0 INST2
- 53 - - - 24 OUTPUT 0 1 0 0 INST3
- 10 - - A -- OUTPUT 0 1 0 0 INST4
- 163 - - - 04 OUTPUT 0 1 0 0 INST5
- 189 - - - 14 OUTPUT 0 1 0 0 INST6
- 208 - - - 24 OUTPUT 0 1 0 0 INST7
- 205 - - - 23 OUTPUT 0 1 0 0 INST8
- 103 - - - 01 OUTPUT 0 1 0 0 INST9
- 26 - - B -- OUTPUT 0 1 0 0 INST10
- 11 - - A -- OUTPUT 0 1 0 0 INST11
- 27 - - B -- OUTPUT 0 1 0 0 INST12
- 97 - - - 05 OUTPUT 0 1 0 0 INST13
- 136 - - B -- OUTPUT 0 1 0 0 INST14
- 115 - - C -- OUTPUT 0 1 0 0 INST15
- 166 - - - 05 OUTPUT 0 1 0 0 INST16
- 93 - - - 07 OUTPUT 0 1 0 0 INST17
- 41 - - C -- OUTPUT 0 1 0 0 INST18
- 67 - - - 17 OUTPUT 0 1 0 0 INST19
- 18 - - A -- OUTPUT 0 1 0 0 INST20
- 73 - - - 14 OUTPUT 0 1 0 0 INST21
- 206 - - - 23 OUTPUT 0 1 0 0 INST22
- 143 - - A -- OUTPUT 0 1 0 0 INST23
- 175 - - - 10 OUTPUT 0 1 0 0 INST24
- 134 - - B -- OUTPUT 0 1 0 0 INST25
- 150 - - A -- OUTPUT 0 1 0 0 INST26
- 28 - - B -- OUTPUT 0 1 0 0 INST27
- 13 - - A -- OUTPUT 0 1 0 0 INST28
- 31 - - B -- OUTPUT 0 1 0 0 INST29
- 132 - - B -- OUTPUT 0 1 0 0 INST30
- 161 - - - 03 OUTPUT 0 1 0 0 INST31
- 135 - - B -- OUTPUT 0 1 0 0 PCF0
- 90 - - - 08 OUTPUT 0 1 0 0 PCF1
- 204 - - - 22 OUTPUT 0 1 0 0 PCF2
- 158 - - - 01 OUTPUT 0 1 0 0 PCF3
- 170 - - - 08 OUTPUT 0 1 0 0 PCF4
- 47 - - C -- OUTPUT 0 1 0 0 PCF5
- 89 - - - 09 OUTPUT 0 1 0 0 PCF6
- 157 - - - 01 OUTPUT 0 1 0 0 PCF7
- 45 - - C -- OUTPUT 0 1 0 0 PCF8
- 70 - - - 15 OUTPUT 0 1 0 0 PCF9
- 102 - - - 02 OUTPUT 0 1 0 0 PCF10
- 63 - - - 19 OUTPUT 0 1 0 0 PCF11
- 120 - - C -- OUTPUT 0 1 0 0 PCF12
- 85 - - - 11 OUTPUT 0 1 0 0 PCF13
- 127 - - B -- OUTPUT 0 1 0 0 PCF14
- 195 - - - 17 OUTPUT 0 1 0 0 PCF15
- 39 - - C -- OUTPUT 0 1 0 0 PCF16
- 142 - - A -- OUTPUT 0 1 0 0 PCF17
- 75 - - - 13 OUTPUT 0 1 0 0 PCF18
- 24 - - B -- OUTPUT 0 1 0 0 PCF19
- 196 - - - 18 OUTPUT 0 1 0 0 PCF20
- 199 - - - 20 OUTPUT 0 1 0 0 PCF21
- 116 - - C -- OUTPUT 0 1 0 0 PCF22
- 144 - - A -- OUTPUT 0 1 0 0 PCF23
- 46 - - C -- OUTPUT 0 1 0 0 PCF24
- 112 - - C -- OUTPUT 0 1 0 0 PCF25
- 58 - - - 21 OUTPUT 0 1 0 0 PCF26
- 17 - - A -- OUTPUT 0 1 0 0 PCF27
- 99 - - - 04 OUTPUT 0 1 0 0 PCF28
- 169 - - - 07 OUTPUT 0 1 0 0 PCF29
- 104 - - - 01 OUTPUT 0 1 0 0 PCF30
- 187 - - - 13 OUTPUT 0 1 0 0 PCF31
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** BURIED LOGIC **
- Fan-In Fan-Out
- IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 2 - B 08 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q4 (|dffe32:6|dffe8:5|:7)
- - 2 - B 06 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q0 (|dffe32:6|dffe8:5|:8)
- - 8 - C 13 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q5 (|dffe32:6|dffe8:5|:9)
- - 4 - B 07 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q1 (|dffe32:6|dffe8:5|:10)
- - 2 - A 10 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q6 (|dffe32:6|dffe8:5|:11)
- - 1 - C 22 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q2 (|dffe32:6|dffe8:5|:12)
- - 2 - B 02 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q7 (|dffe32:6|dffe8:5|:13)
- - 4 - A 01 DFFE + 2 0 1 0 |dffe32:6|dffe8:5|Q3 (|dffe32:6|dffe8:5|:14)
- - 2 - C 12 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q4 (|dffe32:6|dffe8:6|:7)
- - 6 - C 23 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q0 (|dffe32:6|dffe8:6|:8)
- - 2 - B 11 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q5 (|dffe32:6|dffe8:6|:9)
- - 4 - C 16 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q1 (|dffe32:6|dffe8:6|:10)
- - 8 - B 10 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q6 (|dffe32:6|dffe8:6|:11)
- - 4 - C 01 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q2 (|dffe32:6|dffe8:6|:12)
- - 2 - A 18 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q7 (|dffe32:6|dffe8:6|:13)
- - 2 - A 20 DFFE + 2 0 1 0 |dffe32:6|dffe8:6|Q3 (|dffe32:6|dffe8:6|:14)
- - 2 - B 18 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q4 (|dffe32:6|dffe8:7|:7)
- - 2 - C 24 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q0 (|dffe32:6|dffe8:7|:8)
- - 2 - B 20 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q5 (|dffe32:6|dffe8:7|:9)
- - 6 - A 06 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q1 (|dffe32:6|dffe8:7|:10)
- - 8 - C 06 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q6 (|dffe32:6|dffe8:7|:11)
- - 7 - A 14 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q2 (|dffe32:6|dffe8:7|:12)
- - 5 - A 09 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q7 (|dffe32:6|dffe8:7|:13)
- - 1 - B 23 DFFE + 2 0 1 0 |dffe32:6|dffe8:7|Q3 (|dffe32:6|dffe8:7|:14)
- - 1 - B 04 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q4 (|dffe32:6|dffe8:8|:7)
- - 7 - C 23 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q0 (|dffe32:6|dffe8:8|:8)
- - 2 - C 07 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q5 (|dffe32:6|dffe8:8|:9)
- - 6 - C 10 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q1 (|dffe32:6|dffe8:8|:10)
- - 2 - A 02 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q6 (|dffe32:6|dffe8:8|:11)
- - 2 - B 21 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q2 (|dffe32:6|dffe8:8|:12)
- - 3 - A 14 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q7 (|dffe32:6|dffe8:8|:13)
- - 5 - A 14 DFFE + 2 0 1 0 |dffe32:6|dffe8:8|Q3 (|dffe32:6|dffe8:8|:14)
- - 1 - A 16 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q4 (|dffe32:7|dffe8:5|:7)
- - 4 - A 12 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q0 (|dffe32:7|dffe8:5|:8)
- - 2 - C 03 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q5 (|dffe32:7|dffe8:5|:9)
- - 8 - A 22 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q1 (|dffe32:7|dffe8:5|:10)
- - 1 - A 14 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q6 (|dffe32:7|dffe8:5|:11)
- - 2 - C 09 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q2 (|dffe32:7|dffe8:5|:12)
- - 8 - C 23 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q7 (|dffe32:7|dffe8:5|:13)
- - 5 - C 23 DFFE + 2 0 1 0 |dffe32:7|dffe8:5|Q3 (|dffe32:7|dffe8:5|:14)
- - 4 - B 15 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q4 (|dffe32:7|dffe8:6|:7)
- - 3 - C 23 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q0 (|dffe32:7|dffe8:6|:8)
- - 1 - C 05 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q5 (|dffe32:7|dffe8:6|:9)
- - 2 - B 01 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q1 (|dffe32:7|dffe8:6|:10)
- - 1 - B 05 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q6 (|dffe32:7|dffe8:6|:11)
- - 3 - B 17 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q2 (|dffe32:7|dffe8:6|:12)
- - 6 - C 11 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q7 (|dffe32:7|dffe8:6|:13)
- - 2 - A 14 DFFE + 2 0 1 0 |dffe32:7|dffe8:6|Q3 (|dffe32:7|dffe8:6|:14)
- - 7 - A 13 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q4 (|dffe32:7|dffe8:7|:7)
- - 1 - A 05 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q0 (|dffe32:7|dffe8:7|:8)
- - 8 - A 14 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q5 (|dffe32:7|dffe8:7|:9)
- - 1 - A 07 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q1 (|dffe32:7|dffe8:7|:10)
- - 1 - C 23 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q6 (|dffe32:7|dffe8:7|:11)
- - 4 - C 23 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q2 (|dffe32:7|dffe8:7|:12)
- - 5 - A 04 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q7 (|dffe32:7|dffe8:7|:13)
- - 1 - C 17 DFFE + 2 0 1 0 |dffe32:7|dffe8:7|Q3 (|dffe32:7|dffe8:7|:14)
- - 4 - A 14 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q4 (|dffe32:7|dffe8:8|:7)
- - 2 - B 09 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q0 (|dffe32:7|dffe8:8|:8)
- - 8 - B 13 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q5 (|dffe32:7|dffe8:8|:9)
- - 2 - B 12 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q1 (|dffe32:7|dffe8:8|:10)
- - 5 - B 03 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q6 (|dffe32:7|dffe8:8|:11)
- - 1 - A 08 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q2 (|dffe32:7|dffe8:8|:12)
- - 1 - A 03 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q7 (|dffe32:7|dffe8:8|:13)
- - 5 - B 19 DFFE + 2 0 1 0 |dffe32:7|dffe8:8|Q3 (|dffe32:7|dffe8:8|:14)
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- p = Packed register
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** FASTTRACK INTERCONNECT UTILIZATION **
- Row FastTrack Interconnect:
- Global Left Half- Right Half-
- FastTrack FastTrack FastTrack
- Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
- A: 7/ 96( 7%) 14/ 48( 29%) 11/ 48( 22%) 5/16( 31%) 11/16( 68%) 0/16( 0%)
- B: 9/ 96( 9%) 11/ 48( 22%) 10/ 48( 20%) 6/16( 37%) 10/16( 62%) 0/16( 0%)
- C: 11/ 96( 11%) 7/ 48( 14%) 12/ 48( 25%) 6/16( 37%) 10/16( 62%) 0/16( 0%)
- Column FastTrack Interconnect:
- FastTrack
- Column Interconnect Input Pins Output Pins Bidir Pins
- 01: 4/24( 16%) 0/4( 0%) 4/4(100%) 0/4( 0%)
- 02: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 03: 4/24( 16%) 3/4( 75%) 1/4( 25%) 0/4( 0%)
- 04: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 05: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 07: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 08: 4/24( 16%) 2/4( 50%) 2/4( 50%) 0/4( 0%)
- 09: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 10: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 11: 4/24( 16%) 3/4( 75%) 1/4( 25%) 0/4( 0%)
- 12: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
- 13: 4/24( 16%) 2/4( 50%) 2/4( 50%) 0/4( 0%)
- 14: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 15: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 16: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
- 17: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 18: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 19: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 20: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 21: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 22: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 23: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 24: 4/24( 16%) 2/4( 50%) 2/4( 50%) 0/4( 0%)
- EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** CLOCK SIGNALS **
- Type Fan-out Name
- INPUT 64 CLK
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** CLEAR SIGNALS **
- Type Fan-out Name
- INPUT 64 CLRN
- Device-Specific Information:e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- pipe_fd_reg
- ** EQUATIONS **
- CLK : INPUT;
- CLRN : INPUT;
- INS0 : INPUT;
- INS1 : INPUT;
- INS2 : INPUT;
- INS3 : INPUT;
- INS4 : INPUT;
- INS5 : INPUT;
- INS6 : INPUT;
- INS7 : INPUT;
- INS8 : INPUT;
- INS9 : INPUT;
- INS10 : INPUT;
- INS11 : INPUT;
- INS12 : INPUT;
- INS13 : INPUT;
- INS14 : INPUT;
- INS15 : INPUT;
- INS16 : INPUT;
- INS17 : INPUT;
- INS18 : INPUT;
- INS19 : INPUT;
- INS20 : INPUT;
- INS21 : INPUT;
- INS22 : INPUT;
- INS23 : INPUT;
- INS24 : INPUT;
- INS25 : INPUT;
- INS26 : INPUT;
- INS27 : INPUT;
- INS28 : INPUT;
- INS29 : INPUT;
- INS30 : INPUT;
- INS31 : INPUT;
- PC40 : INPUT;
- PC41 : INPUT;
- PC42 : INPUT;
- PC43 : INPUT;
- PC44 : INPUT;
- PC45 : INPUT;
- PC46 : INPUT;
- PC47 : INPUT;
- PC48 : INPUT;
- PC49 : INPUT;
- PC410 : INPUT;
- PC411 : INPUT;
- PC412 : INPUT;
- PC413 : INPUT;
- PC414 : INPUT;
- PC415 : INPUT;
- PC416 : INPUT;
- PC417 : INPUT;
- PC418 : INPUT;
- PC419 : INPUT;
- PC420 : INPUT;
- PC421 : INPUT;
- PC422 : INPUT;
- PC423 : INPUT;
- PC424 : INPUT;
- PC425 : INPUT;
- PC426 : INPUT;
- PC427 : INPUT;
- PC428 : INPUT;
- PC429 : INPUT;
- PC430 : INPUT;
- PC431 : INPUT;
- WIR : INPUT;
- -- Node name is 'INST0'
- -- Equation name is 'INST0', type is output
- INST0 = _LC4_A12;
- -- Node name is 'INST1'
- -- Equation name is 'INST1', type is output
- INST1 = _LC8_A22;
- -- Node name is 'INST2'
- -- Equation name is 'INST2', type is output
- INST2 = _LC2_C9;
- -- Node name is 'INST3'
- -- Equation name is 'INST3', type is output
- INST3 = _LC5_C23;
- -- Node name is 'INST4'
- -- Equation name is 'INST4', type is output
- INST4 = _LC1_A16;
- -- Node name is 'INST5'
- -- Equation name is 'INST5', type is output
- INST5 = _LC2_C3;
- -- Node name is 'INST6'
- -- Equation name is 'INST6', type is output
- INST6 = _LC1_A14;
- -- Node name is 'INST7'
- -- Equation name is 'INST7', type is output
- INST7 = _LC8_C23;
- -- Node name is 'INST8'
- -- Equation name is 'INST8', type is output
- INST8 = _LC3_C23;
- -- Node name is 'INST9'
- -- Equation name is 'INST9', type is output
- INST9 = _LC2_B1;
- -- Node name is 'INST10'
- -- Equation name is 'INST10', type is output
- INST10 = _LC3_B17;
- -- Node name is 'INST11'
- -- Equation name is 'INST11', type is output
- INST11 = _LC2_A14;
- -- Node name is 'INST12'
- -- Equation name is 'INST12', type is output
- INST12 = _LC4_B15;
- -- Node name is 'INST13'
- -- Equation name is 'INST13', type is output
- INST13 = _LC1_C5;
- -- Node name is 'INST14'
- -- Equation name is 'INST14', type is output
- INST14 = _LC1_B5;
- -- Node name is 'INST15'
- -- Equation name is 'INST15', type is output
- INST15 = _LC6_C11;
- -- Node name is 'INST16'
- -- Equation name is 'INST16', type is output
- INST16 = _LC1_A5;
- -- Node name is 'INST17'
- -- Equation name is 'INST17', type is output
- INST17 = _LC1_A7;
- -- Node name is 'INST18'
- -- Equation name is 'INST18', type is output
- INST18 = _LC4_C23;
- -- Node name is 'INST19'
- -- Equation name is 'INST19', type is output
- INST19 = _LC1_C17;
- -- Node name is 'INST20'
- -- Equation name is 'INST20', type is output
- INST20 = _LC7_A13;
- -- Node name is 'INST21'
- -- Equation name is 'INST21', type is output
- INST21 = _LC8_A14;
- -- Node name is 'INST22'
- -- Equation name is 'INST22', type is output
- INST22 = _LC1_C23;
- -- Node name is 'INST23'
- -- Equation name is 'INST23', type is output
- INST23 = _LC5_A4;
- -- Node name is 'INST24'
- -- Equation name is 'INST24', type is output
- INST24 = _LC2_B9;
- -- Node name is 'INST25'
- -- Equation name is 'INST25', type is output
- INST25 = _LC2_B12;
- -- Node name is 'INST26'
- -- Equation name is 'INST26', type is output
- INST26 = _LC1_A8;
- -- Node name is 'INST27'
- -- Equation name is 'INST27', type is output
- INST27 = _LC5_B19;
- -- Node name is 'INST28'
- -- Equation name is 'INST28', type is output
- INST28 = _LC4_A14;
- -- Node name is 'INST29'
- -- Equation name is 'INST29', type is output
- INST29 = _LC8_B13;
- -- Node name is 'INST30'
- -- Equation name is 'INST30', type is output
- INST30 = _LC5_B3;
- -- Node name is 'INST31'
- -- Equation name is 'INST31', type is output
- INST31 = _LC1_A3;
- -- Node name is 'PCF0'
- -- Equation name is 'PCF0', type is output
- PCF0 = _LC2_B6;
- -- Node name is 'PCF1'
- -- Equation name is 'PCF1', type is output
- PCF1 = _LC4_B7;
- -- Node name is 'PCF2'
- -- Equation name is 'PCF2', type is output
- PCF2 = _LC1_C22;
- -- Node name is 'PCF3'
- -- Equation name is 'PCF3', type is output
- PCF3 = _LC4_A1;
- -- Node name is 'PCF4'
- -- Equation name is 'PCF4', type is output
- PCF4 = _LC2_B8;
- -- Node name is 'PCF5'
- -- Equation name is 'PCF5', type is output
- PCF5 = _LC8_C13;
- -- Node name is 'PCF6'
- -- Equation name is 'PCF6', type is output
- PCF6 = _LC2_A10;
- -- Node name is 'PCF7'
- -- Equation name is 'PCF7', type is output
- PCF7 = _LC2_B2;
- -- Node name is 'PCF8'
- -- Equation name is 'PCF8', type is output
- PCF8 = _LC6_C23;
- -- Node name is 'PCF9'
- -- Equation name is 'PCF9', type is output
- PCF9 = _LC4_C16;
- -- Node name is 'PCF10'
- -- Equation name is 'PCF10', type is output
- PCF10 = _LC4_C1;
- -- Node name is 'PCF11'
- -- Equation name is 'PCF11', type is output
- PCF11 = _LC2_A20;
- -- Node name is 'PCF12'
- -- Equation name is 'PCF12', type is output
- PCF12 = _LC2_C12;
- -- Node name is 'PCF13'
- -- Equation name is 'PCF13', type is output
- PCF13 = _LC2_B11;
- -- Node name is 'PCF14'
- -- Equation name is 'PCF14', type is output
- PCF14 = _LC8_B10;
- -- Node name is 'PCF15'
- -- Equation name is 'PCF15', type is output
- PCF15 = _LC2_A18;
- -- Node name is 'PCF16'
- -- Equation name is 'PCF16', type is output
- PCF16 = _LC2_C24;
- -- Node name is 'PCF17'
- -- Equation name is 'PCF17', type is output
- PCF17 = _LC6_A6;
- -- Node name is 'PCF18'
- -- Equation name is 'PCF18', type is output
- PCF18 = _LC7_A14;
- -- Node name is 'PCF19'
- -- Equation name is 'PCF19', type is output
- PCF19 = _LC1_B23;
- -- Node name is 'PCF20'
- -- Equation name is 'PCF20', type is output
- PCF20 = _LC2_B18;
- -- Node name is 'PCF21'
- -- Equation name is 'PCF21', type is output
- PCF21 = _LC2_B20;
- -- Node name is 'PCF22'
- -- Equation name is 'PCF22', type is output
- PCF22 = _LC8_C6;
- -- Node name is 'PCF23'
- -- Equation name is 'PCF23', type is output
- PCF23 = _LC5_A9;
- -- Node name is 'PCF24'
- -- Equation name is 'PCF24', type is output
- PCF24 = _LC7_C23;
- -- Node name is 'PCF25'
- -- Equation name is 'PCF25', type is output
- PCF25 = _LC6_C10;
- -- Node name is 'PCF26'
- -- Equation name is 'PCF26', type is output
- PCF26 = _LC2_B21;
- -- Node name is 'PCF27'
- -- Equation name is 'PCF27', type is output
- PCF27 = _LC5_A14;
- -- Node name is 'PCF28'
- -- Equation name is 'PCF28', type is output
- PCF28 = _LC1_B4;
- -- Node name is 'PCF29'
- -- Equation name is 'PCF29', type is output
- PCF29 = _LC2_C7;
- -- Node name is 'PCF30'
- -- Equation name is 'PCF30', type is output
- PCF30 = _LC2_A2;
- -- Node name is 'PCF31'
- -- Equation name is 'PCF31', type is output
- PCF31 = _LC3_A14;
- -- Node name is '|dffe32:6|dffe8:5|:8' = '|dffe32:6|dffe8:5|Q0'
- -- Equation name is '_LC2_B6', type is buried
- _LC2_B6 = DFFE( PC40, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:10' = '|dffe32:6|dffe8:5|Q1'
- -- Equation name is '_LC4_B7', type is buried
- _LC4_B7 = DFFE( PC41, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:12' = '|dffe32:6|dffe8:5|Q2'
- -- Equation name is '_LC1_C22', type is buried
- _LC1_C22 = DFFE( PC42, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:14' = '|dffe32:6|dffe8:5|Q3'
- -- Equation name is '_LC4_A1', type is buried
- _LC4_A1 = DFFE( PC43, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:7' = '|dffe32:6|dffe8:5|Q4'
- -- Equation name is '_LC2_B8', type is buried
- _LC2_B8 = DFFE( PC44, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:9' = '|dffe32:6|dffe8:5|Q5'
- -- Equation name is '_LC8_C13', type is buried
- _LC8_C13 = DFFE( PC45, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:11' = '|dffe32:6|dffe8:5|Q6'
- -- Equation name is '_LC2_A10', type is buried
- _LC2_A10 = DFFE( PC46, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:5|:13' = '|dffe32:6|dffe8:5|Q7'
- -- Equation name is '_LC2_B2', type is buried
- _LC2_B2 = DFFE( PC47, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:8' = '|dffe32:6|dffe8:6|Q0'
- -- Equation name is '_LC6_C23', type is buried
- _LC6_C23 = DFFE( PC48, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:10' = '|dffe32:6|dffe8:6|Q1'
- -- Equation name is '_LC4_C16', type is buried
- _LC4_C16 = DFFE( PC49, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:12' = '|dffe32:6|dffe8:6|Q2'
- -- Equation name is '_LC4_C1', type is buried
- _LC4_C1 = DFFE( PC410, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:14' = '|dffe32:6|dffe8:6|Q3'
- -- Equation name is '_LC2_A20', type is buried
- _LC2_A20 = DFFE( PC411, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:7' = '|dffe32:6|dffe8:6|Q4'
- -- Equation name is '_LC2_C12', type is buried
- _LC2_C12 = DFFE( PC412, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:9' = '|dffe32:6|dffe8:6|Q5'
- -- Equation name is '_LC2_B11', type is buried
- _LC2_B11 = DFFE( PC413, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:11' = '|dffe32:6|dffe8:6|Q6'
- -- Equation name is '_LC8_B10', type is buried
- _LC8_B10 = DFFE( PC414, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:6|:13' = '|dffe32:6|dffe8:6|Q7'
- -- Equation name is '_LC2_A18', type is buried
- _LC2_A18 = DFFE( PC415, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:8' = '|dffe32:6|dffe8:7|Q0'
- -- Equation name is '_LC2_C24', type is buried
- _LC2_C24 = DFFE( PC416, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:10' = '|dffe32:6|dffe8:7|Q1'
- -- Equation name is '_LC6_A6', type is buried
- _LC6_A6 = DFFE( PC417, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:12' = '|dffe32:6|dffe8:7|Q2'
- -- Equation name is '_LC7_A14', type is buried
- _LC7_A14 = DFFE( PC418, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:14' = '|dffe32:6|dffe8:7|Q3'
- -- Equation name is '_LC1_B23', type is buried
- _LC1_B23 = DFFE( PC419, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:7' = '|dffe32:6|dffe8:7|Q4'
- -- Equation name is '_LC2_B18', type is buried
- _LC2_B18 = DFFE( PC420, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:9' = '|dffe32:6|dffe8:7|Q5'
- -- Equation name is '_LC2_B20', type is buried
- _LC2_B20 = DFFE( PC421, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:11' = '|dffe32:6|dffe8:7|Q6'
- -- Equation name is '_LC8_C6', type is buried
- _LC8_C6 = DFFE( PC422, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:7|:13' = '|dffe32:6|dffe8:7|Q7'
- -- Equation name is '_LC5_A9', type is buried
- _LC5_A9 = DFFE( PC423, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:8' = '|dffe32:6|dffe8:8|Q0'
- -- Equation name is '_LC7_C23', type is buried
- _LC7_C23 = DFFE( PC424, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:10' = '|dffe32:6|dffe8:8|Q1'
- -- Equation name is '_LC6_C10', type is buried
- _LC6_C10 = DFFE( PC425, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:12' = '|dffe32:6|dffe8:8|Q2'
- -- Equation name is '_LC2_B21', type is buried
- _LC2_B21 = DFFE( PC426, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:14' = '|dffe32:6|dffe8:8|Q3'
- -- Equation name is '_LC5_A14', type is buried
- _LC5_A14 = DFFE( PC427, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:7' = '|dffe32:6|dffe8:8|Q4'
- -- Equation name is '_LC1_B4', type is buried
- _LC1_B4 = DFFE( PC428, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:9' = '|dffe32:6|dffe8:8|Q5'
- -- Equation name is '_LC2_C7', type is buried
- _LC2_C7 = DFFE( PC429, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:11' = '|dffe32:6|dffe8:8|Q6'
- -- Equation name is '_LC2_A2', type is buried
- _LC2_A2 = DFFE( PC430, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:6|dffe8:8|:13' = '|dffe32:6|dffe8:8|Q7'
- -- Equation name is '_LC3_A14', type is buried
- _LC3_A14 = DFFE( PC431, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:8' = '|dffe32:7|dffe8:5|Q0'
- -- Equation name is '_LC4_A12', type is buried
- _LC4_A12 = DFFE( INS0, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:10' = '|dffe32:7|dffe8:5|Q1'
- -- Equation name is '_LC8_A22', type is buried
- _LC8_A22 = DFFE( INS1, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:12' = '|dffe32:7|dffe8:5|Q2'
- -- Equation name is '_LC2_C9', type is buried
- _LC2_C9 = DFFE( INS2, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:14' = '|dffe32:7|dffe8:5|Q3'
- -- Equation name is '_LC5_C23', type is buried
- _LC5_C23 = DFFE( INS3, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:7' = '|dffe32:7|dffe8:5|Q4'
- -- Equation name is '_LC1_A16', type is buried
- _LC1_A16 = DFFE( INS4, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:9' = '|dffe32:7|dffe8:5|Q5'
- -- Equation name is '_LC2_C3', type is buried
- _LC2_C3 = DFFE( INS5, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:11' = '|dffe32:7|dffe8:5|Q6'
- -- Equation name is '_LC1_A14', type is buried
- _LC1_A14 = DFFE( INS6, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:5|:13' = '|dffe32:7|dffe8:5|Q7'
- -- Equation name is '_LC8_C23', type is buried
- _LC8_C23 = DFFE( INS7, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:8' = '|dffe32:7|dffe8:6|Q0'
- -- Equation name is '_LC3_C23', type is buried
- _LC3_C23 = DFFE( INS8, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:10' = '|dffe32:7|dffe8:6|Q1'
- -- Equation name is '_LC2_B1', type is buried
- _LC2_B1 = DFFE( INS9, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:12' = '|dffe32:7|dffe8:6|Q2'
- -- Equation name is '_LC3_B17', type is buried
- _LC3_B17 = DFFE( INS10, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:14' = '|dffe32:7|dffe8:6|Q3'
- -- Equation name is '_LC2_A14', type is buried
- _LC2_A14 = DFFE( INS11, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:7' = '|dffe32:7|dffe8:6|Q4'
- -- Equation name is '_LC4_B15', type is buried
- _LC4_B15 = DFFE( INS12, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:9' = '|dffe32:7|dffe8:6|Q5'
- -- Equation name is '_LC1_C5', type is buried
- _LC1_C5 = DFFE( INS13, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:11' = '|dffe32:7|dffe8:6|Q6'
- -- Equation name is '_LC1_B5', type is buried
- _LC1_B5 = DFFE( INS14, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:6|:13' = '|dffe32:7|dffe8:6|Q7'
- -- Equation name is '_LC6_C11', type is buried
- _LC6_C11 = DFFE( INS15, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:8' = '|dffe32:7|dffe8:7|Q0'
- -- Equation name is '_LC1_A5', type is buried
- _LC1_A5 = DFFE( INS16, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:10' = '|dffe32:7|dffe8:7|Q1'
- -- Equation name is '_LC1_A7', type is buried
- _LC1_A7 = DFFE( INS17, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:12' = '|dffe32:7|dffe8:7|Q2'
- -- Equation name is '_LC4_C23', type is buried
- _LC4_C23 = DFFE( INS18, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:14' = '|dffe32:7|dffe8:7|Q3'
- -- Equation name is '_LC1_C17', type is buried
- _LC1_C17 = DFFE( INS19, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:7' = '|dffe32:7|dffe8:7|Q4'
- -- Equation name is '_LC7_A13', type is buried
- _LC7_A13 = DFFE( INS20, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:9' = '|dffe32:7|dffe8:7|Q5'
- -- Equation name is '_LC8_A14', type is buried
- _LC8_A14 = DFFE( INS21, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:11' = '|dffe32:7|dffe8:7|Q6'
- -- Equation name is '_LC1_C23', type is buried
- _LC1_C23 = DFFE( INS22, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:7|:13' = '|dffe32:7|dffe8:7|Q7'
- -- Equation name is '_LC5_A4', type is buried
- _LC5_A4 = DFFE( INS23, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:8' = '|dffe32:7|dffe8:8|Q0'
- -- Equation name is '_LC2_B9', type is buried
- _LC2_B9 = DFFE( INS24, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:10' = '|dffe32:7|dffe8:8|Q1'
- -- Equation name is '_LC2_B12', type is buried
- _LC2_B12 = DFFE( INS25, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:12' = '|dffe32:7|dffe8:8|Q2'
- -- Equation name is '_LC1_A8', type is buried
- _LC1_A8 = DFFE( INS26, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:14' = '|dffe32:7|dffe8:8|Q3'
- -- Equation name is '_LC5_B19', type is buried
- _LC5_B19 = DFFE( INS27, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:7' = '|dffe32:7|dffe8:8|Q4'
- -- Equation name is '_LC4_A14', type is buried
- _LC4_A14 = DFFE( INS28, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:9' = '|dffe32:7|dffe8:8|Q5'
- -- Equation name is '_LC8_B13', type is buried
- _LC8_B13 = DFFE( INS29, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:11' = '|dffe32:7|dffe8:8|Q6'
- -- Equation name is '_LC5_B3', type is buried
- _LC5_B3 = DFFE( INS30, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- -- Node name is '|dffe32:7|dffe8:8|:13' = '|dffe32:7|dffe8:8|Q7'
- -- Equation name is '_LC1_A3', type is buried
- _LC1_A3 = DFFE( INS31, GLOBAL( CLK), GLOBAL( CLRN), VCC, WIR);
- Project Information e:doucumentsprojectsmips_1080379086pipe_fd_reg.rpt
- ** COMPILATION SETTINGS & TIMES **
- Processing Menu Commands
- ------------------------
- Design Doctor = off
- Logic Synthesis:
- Synthesis Type Used = Multi-Level
- Default Synthesis Style = NORMAL
- Logic option settings in 'NORMAL' style for 'FLEX10K' family
- CARRY_CHAIN = ignore
- CARRY_CHAIN_LENGTH = 32
- CASCADE_CHAIN = ignore
- CASCADE_CHAIN_LENGTH = 2
- DECOMPOSE_GATES = on
- DUPLICATE_LOGIC_EXTRACTION = on
- MINIMIZATION = full
- MULTI_LEVEL_FACTORING = on
- NOT_GATE_PUSH_BACK = on
- REDUCE_LOGIC = on
- REFACTORIZATION = on
- REGISTER_OPTIMIZATION = on
- RESYNTHESIZE_NETWORK = on
- SLOW_SLEW_RATE = off
- SUBFACTOR_EXTRACTION = on
- IGNORE_SOFT_BUFFERS = on
- USE_LPM_FOR_AHDL_OPERATORS = off
- Other logic synthesis settings:
- Automatic Global Clock = on
- Automatic Global Clear = on
- Automatic Global Preset = on
- Automatic Global Output Enable = on
- Automatic Fast I/O = off
- Automatic Register Packing = off
- Automatic Open-Drain Pins = on
- Automatic Implement in EAB = off
- Optimize = 5
- Default Timing Specifications: None
- Cut All Bidir Feedback Timing Paths = on
- Cut All Clear & Preset Timing Paths = on
- Ignore Timing Assignments = on
- Functional SNF Extractor = off
- Linked SNF Extractor = off
- Timing SNF Extractor = on
- Optimize Timing SNF = off
- Generate AHDL TDO File = off
- Fitter Settings = NORMAL
- Use Quartus Fitter = on
- Smart Recompile = off
- Total Recompile = off
- Interfaces Menu Commands
- ------------------------
- EDIF Netlist Writer = off
- Verilog Netlist Writer = off
- VHDL Netlist Writer = off
- Compilation Times
- -----------------
- Compiler Netlist Extractor 00:00:00
- Database Builder 00:00:00
- Logic Synthesizer 00:00:00
- Partitioner 00:00:00
- Fitter 00:00:01
- Timing SNF Extractor 00:00:00
- Assembler 00:00:00
- -------------------------- --------
- Total Time 00:00:01
- Memory Allocated
- -----------------
- Peak memory allocated during compilation = 10,772K