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reg32x8.acf
资源名称：mips.rar　[点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：14k
源码类别：

VHDL/FPGA/Verilog

开发平台：

VHDL

reg32x8.acf：源码内容
  1. --
  2. --  Copyright (C) 1988-2000 Altera Corporation
  3. --  Any megafunction design, and related net list (encrypted or decrypted),
  4. --  support information, device programming or simulation file, and any other
  5. --  associated documentation or information provided by Altera or a partner
  6. --  under Altera's Megafunction Partnership Program may be used only to
  7. --  program PLD devices (but not masked PLD devices) from Altera.  Any other
  8. --  use of such megafunction design, net list, support information, device
  9. --  programming or simulation file, or any other related documentation or
  10. --  information is prohibited for any other purpose, including, but not
  11. --  limited to modification, reverse engineering, de-compiling, or use with
  12. --  any other silicon devices, unless such use is explicitly licensed under
  13. --  a separate agreement with Altera or a megafunction partner.  Title to
  14. --  the intellectual property, including patents, copyrights, trademarks,
  15. --  trade secrets, or maskworks, embodied in any such megafunction design,
  16. --  net list, support information, device programming or simulation file, or
  17. --  any other related documentation or information provided by Altera or a
  18. --  megafunction partner, remains with Altera, the megafunction partner, or
  19. --  their respective licensors.  No other licenses, including any licenses
  20. --  needed under any third party's intellectual property, are provided herein.
  21. --
  22. DEFAULT_DEVICES
  23. BEGIN
  24. AUTO_DEVICE = EPF10K70RC240-2;
  25. AUTO_DEVICE = EPF10K50BC356-3;
  26. AUTO_DEVICE = EPF10K50RC240-3;
  27. AUTO_DEVICE = EPF10K40RC240-3;
  28. AUTO_DEVICE = EPF10K40RC208-3;
  29. AUTO_DEVICE = EPF10K30BC356-3;
  30. AUTO_DEVICE = EPF10K30RC240-3;
  31. AUTO_DEVICE = EPF10K30RC208-3;
  32. AUTO_DEVICE = EPF10K20RC240-3;
  33. AUTO_DEVICE = EPF10K20RC208-3;
  34. AUTO_DEVICE = EPF10K20TC144-3;
  35. AUTO_DEVICE = EPF10K10QC208-3;
  36. AUTO_DEVICE = EPF10K10TC144-3;
  37. AUTO_DEVICE = EPF10K10LC84-3;
  38. ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
  39. END;
  41. TIMING_POINT
  42. BEGIN
  43. MAINTAIN_STABLE_SYNTHESIS = OFF;
  44. CUT_ALL_CLEAR_PRESET = ON;
  45. CUT_ALL_BIDIR = ON;
  46. END;
  48. IGNORED_ASSIGNMENTS
  49. BEGIN
  50. FIT_IGNORE_TIMING = ON;
  51. DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
  52. IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
  53. IGNORE_DEVICE_ASSIGNMENTS = OFF;
  54. IGNORE_LC_ASSIGNMENTS = OFF;
  55. IGNORE_PIN_ASSIGNMENTS = OFF;
  56. IGNORE_CHIP_ASSIGNMENTS = OFF;
  57. IGNORE_TIMING_ASSIGNMENTS = OFF;
  58. IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
  59. IGNORE_CLIQUE_ASSIGNMENTS = OFF;
  60. END;
  62. GLOBAL_PROJECT_DEVICE_OPTIONS
  63. BEGIN
  64. MAX7000B_ENABLE_VREFB = OFF;
  65. MAX7000B_ENABLE_VREFA = OFF;
  66. MAX7000B_VCCIO_IOBANK2 = 3.3V;
  67. MAX7000B_VCCIO_IOBANK1 = 3.3V;
  68. CONFIG_EPROM_PULLUP_RESISTOR = ON;
  69. CONFIG_EPROM_USER_CODE = FFFFFFFF;
  70. FLEX_CONFIGURATION_EPROM = AUTO;
  71. MAX7000AE_ENABLE_JTAG = ON;
  72. MAX7000AE_USER_CODE = FFFFFFFF;
  73. FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  74. FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
  75. FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  76. FLEX6000_ENABLE_JTAG = OFF;
  77. CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
  78. MULTIVOLT_IO = OFF;
  79. MAX7000S_ENABLE_JTAG = ON;
  80. FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
  81. MAX7000S_USER_CODE = FFFF;
  82. CONFIG_SCHEME_10K = PASSIVE_SERIAL;
  83. FLEX10K_JTAG_USER_CODE = 7F;
  84. ENABLE_INIT_DONE_OUTPUT = OFF;
  85. ENABLE_CHIP_WIDE_OE = OFF;
  86. ENABLE_CHIP_WIDE_RESET = OFF;
  87. nCEO = UNRESERVED;
  88. CLKUSR = UNRESERVED;
  89. ADD17 = UNRESERVED;
  90. ADD16 = UNRESERVED;
  91. ADD15 = UNRESERVED;
  92. ADD14 = UNRESERVED;
  93. ADD13 = UNRESERVED;
  94. ADD0_TO_ADD12 = UNRESERVED;
  95. SDOUT = RESERVED_DRIVES_OUT;
  96. RDCLK = UNRESERVED;
  97. RDYnBUSY = UNRESERVED;
  98. nWS_nRS_nCS_CS = UNRESERVED;
  99. DATA1_TO_DATA7 = UNRESERVED;
  100. DATA0 = RESERVED_TRI_STATED;
  101. FLEX8000_ENABLE_JTAG = OFF;
  102. CONFIG_SCHEME = ACTIVE_SERIAL;
  103. DISABLE_TIME_OUT = OFF;
  104. ENABLE_DCLK_OUTPUT = OFF;
  105. RELEASE_CLEARS = OFF;
  106. AUTO_RESTART = OFF;
  107. USER_CLOCK = OFF;
  108. SECURITY_BIT = OFF;
  109. RESERVED_PINS_PERCENT = 0;
  110. RESERVED_LCELLS_PERCENT = 0;
  111. END;
  113. GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
  114. BEGIN
  115. MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
  116. AUTO_IMPLEMENT_IN_EAB = OFF;
  117. AUTO_OPEN_DRAIN_PINS = ON;
  118. ONE_HOT_STATE_MACHINE_ENCODING = OFF;
  119. AUTO_REGISTER_PACKING = OFF;
  120. DEVICE_FAMILY = FLEX10K;
  121. STYLE = NORMAL;
  122. AUTO_FAST_IO = OFF;
  123. AUTO_GLOBAL_OE = ON;
  124. AUTO_GLOBAL_PRESET = ON;
  125. AUTO_GLOBAL_CLEAR = ON;
  126. AUTO_GLOBAL_CLOCK = ON;
  127. MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
  128. OPTIMIZE_FOR_SPEED = 5;
  129. END;
  131. COMPILER_PROCESSING_CONFIGURATION
  132. BEGIN
  133. PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
  134. FITTER_SETTINGS = NORMAL;
  135. SMART_RECOMPILE = OFF;
  136. GENERATE_AHDL_TDO_FILE = OFF;
  137. RPT_FILE_USER_ASSIGNMENTS = ON;
  138. RPT_FILE_LCELL_INTERCONNECT = ON;
  139. RPT_FILE_HIERARCHY = ON;
  140. RPT_FILE_EQUATIONS = ON;
  141. LINKED_SNF_EXTRACTOR = OFF;
  142. OPTIMIZE_TIMING_SNF = OFF;
  143. TIMING_SNF_EXTRACTOR = ON;
  144. FUNCTIONAL_SNF_EXTRACTOR = OFF;
  145. DESIGN_DOCTOR_RULES = EPLD;
  146. DESIGN_DOCTOR = OFF;
  147. END;
  149. COMPILER_INTERFACES_CONFIGURATION
  150. BEGIN
  151. VHDL_WRITER_VERSION = VHDL93;
  152. VHDL_READER_VERSION = VHDL93;
  153. SYNOPSYS_MAPPING_EFFORT = MEDIUM;
  154. SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
  155. SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
  156. SYNOPSYS_DESIGNWARE = OFF;
  157. SYNOPSYS_COMPILER = DESIGN;
  158. USE_SYNOPSYS_SYNTHESIS = OFF;
  159. VHDL_NETLIST_WRITER = OFF;
  160. VERILOG_NETLIST_WRITER = OFF;
  161. XNF_GENERATE_AHDL_TDX_FILE = ON;
  162. XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
  163. XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
  164. EDIF_OUTPUT_VERSION = 200;
  165. EDIF_NETLIST_WRITER = OFF;
  166. END;
  168. CUSTOM_DESIGN_DOCTOR_RULES
  169. BEGIN
  170. MASTER_RESET = OFF;
  171. EXPANDER_NETWORKS = ON;
  172. RACE_CONDITIONS = ON;
  173. DELAY_CHAINS = ON;
  174. ASYNCHRONOUS_INPUTS = ON;
  175. PRESET_CLEAR_NETWORKS = ON;
  176. STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
  177. STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
  178. MULTI_CLOCK_NETWORKS = ON;
  179. MULTI_LEVEL_CLOCKS = ON;
  180. GATED_CLOCKS = ON;
  181. RIPPLE_CLOCKS = ON;
  182. END;
  184. SIMULATOR_CONFIGURATION
  185. BEGIN
  186. BIDIR_PIN = STRONG;
  187. END_TIME = 0.0ns;
  188. START_TIME = 0.0ns;
  189. GLITCH_TIME = 0.0ns;
  190. GLITCH = OFF;
  191. OSCILLATION_TIME = 0.0ns;
  192. OSCILLATION = OFF;
  193. CHECK_OUTPUTS = OFF;
  194. SETUP_HOLD = OFF;
  195. USE_DEVICE = OFF;
  196. END;
  198. TIMING_ANALYZER_CONFIGURATION
  199. BEGIN
  200. CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
  201. LIST_PATH_FREQUENCY = 10MHz;
  202. LIST_PATH_COUNT = 10;
  203. REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
  204. INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
  205. INCLUDE_PATHS_LESS_THAN = OFF;
  206. INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
  207. INCLUDE_PATHS_GREATER_THAN = OFF;
  208. DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
  209. CELL_WIDTH = 18;
  210. LIST_ONLY_LONGEST_PATH = ON;
  211. CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
  212. CUT_OFF_IO_PIN_FEEDBACK = ON;
  213. AUTO_RECALCULATE = OFF;
  214. ANALYSIS_MODE = DELAY_MATRIX;
  215. END;
  217. OTHER_CONFIGURATION
  218. BEGIN
  219. LAST_MAXPLUS2_VERSION = 10.0;
  220. FLEX_10K_52_COLUMNS = 40;
  221. DEFAULT_9K_EXP_PER_LCELL = 1/2;
  222. LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
  223. LCELLS_PER_ROW_PERCENT = 100;
  224. FAN_IN_PER_LCELL_PERCENT = 100;
  225. EXP_PER_LCELL_PERCENT = 100;
  226. ROW_PINS_PERCENT = 50;
  227. ORIGINAL_MAXPLUS2_VERSION = 10.0;
  228. COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
  229. EXPLICIT_FAMILY = OFF;
  230. END;
  232. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
  233. BEGIN
  234. REGISTER_OPTIMIZATION = ON;
  235. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  236. RESYNTHESIZE_NETWORK = ON;
  237. MULTI_LEVEL_FACTORING = ON;
  238. SUBFACTOR_EXTRACTION = ON;
  239. REFACTORIZATION = ON;
  240. NOT_GATE_PUSH_BACK = ON;
  241. DUPLICATE_LOGIC_EXTRACTION = ON;
  242. REDUCE_LOGIC = ON;
  243. DECOMPOSE_GATES = ON;
  244. SOFT_BUFFER_INSERTION = ON;
  245. FAST_IO = OFF;
  246. IGNORE_SOFT_BUFFERS = OFF;
  247. PARALLEL_EXPANDERS = OFF;
  248. TURBO_BIT = OFF;
  249. XOR_SYNTHESIS = ON;
  250. SLOW_SLEW_RATE = OFF;
  251. MINIMIZATION = FULL;
  252. CARRY_CHAIN_LENGTH = -1;
  253. CARRY_CHAIN = IGNORE;
  254. CASCADE_CHAIN_LENGTH = -1;
  255. CASCADE_CHAIN = IGNORE;
  256. END;
  258. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
  259. BEGIN
  260. REGISTER_OPTIMIZATION = ON;
  261. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  262. RESYNTHESIZE_NETWORK = ON;
  263. MULTI_LEVEL_FACTORING = ON;
  264. SUBFACTOR_EXTRACTION = ON;
  265. REFACTORIZATION = ON;
  266. NOT_GATE_PUSH_BACK = ON;
  267. DUPLICATE_LOGIC_EXTRACTION = ON;
  268. REDUCE_LOGIC = ON;
  269. DECOMPOSE_GATES = ON;
  270. SOFT_BUFFER_INSERTION = ON;
  271. FAST_IO = OFF;
  272. IGNORE_SOFT_BUFFERS = OFF;
  273. PARALLEL_EXPANDERS = OFF;
  274. TURBO_BIT = ON;
  275. XOR_SYNTHESIS = ON;
  276. SLOW_SLEW_RATE = OFF;
  277. MINIMIZATION = FULL;
  278. CARRY_CHAIN_LENGTH = -1;
  279. CARRY_CHAIN = IGNORE;
  280. CASCADE_CHAIN_LENGTH = -1;
  281. CASCADE_CHAIN = IGNORE;
  282. END;
  284. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
  285. BEGIN
  286. REGISTER_OPTIMIZATION = OFF;
  287. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  288. RESYNTHESIZE_NETWORK = ON;
  289. MULTI_LEVEL_FACTORING = OFF;
  290. SUBFACTOR_EXTRACTION = OFF;
  291. REFACTORIZATION = OFF;
  292. NOT_GATE_PUSH_BACK = ON;
  293. DUPLICATE_LOGIC_EXTRACTION = OFF;
  294. REDUCE_LOGIC = OFF;
  295. DECOMPOSE_GATES = ON;
  296. SOFT_BUFFER_INSERTION = ON;
  297. FAST_IO = OFF;
  298. IGNORE_SOFT_BUFFERS = OFF;
  299. PARALLEL_EXPANDERS = OFF;
  300. TURBO_BIT = ON;
  301. XOR_SYNTHESIS = OFF;
  302. SLOW_SLEW_RATE = OFF;
  303. MINIMIZATION = FULL;
  304. CARRY_CHAIN_LENGTH = -1;
  305. CARRY_CHAIN = IGNORE;
  306. CASCADE_CHAIN_LENGTH = -1;
  307. CASCADE_CHAIN = IGNORE;
  308. END;
  310. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
  311. BEGIN
  312. REGISTER_OPTIMIZATION = ON;
  313. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  314. RESYNTHESIZE_NETWORK = ON;
  315. MULTI_LEVEL_FACTORING = ON;
  316. SUBFACTOR_EXTRACTION = ON;
  317. REFACTORIZATION = ON;
  318. NOT_GATE_PUSH_BACK = ON;
  319. DUPLICATE_LOGIC_EXTRACTION = ON;
  320. REDUCE_LOGIC = ON;
  321. DECOMPOSE_GATES = ON;
  322. SOFT_BUFFER_INSERTION = ON;
  323. IGNORE_SOFT_BUFFERS = ON;
  324. PARALLEL_EXPANDERS = OFF;
  325. TURBO_BIT = OFF;
  326. XOR_SYNTHESIS = OFF;
  327. SLOW_SLEW_RATE = OFF;
  328. MINIMIZATION = FULL;
  329. CARRY_CHAIN_LENGTH = 32;
  330. CARRY_CHAIN = IGNORE;
  331. CASCADE_CHAIN_LENGTH = 2;
  332. CASCADE_CHAIN = IGNORE;
  333. END;
  335. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
  336. BEGIN
  337. REGISTER_OPTIMIZATION = ON;
  338. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  339. RESYNTHESIZE_NETWORK = ON;
  340. MULTI_LEVEL_FACTORING = ON;
  341. SUBFACTOR_EXTRACTION = OFF;
  342. REFACTORIZATION = OFF;
  343. NOT_GATE_PUSH_BACK = ON;
  344. DUPLICATE_LOGIC_EXTRACTION = ON;
  345. REDUCE_LOGIC = ON;
  346. DECOMPOSE_GATES = ON;
  347. SOFT_BUFFER_INSERTION = ON;
  348. FAST_IO = OFF;
  349. IGNORE_SOFT_BUFFERS = OFF;
  350. PARALLEL_EXPANDERS = OFF;
  351. TURBO_BIT = OFF;
  352. XOR_SYNTHESIS = ON;
  353. SLOW_SLEW_RATE = OFF;
  354. MINIMIZATION = FULL;
  355. CARRY_CHAIN_LENGTH = -1;
  356. CARRY_CHAIN = IGNORE;
  357. CASCADE_CHAIN_LENGTH = -1;
  358. CASCADE_CHAIN = IGNORE;
  359. END;
  361. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
  362. BEGIN
  363. REGISTER_OPTIMIZATION = ON;
  364. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  365. RESYNTHESIZE_NETWORK = ON;
  366. MULTI_LEVEL_FACTORING = ON;
  367. SUBFACTOR_EXTRACTION = OFF;
  368. REFACTORIZATION = OFF;
  369. NOT_GATE_PUSH_BACK = ON;
  370. DUPLICATE_LOGIC_EXTRACTION = ON;
  371. REDUCE_LOGIC = ON;
  372. DECOMPOSE_GATES = ON;
  373. SOFT_BUFFER_INSERTION = ON;
  374. FAST_IO = OFF;
  375. IGNORE_SOFT_BUFFERS = OFF;
  376. PARALLEL_EXPANDERS = ON;
  377. TURBO_BIT = ON;
  378. XOR_SYNTHESIS = ON;
  379. SLOW_SLEW_RATE = OFF;
  380. MINIMIZATION = FULL;
  381. CARRY_CHAIN_LENGTH = -1;
  382. CARRY_CHAIN = IGNORE;
  383. CASCADE_CHAIN_LENGTH = -1;
  384. CASCADE_CHAIN = IGNORE;
  385. END;
  387. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
  388. BEGIN
  389. REGISTER_OPTIMIZATION = OFF;
  390. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  391. RESYNTHESIZE_NETWORK = ON;
  392. MULTI_LEVEL_FACTORING = OFF;
  393. SUBFACTOR_EXTRACTION = OFF;
  394. REFACTORIZATION = OFF;
  395. NOT_GATE_PUSH_BACK = ON;
  396. DUPLICATE_LOGIC_EXTRACTION = OFF;
  397. REDUCE_LOGIC = OFF;
  398. DECOMPOSE_GATES = ON;
  399. SOFT_BUFFER_INSERTION = ON;
  400. FAST_IO = OFF;
  401. IGNORE_SOFT_BUFFERS = OFF;
  402. PARALLEL_EXPANDERS = OFF;
  403. TURBO_BIT = ON;
  404. XOR_SYNTHESIS = OFF;
  405. SLOW_SLEW_RATE = OFF;
  406. MINIMIZATION = FULL;
  407. CARRY_CHAIN_LENGTH = -1;
  408. CARRY_CHAIN = IGNORE;
  409. CASCADE_CHAIN_LENGTH = -1;
  410. CASCADE_CHAIN = IGNORE;
  411. END;
  413. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
  414. BEGIN
  415. REGISTER_OPTIMIZATION = ON;
  416. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  417. RESYNTHESIZE_NETWORK = ON;
  418. MULTI_LEVEL_FACTORING = ON;
  419. SUBFACTOR_EXTRACTION = OFF;
  420. REFACTORIZATION = OFF;
  421. NOT_GATE_PUSH_BACK = ON;
  422. DUPLICATE_LOGIC_EXTRACTION = ON;
  423. REDUCE_LOGIC = ON;
  424. DECOMPOSE_GATES = ON;
  425. SOFT_BUFFER_INSERTION = ON;
  426. IGNORE_SOFT_BUFFERS = ON;
  427. PARALLEL_EXPANDERS = OFF;
  428. TURBO_BIT = OFF;
  429. XOR_SYNTHESIS = OFF;
  430. SLOW_SLEW_RATE = OFF;
  431. MINIMIZATION = FULL;
  432. CARRY_CHAIN_LENGTH = 32;
  433. CARRY_CHAIN = AUTO;
  434. CASCADE_CHAIN_LENGTH = 2;
  435. CASCADE_CHAIN = AUTO;
  436. END;
  438. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
  439. BEGIN
  440. REGISTER_OPTIMIZATION = OFF;
  441. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  442. RESYNTHESIZE_NETWORK = OFF;
  443. MULTI_LEVEL_FACTORING = OFF;
  444. SUBFACTOR_EXTRACTION = OFF;
  445. REFACTORIZATION = OFF;
  446. NOT_GATE_PUSH_BACK = ON;
  447. DUPLICATE_LOGIC_EXTRACTION = OFF;
  448. REDUCE_LOGIC = OFF;
  449. DECOMPOSE_GATES = OFF;
  450. SOFT_BUFFER_INSERTION = OFF;
  451. FAST_IO = OFF;
  452. IGNORE_SOFT_BUFFERS = OFF;
  453. PARALLEL_EXPANDERS = OFF;
  454. TURBO_BIT = OFF;
  455. XOR_SYNTHESIS = OFF;
  456. SLOW_SLEW_RATE = OFF;
  457. MINIMIZATION = PARTIAL;
  458. CARRY_CHAIN_LENGTH = -1;
  459. CARRY_CHAIN = IGNORE;
  460. CASCADE_CHAIN_LENGTH = -1;
  461. CASCADE_CHAIN = IGNORE;
  462. END;
  464. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
  465. BEGIN
  466. REGISTER_OPTIMIZATION = OFF;
  467. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  468. RESYNTHESIZE_NETWORK = OFF;
  469. MULTI_LEVEL_FACTORING = OFF;
  470. SUBFACTOR_EXTRACTION = OFF;
  471. REFACTORIZATION = OFF;
  472. NOT_GATE_PUSH_BACK = ON;
  473. DUPLICATE_LOGIC_EXTRACTION = OFF;
  474. REDUCE_LOGIC = OFF;
  475. DECOMPOSE_GATES = OFF;
  476. SOFT_BUFFER_INSERTION = OFF;
  477. FAST_IO = OFF;
  478. IGNORE_SOFT_BUFFERS = OFF;
  479. PARALLEL_EXPANDERS = OFF;
  480. TURBO_BIT = ON;
  481. XOR_SYNTHESIS = OFF;
  482. SLOW_SLEW_RATE = OFF;
  483. MINIMIZATION = PARTIAL;
  484. CARRY_CHAIN_LENGTH = -1;
  485. CARRY_CHAIN = IGNORE;
  486. CASCADE_CHAIN_LENGTH = -1;
  487. CASCADE_CHAIN = IGNORE;
  488. END;
  490. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
  491. BEGIN
  492. REGISTER_OPTIMIZATION = OFF;
  493. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  494. RESYNTHESIZE_NETWORK = ON;
  495. MULTI_LEVEL_FACTORING = OFF;
  496. SUBFACTOR_EXTRACTION = OFF;
  497. REFACTORIZATION = OFF;
  498. NOT_GATE_PUSH_BACK = ON;
  499. DUPLICATE_LOGIC_EXTRACTION = OFF;
  500. REDUCE_LOGIC = OFF;
  501. DECOMPOSE_GATES = ON;
  502. SOFT_BUFFER_INSERTION = OFF;
  503. FAST_IO = OFF;
  504. IGNORE_SOFT_BUFFERS = OFF;
  505. PARALLEL_EXPANDERS = OFF;
  506. TURBO_BIT = ON;
  507. XOR_SYNTHESIS = OFF;
  508. SLOW_SLEW_RATE = OFF;
  509. MINIMIZATION = PARTIAL;
  510. CARRY_CHAIN_LENGTH = -1;
  511. CARRY_CHAIN = IGNORE;
  512. CASCADE_CHAIN_LENGTH = -1;
  513. CASCADE_CHAIN = IGNORE;
  514. END;
  516. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
  517. BEGIN
  518. REGISTER_OPTIMIZATION = OFF;
  519. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  520. RESYNTHESIZE_NETWORK = OFF;
  521. MULTI_LEVEL_FACTORING = OFF;
  522. SUBFACTOR_EXTRACTION = OFF;
  523. REFACTORIZATION = OFF;
  524. NOT_GATE_PUSH_BACK = ON;
  525. DUPLICATE_LOGIC_EXTRACTION = OFF;
  526. REDUCE_LOGIC = OFF;
  527. DECOMPOSE_GATES = OFF;
  528. SOFT_BUFFER_INSERTION = ON;
  529. IGNORE_SOFT_BUFFERS = ON;
  530. PARALLEL_EXPANDERS = OFF;
  531. TURBO_BIT = OFF;
  532. XOR_SYNTHESIS = OFF;
  533. SLOW_SLEW_RATE = OFF;
  534. MINIMIZATION = PARTIAL;
  535. CARRY_CHAIN_LENGTH = 32;
  536. CARRY_CHAIN = MANUAL;
  537. CASCADE_CHAIN_LENGTH = 2;
  538. CASCADE_CHAIN = MANUAL;
  539. END;