English
as32.rpt
资源名称：mips.rar [点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：67k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Project Information e:doucumentsprojectsmips__1080379086as32.rpt
- MAX+plus II Compiler Report File
- Version 10.0 9/14/2000
- Compiled: 12/13/2008 00:47:16
- Copyright (C) 1988-2000 Altera Corporation
- Any megafunction design, and related net list (encrypted or decrypted),
- support information, device programming or simulation file, and any other
- associated documentation or information provided by Altera or a partner
- under Altera's Megafunction Partnership Program may be used only to
- program PLD devices (but not masked PLD devices) from Altera. Any other
- use of such megafunction design, net list, support information, device
- programming or simulation file, or any other related documentation or
- information is prohibited for any other purpose, including, but not
- limited to modification, reverse engineering, de-compiling, or use with
- any other silicon devices, unless such use is explicitly licensed under
- a separate agreement with Altera or a megafunction partner. Title to
- the intellectual property, including patents, copyrights, trademarks,
- trade secrets, or maskworks, embodied in any such megafunction design,
- net list, support information, device programming or simulation file, or
- any other related documentation or information provided by Altera or a
- megafunction partner, remains with Altera, the megafunction partner, or
- their respective licensors. No other licenses, including any licenses
- needed under any third party's intellectual property, are provided herein.
- ***** Project compilation was successful
- ** DEVICE SUMMARY **
- Chip/ Input Output Bidir Memory Memory LCs
- POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
- as32 EPF10K10TC144-3 65 32 0 0 0 % 63 10 %
- User Pins: 65 32 0
- Project Information e:doucumentsprojectsmips__1080379086as32.rpt
- ** FILE HIERARCHY **
- |add32bit:7|
- |add32bit:7|add8bit:4|
- |add32bit:7|add8bit:4|add1bit:5|
- |add32bit:7|add8bit:4|add1bit:12|
- |add32bit:7|add8bit:4|add1bit:11|
- |add32bit:7|add8bit:4|add1bit:10|
- |add32bit:7|add8bit:4|add1bit:9|
- |add32bit:7|add8bit:4|add1bit:8|
- |add32bit:7|add8bit:4|add1bit:7|
- |add32bit:7|add8bit:4|add1bit:6|
- |add32bit:7|add8bit:7|
- |add32bit:7|add8bit:7|add1bit:5|
- |add32bit:7|add8bit:7|add1bit:12|
- |add32bit:7|add8bit:7|add1bit:11|
- |add32bit:7|add8bit:7|add1bit:10|
- |add32bit:7|add8bit:7|add1bit:9|
- |add32bit:7|add8bit:7|add1bit:8|
- |add32bit:7|add8bit:7|add1bit:7|
- |add32bit:7|add8bit:7|add1bit:6|
- |add32bit:7|add8bit:6|
- |add32bit:7|add8bit:6|add1bit:5|
- |add32bit:7|add8bit:6|add1bit:12|
- |add32bit:7|add8bit:6|add1bit:11|
- |add32bit:7|add8bit:6|add1bit:10|
- |add32bit:7|add8bit:6|add1bit:9|
- |add32bit:7|add8bit:6|add1bit:8|
- |add32bit:7|add8bit:6|add1bit:7|
- |add32bit:7|add8bit:6|add1bit:6|
- |add32bit:7|add8bit:5|
- |add32bit:7|add8bit:5|add1bit:5|
- |add32bit:7|add8bit:5|add1bit:12|
- |add32bit:7|add8bit:5|add1bit:11|
- |add32bit:7|add8bit:5|add1bit:10|
- |add32bit:7|add8bit:5|add1bit:9|
- |add32bit:7|add8bit:5|add1bit:8|
- |add32bit:7|add8bit:5|add1bit:7|
- |add32bit:7|add8bit:5|add1bit:6|
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ***** Logic for device 'as32' compiled without errors.
- Device: EPF10K10TC144-3
- FLEX 10K Configuration Scheme: Passive Serial
- Device Options:
- User-Supplied Start-Up Clock = OFF
- Auto-Restart Configuration on Frame Error = OFF
- Release Clears Before Tri-States = OFF
- Enable Chip_Wide Reset = OFF
- Enable Chip-Wide Output Enable = OFF
- Enable INIT_DONE Output = OFF
- JTAG User Code = 7f
- MultiVolt I/O = OFF
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** ERROR SUMMARY **
- Info: Chip 'as32' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
- R R
- E E
- G V S S
- G V G N C E V E
- N C N D C R C R
- B A S B B D C A D I B I V A B S A A S C A B B B V A
- 1 1 1 1 1 I A B S S I S B A 1 I A N B 2 A N E 2 2 2 2 2 2 I 3 2 3 2 E 1
- 1 7 3 0 8 O 9 8 8 7 O 6 0 4 4 O 0 T 7 3 3 T D 7 8 7 5 4 6 O 0 7 0 2 D 9
- --------------------------------------------------------------------------_
- / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
- / 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
- #TCK | 1 108 | ^DATA0
- ^CONF_DONE | 2 107 | ^DCLK
- ^nCEO | 3 106 | ^nCE
- #TDO | 4 105 | #TDI
- VCCIO | 5 104 | GNDIO
- VCCINT | 6 103 | GNDINT
- B20 | 7 102 | A20
- S16 | 8 101 | B16
- B15 | 9 100 | S22
- S15 | 10 99 | S21
- S17 | 11 98 | A18
- A21 | 12 97 | A15
- A22 | 13 96 | B21
- S18 | 14 95 | S19
- GNDIO | 15 94 | VCCIO
- GNDINT | 16 93 | VCCINT
- S9 | 17 92 | S24
- A26 | 18 91 | A13
- A12 | 19 EPF10K10TC144-3 90 | S28
- S11 | 20 89 | S30
- S12 | 21 88 | S29
- S23 | 22 87 | A23
- A29 | 23 86 | B25
- VCCIO | 24 85 | GNDIO
- VCCINT | 25 84 | GNDINT
- S1 | 26 83 | A6
- A2 | 27 82 | A5
- B5 | 28 81 | B2
- B4 | 29 80 | B1
- S2 | 30 79 | B6
- S4 | 31 78 | A1
- S5 | 32 77 | ^MSEL0
- S0 | 33 76 | ^MSEL1
- #TMS | 34 75 | VCCINT
- ^nSTATUS | 35 74 | ^nCONFIG
- B14 | 36 73 | B26
- | 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
- 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
- ---------------------------------------------------------------------------
- S S R G B S A A V B A A B G B V V S A B G G A B V R B R S G B B S S V A
- 1 3 E N 9 1 1 1 C 1 1 8 1 N 1 C C U 7 3 N N 2 2 C E 3 E 3 N 2 1 2 2 C 3
- 4 S D 0 1 6 C 7 0 3 D 2 C C B D D 8 9 C S 1 S 1 D 4 9 0 5 C 1
- E I I I I I I I I E E I I
- R O O O N N N N O R R O O
- V T T T T V V
- E E E
- D D D
- N.C. = No Connect. This pin has no internal connection to the device.
- VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
- GNDIO = Dedicated ground pin, which MUST be connected to GND.
- RESERVED = Unused I/O pin, which MUST be left unconnected.
- ^ = Dedicated configuration pin.
- + = Reserved configuration pin, which is tri-stated during user mode.
- * = Reserved configuration pin, which drives out in user mode.
- PDn = Power Down pin.
- @ = Special-purpose pin.
- # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
- & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** RESOURCE USAGE **
- Logic Column Row
- Array Interconnect Interconnect Clears/ External
- Block Logic Cells Driven Driven Clocks Presets Interconnect
- A5 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
- A19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
- B6 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
- B8 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
- B9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
- B20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
- B23 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
- C18 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
- C21 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
- Embedded Column Row
- Array Embedded Interconnect Interconnect Read/ External
- Block Cells Driven Driven Clocks Write Interconnect
- Total dedicated input pins used: 6/6 (100%)
- Total I/O pins used: 91/96 ( 94%)
- Total logic cells used: 63/576 ( 10%)
- Total embedded cells used: 0/24 ( 0%)
- Total EABs used: 0/3 ( 0%)
- Average fan-in: 3.93/4 ( 98%)
- Total fan-in: 248/2304 ( 10%)
- Total input pins required: 65
- Total input I/O cell registers required: 0
- Total output pins required: 32
- Total output I/O cell registers required: 0
- Total buried I/O cell registers required: 0
- Total bidirectional pins required: 0
- Total reserved pins required 0
- Total logic cells required: 63
- Total flipflops required: 0
- Total packed registers required: 0
- Total logic cells in carry chains: 0
- Total number of carry chains: 0
- Total logic cells in cascade chains: 0
- Total number of cascade chains: 0
- Total single-pin Clock Enables required: 0
- Total single-pin Output Enables required: 0
- Synthesized logic cells: 1/ 576 ( 0%)
- Logic Cell and Embedded Cell Counts
- Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
- A: 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 16/0
- B: 0 0 0 0 0 7 0 8 1 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 0 32/0
- C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 7 0 0 0 15/0
- Total: 0 0 0 0 8 7 0 8 1 0 0 0 0 0 0 0 0 0 8 8 8 7 0 8 0 63/0
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** INPUTS **
- Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 128 - - - 13 INPUT 0 0 0 2 A0
- 78 - - C -- INPUT 0 0 0 2 A1
- 27 - - C -- INPUT 0 0 0 2 A2
- 124 - - - -- INPUT 0 0 0 2 A3
- 131 - - - 15 INPUT 0 0 0 2 A4
- 82 - - C -- INPUT 0 0 0 2 A5
- 83 - - C -- INPUT 0 0 0 2 A6
- 55 - - - -- INPUT 0 0 0 2 A7
- 48 - - - 15 INPUT 0 0 0 2 A8
- 138 - - - 20 INPUT 0 0 0 2 A9
- 47 - - - 16 INPUT 0 0 0 2 A10
- 43 - - - 18 INPUT 0 0 0 2 A11
- 19 - - B -- INPUT 0 0 0 2 A12
- 91 - - B -- INPUT 0 0 0 2 A13
- 130 - - - 14 INPUT 0 0 0 2 A14
- 97 - - A -- INPUT 0 0 0 2 A15
- 44 - - - 18 INPUT 0 0 0 2 A16
- 143 - - - 24 INPUT 0 0 0 2 A17
- 98 - - A -- INPUT 0 0 0 2 A18
- 109 - - - 01 INPUT 0 0 0 2 A19
- 102 - - A -- INPUT 0 0 0 2 A20
- 12 - - A -- INPUT 0 0 0 2 A21
- 13 - - A -- INPUT 0 0 0 2 A22
- 87 - - B -- INPUT 0 0 0 2 A23
- 117 - - - 06 INPUT 0 0 0 2 A24
- 118 - - - 07 INPUT 0 0 0 2 A25
- 18 - - B -- INPUT 0 0 0 2 A26
- 121 - - - 10 INPUT 0 0 0 2 A27
- 59 - - - 12 INPUT 0 0 0 2 A28
- 23 - - B -- INPUT 0 0 0 2 A29
- 114 - - - 04 INPUT 0 0 0 2 A30
- 72 - - - 04 INPUT 0 0 0 1 A31
- 132 - - - 16 INPUT 0 0 0 2 B0
- 80 - - C -- INPUT 0 0 0 2 B1
- 81 - - C -- INPUT 0 0 0 2 B2
- 56 - - - -- INPUT 0 0 0 2 B3
- 29 - - C -- INPUT 0 0 0 2 B4
- 28 - - C -- INPUT 0 0 0 2 B5
- 79 - - C -- INPUT 0 0 0 2 B6
- 126 - - - -- INPUT 0 0 0 2 B7
- 137 - - - 19 INPUT 0 0 0 2 B8
- 41 - - - 20 INPUT 0 0 0 2 B9
- 141 - - - 22 INPUT 0 0 0 2 B10
- 144 - - - 24 INPUT 0 0 0 2 B11
- 51 - - - 13 INPUT 0 0 0 2 B12
- 49 - - - 14 INPUT 0 0 0 2 B13
- 36 - - - 24 INPUT 0 0 0 2 B14
- 9 - - A -- INPUT 0 0 0 2 B15
- 101 - - A -- INPUT 0 0 0 2 B16
- 46 - - - 17 INPUT 0 0 0 2 B17
- 140 - - - 21 INPUT 0 0 0 2 B18
- 68 - - - 07 INPUT 0 0 0 2 B19
- 7 - - A -- INPUT 0 0 0 2 B20
- 96 - - A -- INPUT 0 0 0 2 B21
- 111 - - - 02 INPUT 0 0 0 2 B22
- 125 - - - -- INPUT 0 0 0 2 B23
- 67 - - - 08 INPUT 0 0 0 2 B24
- 86 - - B -- INPUT 0 0 0 2 B25
- 73 - - - 02 INPUT 0 0 0 2 B26
- 113 - - - 03 INPUT 0 0 0 2 B27
- 120 - - - 09 INPUT 0 0 0 2 B28
- 60 - - - 12 INPUT 0 0 0 2 B29
- 112 - - - 03 INPUT 0 0 0 2 B30
- 63 - - - 11 INPUT 0 0 0 1 B31
- 54 - - - -- INPUT 0 0 0 61 SUB
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** OUTPUTS **
- Fed By Fed By Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 33 - - C -- OUTPUT 0 1 0 0 S0
- 26 - - C -- OUTPUT 0 1 0 0 S1
- 30 - - C -- OUTPUT 0 1 0 0 S2
- 38 - - - 22 OUTPUT 0 1 0 0 S3
- 31 - - C -- OUTPUT 0 1 0 0 S4
- 32 - - C -- OUTPUT 0 1 0 0 S5
- 133 - - - 17 OUTPUT 0 1 0 0 S6
- 135 - - - 18 OUTPUT 0 1 0 0 S7
- 136 - - - 19 OUTPUT 0 1 0 0 S8
- 17 - - B -- OUTPUT 0 1 0 0 S9
- 42 - - - 19 OUTPUT 0 1 0 0 S10
- 20 - - B -- OUTPUT 0 1 0 0 S11
- 21 - - B -- OUTPUT 0 1 0 0 S12
- 142 - - - 23 OUTPUT 0 1 0 0 S13
- 37 - - - 23 OUTPUT 0 1 0 0 S14
- 10 - - A -- OUTPUT 0 1 0 0 S15
- 8 - - A -- OUTPUT 0 1 0 0 S16
- 11 - - A -- OUTPUT 0 1 0 0 S17
- 14 - - A -- OUTPUT 0 1 0 0 S18
- 95 - - A -- OUTPUT 0 1 0 0 S19
- 69 - - - 06 OUTPUT 0 1 0 0 S20
- 99 - - A -- OUTPUT 0 1 0 0 S21
- 100 - - A -- OUTPUT 0 1 0 0 S22
- 22 - - B -- OUTPUT 0 1 0 0 S23
- 92 - - B -- OUTPUT 0 1 0 0 S24
- 70 - - - 05 OUTPUT 0 1 0 0 S25
- 116 - - - 05 OUTPUT 0 1 0 0 S26
- 119 - - - 08 OUTPUT 0 1 0 0 S27
- 90 - - B -- OUTPUT 0 1 0 0 S28
- 88 - - B -- OUTPUT 0 1 0 0 S29
- 89 - - B -- OUTPUT 0 1 0 0 S30
- 65 - - - 09 OUTPUT 0 1 0 0 S31
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** BURIED LOGIC **
- Fan-In Fan-Out
- IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 8 - C 21 OR2 2 0 1 0 |add32bit:7|add8bit:4|add1bit:5|S (|add32bit:7|add8bit:4|add1bit:5|:6)
- - 3 - C 21 OR2 3 0 0 2 |add32bit:7|add8bit:4|add1bit:5|CO (|add32bit:7|add8bit:4|add1bit:5|:11)
- - 1 - C 21 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:6|S (|add32bit:7|add8bit:4|add1bit:6|:6)
- - 6 - C 21 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:6|CO (|add32bit:7|add8bit:4|add1bit:6|:11)
- - 5 - C 21 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:7|S (|add32bit:7|add8bit:4|add1bit:7|:6)
- - 2 - C 21 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:7|CO (|add32bit:7|add8bit:4|add1bit:7|:11)
- - 4 - C 21 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:8|S (|add32bit:7|add8bit:4|add1bit:8|:6)
- - 2 - C 18 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:8|CO (|add32bit:7|add8bit:4|add1bit:8|:11)
- - 5 - C 18 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:9|S (|add32bit:7|add8bit:4|add1bit:9|:6)
- - 3 - C 18 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:9|CO (|add32bit:7|add8bit:4|add1bit:9|:11)
- - 6 - C 18 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:10|S (|add32bit:7|add8bit:4|add1bit:10|:6)
- - 7 - C 18 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:10|CO (|add32bit:7|add8bit:4|add1bit:10|:11)
- - 8 - C 18 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:11|S (|add32bit:7|add8bit:4|add1bit:11|:6)
- - 4 - C 18 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:11|CO (|add32bit:7|add8bit:4|add1bit:11|:11)
- - 1 - C 18 OR2 3 1 1 0 |add32bit:7|add8bit:4|add1bit:12|S (|add32bit:7|add8bit:4|add1bit:12|:6)
- - 3 - B 20 OR2 3 1 0 2 |add32bit:7|add8bit:4|add1bit:12|CO (|add32bit:7|add8bit:4|add1bit:12|:11)
- - 4 - B 20 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:5|S (|add32bit:7|add8bit:5|add1bit:5|:6)
- - 5 - B 20 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:5|CO (|add32bit:7|add8bit:5|add1bit:5|:11)
- - 1 - B 20 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:6|S (|add32bit:7|add8bit:5|add1bit:6|:6)
- - 7 - B 20 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:6|CO (|add32bit:7|add8bit:5|add1bit:6|:11)
- - 8 - B 20 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:7|S (|add32bit:7|add8bit:5|add1bit:7|:6)
- - 2 - B 20 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:7|CO (|add32bit:7|add8bit:5|add1bit:7|:11)
- - 4 - B 23 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:8|S (|add32bit:7|add8bit:5|add1bit:8|:6)
- - 2 - B 23 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:8|CO (|add32bit:7|add8bit:5|add1bit:8|:11)
- - 5 - B 23 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:9|S (|add32bit:7|add8bit:5|add1bit:9|:6)
- - 7 - B 23 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:9|CO (|add32bit:7|add8bit:5|add1bit:9|:11)
- - 3 - B 23 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:10|S (|add32bit:7|add8bit:5|add1bit:10|:6)
- - 8 - B 23 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:10|CO (|add32bit:7|add8bit:5|add1bit:10|:11)
- - 6 - B 23 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:11|S (|add32bit:7|add8bit:5|add1bit:11|:6)
- - 1 - B 23 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:11|CO (|add32bit:7|add8bit:5|add1bit:11|:11)
- - 4 - A 19 OR2 3 1 1 0 |add32bit:7|add8bit:5|add1bit:12|S (|add32bit:7|add8bit:5|add1bit:12|:6)
- - 1 - A 19 OR2 3 1 0 2 |add32bit:7|add8bit:5|add1bit:12|CO (|add32bit:7|add8bit:5|add1bit:12|:11)
- - 2 - A 19 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:5|S (|add32bit:7|add8bit:6|add1bit:5|:6)
- - 3 - A 19 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:5|CO (|add32bit:7|add8bit:6|add1bit:5|:11)
- - 5 - A 19 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:6|S (|add32bit:7|add8bit:6|add1bit:6|:6)
- - 6 - A 19 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:6|CO (|add32bit:7|add8bit:6|add1bit:6|:11)
- - 8 - A 19 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:7|S (|add32bit:7|add8bit:6|add1bit:7|:6)
- - 7 - A 19 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:7|CO (|add32bit:7|add8bit:6|add1bit:7|:11)
- - 8 - A 05 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:8|S (|add32bit:7|add8bit:6|add1bit:8|:6)
- - 2 - A 05 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:8|CO (|add32bit:7|add8bit:6|add1bit:8|:11)
- - 5 - A 05 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:9|S (|add32bit:7|add8bit:6|add1bit:9|:6)
- - 6 - A 05 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:9|CO (|add32bit:7|add8bit:6|add1bit:9|:11)
- - 4 - A 05 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:10|S (|add32bit:7|add8bit:6|add1bit:10|:6)
- - 7 - A 05 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:10|CO (|add32bit:7|add8bit:6|add1bit:10|:11)
- - 3 - A 05 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:11|S (|add32bit:7|add8bit:6|add1bit:11|:6)
- - 1 - A 05 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:11|CO (|add32bit:7|add8bit:6|add1bit:11|:11)
- - 6 - B 20 OR2 3 1 1 0 |add32bit:7|add8bit:6|add1bit:12|S (|add32bit:7|add8bit:6|add1bit:12|:6)
- - 3 - B 06 OR2 3 1 0 2 |add32bit:7|add8bit:6|add1bit:12|CO (|add32bit:7|add8bit:6|add1bit:12|:11)
- - 1 - B 06 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:5|S (|add32bit:7|add8bit:7|add1bit:5|:6)
- - 4 - B 06 OR2 3 1 0 2 |add32bit:7|add8bit:7|add1bit:5|CO (|add32bit:7|add8bit:7|add1bit:5|:11)
- - 6 - B 06 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:6|S (|add32bit:7|add8bit:7|add1bit:6|:6)
- - 7 - B 06 OR2 3 1 0 2 |add32bit:7|add8bit:7|add1bit:6|CO (|add32bit:7|add8bit:7|add1bit:6|:11)
- - 5 - B 06 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:7|S (|add32bit:7|add8bit:7|add1bit:7|:6)
- - 2 - B 06 OR2 3 1 0 2 |add32bit:7|add8bit:7|add1bit:7|CO (|add32bit:7|add8bit:7|add1bit:7|:11)
- - 3 - B 08 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:8|S (|add32bit:7|add8bit:7|add1bit:8|:6)
- - 2 - B 08 OR2 3 1 0 2 |add32bit:7|add8bit:7|add1bit:8|CO (|add32bit:7|add8bit:7|add1bit:8|:11)
- - 4 - B 08 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:9|S (|add32bit:7|add8bit:7|add1bit:9|:6)
- - 7 - B 08 OR2 3 1 0 2 |add32bit:7|add8bit:7|add1bit:9|CO (|add32bit:7|add8bit:7|add1bit:9|:11)
- - 6 - B 08 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:10|S (|add32bit:7|add8bit:7|add1bit:10|:6)
- - 8 - B 08 OR2 3 1 0 2 |add32bit:7|add8bit:7|add1bit:10|CO (|add32bit:7|add8bit:7|add1bit:10|:11)
- - 5 - B 08 OR2 3 1 1 0 |add32bit:7|add8bit:7|add1bit:11|S (|add32bit:7|add8bit:7|add1bit:11|:6)
- - 1 - B 08 OR2 s 3 1 0 1 |add32bit:7|add8bit:7|add1bit:12|S~1 (|add32bit:7|add8bit:7|add1bit:12|~6~1)
- - 1 - B 09 OR2 2 1 1 0 |add32bit:7|add8bit:7|add1bit:12|S (|add32bit:7|add8bit:7|add1bit:12|:6)
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- p = Packed register
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** FASTTRACK INTERCONNECT UTILIZATION **
- Row FastTrack Interconnect:
- Global Left Half- Right Half-
- FastTrack FastTrack FastTrack
- Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
- A: 10/ 96( 10%) 6/ 48( 12%) 9/ 48( 18%) 9/16( 56%) 7/16( 43%) 0/16( 0%)
- B: 14/ 96( 14%) 16/ 48( 33%) 14/ 48( 29%) 6/16( 37%) 8/16( 50%) 0/16( 0%)
- C: 10/ 96( 10%) 0/ 48( 0%) 8/ 48( 16%) 9/16( 56%) 5/16( 31%) 0/16( 0%)
- Column FastTrack Interconnect:
- FastTrack
- Column Interconnect Input Pins Output Pins Bidir Pins
- 01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 05: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
- 06: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 07: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 08: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 09: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 13: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 14: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 15: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 16: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 17: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 18: 4/24( 16%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- 19: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
- 20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 22: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 23: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
- 24: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
- EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- Device-Specific Information: e:doucumentsprojectsmips__1080379086as32.rpt
- as32
- ** EQUATIONS **
- A0 : INPUT;
- A1 : INPUT;
- A2 : INPUT;
- A3 : INPUT;
- A4 : INPUT;
- A5 : INPUT;
- A6 : INPUT;
- A7 : INPUT;
- A8 : INPUT;
- A9 : INPUT;
- A10 : INPUT;
- A11 : INPUT;
- A12 : INPUT;
- A13 : INPUT;
- A14 : INPUT;
- A15 : INPUT;
- A16 : INPUT;
- A17 : INPUT;
- A18 : INPUT;
- A19 : INPUT;
- A20 : INPUT;
- A21 : INPUT;
- A22 : INPUT;
- A23 : INPUT;
- A24 : INPUT;
- A25 : INPUT;
- A26 : INPUT;
- A27 : INPUT;
- A28 : INPUT;
- A29 : INPUT;
- A30 : INPUT;
- A31 : INPUT;
- B0 : INPUT;
- B1 : INPUT;
- B2 : INPUT;
- B3 : INPUT;
- B4 : INPUT;
- B5 : INPUT;
- B6 : INPUT;
- B7 : INPUT;
- B8 : INPUT;
- B9 : INPUT;
- B10 : INPUT;
- B11 : INPUT;
- B12 : INPUT;
- B13 : INPUT;
- B14 : INPUT;
- B15 : INPUT;
- B16 : INPUT;
- B17 : INPUT;
- B18 : INPUT;
- B19 : INPUT;
- B20 : INPUT;
- B21 : INPUT;
- B22 : INPUT;
- B23 : INPUT;
- B24 : INPUT;
- B25 : INPUT;
- B26 : INPUT;
- B27 : INPUT;
- B28 : INPUT;
- B29 : INPUT;
- B30 : INPUT;
- B31 : INPUT;
- SUB : INPUT;
- -- Node name is 'S0'
- -- Equation name is 'S0', type is output
- S0 = _LC8_C21;
- -- Node name is 'S1'
- -- Equation name is 'S1', type is output
- S1 = _LC1_C21;
- -- Node name is 'S2'
- -- Equation name is 'S2', type is output
- S2 = _LC5_C21;
- -- Node name is 'S3'
- -- Equation name is 'S3', type is output
- S3 = _LC4_C21;
- -- Node name is 'S4'
- -- Equation name is 'S4', type is output
- S4 = _LC5_C18;
- -- Node name is 'S5'
- -- Equation name is 'S5', type is output
- S5 = _LC6_C18;
- -- Node name is 'S6'
- -- Equation name is 'S6', type is output
- S6 = _LC8_C18;
- -- Node name is 'S7'
- -- Equation name is 'S7', type is output
- S7 = _LC1_C18;
- -- Node name is 'S8'
- -- Equation name is 'S8', type is output
- S8 = _LC4_B20;
- -- Node name is 'S9'
- -- Equation name is 'S9', type is output
- S9 = _LC1_B20;
- -- Node name is 'S10'
- -- Equation name is 'S10', type is output
- S10 = _LC8_B20;
- -- Node name is 'S11'
- -- Equation name is 'S11', type is output
- S11 = _LC4_B23;
- -- Node name is 'S12'
- -- Equation name is 'S12', type is output
- S12 = _LC5_B23;
- -- Node name is 'S13'
- -- Equation name is 'S13', type is output
- S13 = _LC3_B23;
- -- Node name is 'S14'
- -- Equation name is 'S14', type is output
- S14 = _LC6_B23;
- -- Node name is 'S15'
- -- Equation name is 'S15', type is output
- S15 = _LC4_A19;
- -- Node name is 'S16'
- -- Equation name is 'S16', type is output
- S16 = _LC2_A19;
- -- Node name is 'S17'
- -- Equation name is 'S17', type is output
- S17 = _LC5_A19;
- -- Node name is 'S18'
- -- Equation name is 'S18', type is output
- S18 = _LC8_A19;
- -- Node name is 'S19'
- -- Equation name is 'S19', type is output
- S19 = _LC8_A5;
- -- Node name is 'S20'
- -- Equation name is 'S20', type is output
- S20 = _LC5_A5;
- -- Node name is 'S21'
- -- Equation name is 'S21', type is output
- S21 = _LC4_A5;
- -- Node name is 'S22'
- -- Equation name is 'S22', type is output
- S22 = _LC3_A5;
- -- Node name is 'S23'
- -- Equation name is 'S23', type is output
- S23 = _LC6_B20;
- -- Node name is 'S24'
- -- Equation name is 'S24', type is output
- S24 = _LC1_B6;
- -- Node name is 'S25'
- -- Equation name is 'S25', type is output
- S25 = _LC6_B6;
- -- Node name is 'S26'
- -- Equation name is 'S26', type is output
- S26 = _LC5_B6;
- -- Node name is 'S27'
- -- Equation name is 'S27', type is output
- S27 = _LC3_B8;
- -- Node name is 'S28'
- -- Equation name is 'S28', type is output
- S28 = _LC4_B8;
- -- Node name is 'S29'
- -- Equation name is 'S29', type is output
- S29 = _LC6_B8;
- -- Node name is 'S30'
- -- Equation name is 'S30', type is output
- S30 = _LC5_B8;
- -- Node name is 'S31'
- -- Equation name is 'S31', type is output
- S31 = _LC1_B9;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:5|:11' = '|add32bit:7|add8bit:4|add1bit:5|CO'
- -- Equation name is '_LC3_C21', type is buried
- _LC3_C21 = LCELL( _EQ001);
- _EQ001 = A0 & B0
- # A0 & SUB
- # !B0 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:5|:6' = '|add32bit:7|add8bit:4|add1bit:5|S'
- -- Equation name is '_LC8_C21', type is buried
- _LC8_C21 = LCELL( _EQ002);
- _EQ002 = A0 & !B0
- # !A0 & B0;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:6|:11' = '|add32bit:7|add8bit:4|add1bit:6|CO'
- -- Equation name is '_LC6_C21', type is buried
- _LC6_C21 = LCELL( _EQ003);
- _EQ003 = B1 & _LC3_C21 & !SUB
- # !B1 & _LC3_C21 & SUB
- # A1 & _LC3_C21
- # A1 & B1 & !SUB
- # A1 & !B1 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:6|:6' = '|add32bit:7|add8bit:4|add1bit:6|S'
- -- Equation name is '_LC1_C21', type is buried
- _LC1_C21 = LCELL( _EQ004);
- _EQ004 = A1 & B1 & _LC3_C21 & !SUB
- # A1 & !B1 & _LC3_C21 & SUB
- # A1 & B1 & !_LC3_C21 & SUB
- # A1 & !B1 & !_LC3_C21 & !SUB
- # !A1 & B1 & _LC3_C21 & SUB
- # !A1 & !B1 & _LC3_C21 & !SUB
- # !A1 & B1 & !_LC3_C21 & !SUB
- # !A1 & !B1 & !_LC3_C21 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:7|:11' = '|add32bit:7|add8bit:4|add1bit:7|CO'
- -- Equation name is '_LC2_C21', type is buried
- _LC2_C21 = LCELL( _EQ005);
- _EQ005 = B2 & _LC6_C21 & !SUB
- # !B2 & _LC6_C21 & SUB
- # A2 & _LC6_C21
- # A2 & B2 & !SUB
- # A2 & !B2 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:7|:6' = '|add32bit:7|add8bit:4|add1bit:7|S'
- -- Equation name is '_LC5_C21', type is buried
- _LC5_C21 = LCELL( _EQ006);
- _EQ006 = A2 & B2 & _LC6_C21 & !SUB
- # A2 & !B2 & _LC6_C21 & SUB
- # !A2 & B2 & _LC6_C21 & SUB
- # !A2 & !B2 & _LC6_C21 & !SUB
- # A2 & B2 & !_LC6_C21 & SUB
- # A2 & !B2 & !_LC6_C21 & !SUB
- # !A2 & B2 & !_LC6_C21 & !SUB
- # !A2 & !B2 & !_LC6_C21 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:8|:11' = '|add32bit:7|add8bit:4|add1bit:8|CO'
- -- Equation name is '_LC2_C18', type is buried
- _LC2_C18 = LCELL( _EQ007);
- _EQ007 = B3 & _LC2_C21 & !SUB
- # !B3 & _LC2_C21 & SUB
- # A3 & _LC2_C21
- # A3 & B3 & !SUB
- # A3 & !B3 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:8|:6' = '|add32bit:7|add8bit:4|add1bit:8|S'
- -- Equation name is '_LC4_C21', type is buried
- _LC4_C21 = LCELL( _EQ008);
- _EQ008 = A3 & B3 & _LC2_C21 & !SUB
- # A3 & !B3 & _LC2_C21 & SUB
- # !A3 & B3 & _LC2_C21 & SUB
- # !A3 & !B3 & _LC2_C21 & !SUB
- # A3 & B3 & !_LC2_C21 & SUB
- # A3 & !B3 & !_LC2_C21 & !SUB
- # !A3 & B3 & !_LC2_C21 & !SUB
- # !A3 & !B3 & !_LC2_C21 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:9|:11' = '|add32bit:7|add8bit:4|add1bit:9|CO'
- -- Equation name is '_LC3_C18', type is buried
- _LC3_C18 = LCELL( _EQ009);
- _EQ009 = B4 & _LC2_C18 & !SUB
- # !B4 & _LC2_C18 & SUB
- # A4 & _LC2_C18
- # A4 & B4 & !SUB
- # A4 & !B4 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:9|:6' = '|add32bit:7|add8bit:4|add1bit:9|S'
- -- Equation name is '_LC5_C18', type is buried
- _LC5_C18 = LCELL( _EQ010);
- _EQ010 = A4 & B4 & _LC2_C18 & !SUB
- # A4 & !B4 & _LC2_C18 & SUB
- # !A4 & B4 & _LC2_C18 & SUB
- # !A4 & !B4 & _LC2_C18 & !SUB
- # A4 & B4 & !_LC2_C18 & SUB
- # A4 & !B4 & !_LC2_C18 & !SUB
- # !A4 & B4 & !_LC2_C18 & !SUB
- # !A4 & !B4 & !_LC2_C18 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:10|:11' = '|add32bit:7|add8bit:4|add1bit:10|CO'
- -- Equation name is '_LC7_C18', type is buried
- _LC7_C18 = LCELL( _EQ011);
- _EQ011 = B5 & _LC3_C18 & !SUB
- # !B5 & _LC3_C18 & SUB
- # A5 & _LC3_C18
- # A5 & B5 & !SUB
- # A5 & !B5 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:10|:6' = '|add32bit:7|add8bit:4|add1bit:10|S'
- -- Equation name is '_LC6_C18', type is buried
- _LC6_C18 = LCELL( _EQ012);
- _EQ012 = A5 & B5 & _LC3_C18 & !SUB
- # A5 & !B5 & _LC3_C18 & SUB
- # !A5 & B5 & _LC3_C18 & SUB
- # !A5 & !B5 & _LC3_C18 & !SUB
- # A5 & B5 & !_LC3_C18 & SUB
- # A5 & !B5 & !_LC3_C18 & !SUB
- # !A5 & B5 & !_LC3_C18 & !SUB
- # !A5 & !B5 & !_LC3_C18 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:11|:11' = '|add32bit:7|add8bit:4|add1bit:11|CO'
- -- Equation name is '_LC4_C18', type is buried
- _LC4_C18 = LCELL( _EQ013);
- _EQ013 = B6 & _LC7_C18 & !SUB
- # !B6 & _LC7_C18 & SUB
- # A6 & _LC7_C18
- # A6 & B6 & !SUB
- # A6 & !B6 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:11|:6' = '|add32bit:7|add8bit:4|add1bit:11|S'
- -- Equation name is '_LC8_C18', type is buried
- _LC8_C18 = LCELL( _EQ014);
- _EQ014 = A6 & B6 & _LC7_C18 & !SUB
- # A6 & !B6 & _LC7_C18 & SUB
- # !A6 & B6 & _LC7_C18 & SUB
- # !A6 & !B6 & _LC7_C18 & !SUB
- # A6 & B6 & !_LC7_C18 & SUB
- # A6 & !B6 & !_LC7_C18 & !SUB
- # !A6 & B6 & !_LC7_C18 & !SUB
- # !A6 & !B6 & !_LC7_C18 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:12|:11' = '|add32bit:7|add8bit:4|add1bit:12|CO'
- -- Equation name is '_LC3_B20', type is buried
- _LC3_B20 = LCELL( _EQ015);
- _EQ015 = B7 & _LC4_C18 & !SUB
- # !B7 & _LC4_C18 & SUB
- # A7 & _LC4_C18
- # A7 & B7 & !SUB
- # A7 & !B7 & SUB;
- -- Node name is '|add32bit:7|add8bit:4|add1bit:12|:6' = '|add32bit:7|add8bit:4|add1bit:12|S'
- -- Equation name is '_LC1_C18', type is buried
- _LC1_C18 = LCELL( _EQ016);
- _EQ016 = A7 & B7 & _LC4_C18 & !SUB
- # A7 & !B7 & _LC4_C18 & SUB
- # !A7 & B7 & _LC4_C18 & SUB
- # !A7 & !B7 & _LC4_C18 & !SUB
- # A7 & B7 & !_LC4_C18 & SUB
- # A7 & !B7 & !_LC4_C18 & !SUB
- # !A7 & B7 & !_LC4_C18 & !SUB
- # !A7 & !B7 & !_LC4_C18 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:5|:11' = '|add32bit:7|add8bit:5|add1bit:5|CO'
- -- Equation name is '_LC5_B20', type is buried
- _LC5_B20 = LCELL( _EQ017);
- _EQ017 = B8 & _LC3_B20 & !SUB
- # !B8 & _LC3_B20 & SUB
- # A8 & _LC3_B20
- # A8 & B8 & !SUB
- # A8 & !B8 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:5|:6' = '|add32bit:7|add8bit:5|add1bit:5|S'
- -- Equation name is '_LC4_B20', type is buried
- _LC4_B20 = LCELL( _EQ018);
- _EQ018 = A8 & B8 & _LC3_B20 & !SUB
- # A8 & !B8 & _LC3_B20 & SUB
- # !A8 & B8 & _LC3_B20 & SUB
- # !A8 & !B8 & _LC3_B20 & !SUB
- # A8 & B8 & !_LC3_B20 & SUB
- # A8 & !B8 & !_LC3_B20 & !SUB
- # !A8 & B8 & !_LC3_B20 & !SUB
- # !A8 & !B8 & !_LC3_B20 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:6|:11' = '|add32bit:7|add8bit:5|add1bit:6|CO'
- -- Equation name is '_LC7_B20', type is buried
- _LC7_B20 = LCELL( _EQ019);
- _EQ019 = B9 & _LC5_B20 & !SUB
- # !B9 & _LC5_B20 & SUB
- # A9 & _LC5_B20
- # A9 & B9 & !SUB
- # A9 & !B9 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:6|:6' = '|add32bit:7|add8bit:5|add1bit:6|S'
- -- Equation name is '_LC1_B20', type is buried
- _LC1_B20 = LCELL( _EQ020);
- _EQ020 = A9 & B9 & _LC5_B20 & !SUB
- # A9 & !B9 & _LC5_B20 & SUB
- # !A9 & B9 & _LC5_B20 & SUB
- # !A9 & !B9 & _LC5_B20 & !SUB
- # A9 & B9 & !_LC5_B20 & SUB
- # A9 & !B9 & !_LC5_B20 & !SUB
- # !A9 & B9 & !_LC5_B20 & !SUB
- # !A9 & !B9 & !_LC5_B20 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:7|:11' = '|add32bit:7|add8bit:5|add1bit:7|CO'
- -- Equation name is '_LC2_B20', type is buried
- _LC2_B20 = LCELL( _EQ021);
- _EQ021 = B10 & _LC7_B20 & !SUB
- # !B10 & _LC7_B20 & SUB
- # A10 & _LC7_B20
- # A10 & B10 & !SUB
- # A10 & !B10 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:7|:6' = '|add32bit:7|add8bit:5|add1bit:7|S'
- -- Equation name is '_LC8_B20', type is buried
- _LC8_B20 = LCELL( _EQ022);
- _EQ022 = A10 & B10 & _LC7_B20 & !SUB
- # A10 & !B10 & _LC7_B20 & SUB
- # !A10 & B10 & _LC7_B20 & SUB
- # !A10 & !B10 & _LC7_B20 & !SUB
- # A10 & B10 & !_LC7_B20 & SUB
- # A10 & !B10 & !_LC7_B20 & !SUB
- # !A10 & B10 & !_LC7_B20 & !SUB
- # !A10 & !B10 & !_LC7_B20 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:8|:11' = '|add32bit:7|add8bit:5|add1bit:8|CO'
- -- Equation name is '_LC2_B23', type is buried
- _LC2_B23 = LCELL( _EQ023);
- _EQ023 = B11 & _LC2_B20 & !SUB
- # !B11 & _LC2_B20 & SUB
- # A11 & _LC2_B20
- # A11 & B11 & !SUB
- # A11 & !B11 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:8|:6' = '|add32bit:7|add8bit:5|add1bit:8|S'
- -- Equation name is '_LC4_B23', type is buried
- _LC4_B23 = LCELL( _EQ024);
- _EQ024 = A11 & B11 & _LC2_B20 & !SUB
- # A11 & !B11 & _LC2_B20 & SUB
- # !A11 & B11 & _LC2_B20 & SUB
- # !A11 & !B11 & _LC2_B20 & !SUB
- # A11 & B11 & !_LC2_B20 & SUB
- # A11 & !B11 & !_LC2_B20 & !SUB
- # !A11 & B11 & !_LC2_B20 & !SUB
- # !A11 & !B11 & !_LC2_B20 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:9|:11' = '|add32bit:7|add8bit:5|add1bit:9|CO'
- -- Equation name is '_LC7_B23', type is buried
- _LC7_B23 = LCELL( _EQ025);
- _EQ025 = B12 & _LC2_B23 & !SUB
- # !B12 & _LC2_B23 & SUB
- # A12 & _LC2_B23
- # A12 & B12 & !SUB
- # A12 & !B12 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:9|:6' = '|add32bit:7|add8bit:5|add1bit:9|S'
- -- Equation name is '_LC5_B23', type is buried
- _LC5_B23 = LCELL( _EQ026);
- _EQ026 = A12 & B12 & _LC2_B23 & !SUB
- # A12 & !B12 & _LC2_B23 & SUB
- # !A12 & B12 & _LC2_B23 & SUB
- # !A12 & !B12 & _LC2_B23 & !SUB
- # A12 & B12 & !_LC2_B23 & SUB
- # A12 & !B12 & !_LC2_B23 & !SUB
- # !A12 & B12 & !_LC2_B23 & !SUB
- # !A12 & !B12 & !_LC2_B23 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:10|:11' = '|add32bit:7|add8bit:5|add1bit:10|CO'
- -- Equation name is '_LC8_B23', type is buried
- _LC8_B23 = LCELL( _EQ027);
- _EQ027 = B13 & _LC7_B23 & !SUB
- # !B13 & _LC7_B23 & SUB
- # A13 & _LC7_B23
- # A13 & B13 & !SUB
- # A13 & !B13 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:10|:6' = '|add32bit:7|add8bit:5|add1bit:10|S'
- -- Equation name is '_LC3_B23', type is buried
- _LC3_B23 = LCELL( _EQ028);
- _EQ028 = A13 & B13 & _LC7_B23 & !SUB
- # A13 & !B13 & _LC7_B23 & SUB
- # !A13 & B13 & _LC7_B23 & SUB
- # !A13 & !B13 & _LC7_B23 & !SUB
- # A13 & B13 & !_LC7_B23 & SUB
- # A13 & !B13 & !_LC7_B23 & !SUB
- # !A13 & B13 & !_LC7_B23 & !SUB
- # !A13 & !B13 & !_LC7_B23 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:11|:11' = '|add32bit:7|add8bit:5|add1bit:11|CO'
- -- Equation name is '_LC1_B23', type is buried
- _LC1_B23 = LCELL( _EQ029);
- _EQ029 = B14 & _LC8_B23 & !SUB
- # !B14 & _LC8_B23 & SUB
- # A14 & _LC8_B23
- # A14 & B14 & !SUB
- # A14 & !B14 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:11|:6' = '|add32bit:7|add8bit:5|add1bit:11|S'
- -- Equation name is '_LC6_B23', type is buried
- _LC6_B23 = LCELL( _EQ030);
- _EQ030 = A14 & B14 & _LC8_B23 & !SUB
- # A14 & !B14 & _LC8_B23 & SUB
- # !A14 & B14 & _LC8_B23 & SUB
- # !A14 & !B14 & _LC8_B23 & !SUB
- # A14 & B14 & !_LC8_B23 & SUB
- # A14 & !B14 & !_LC8_B23 & !SUB
- # !A14 & B14 & !_LC8_B23 & !SUB
- # !A14 & !B14 & !_LC8_B23 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:12|:11' = '|add32bit:7|add8bit:5|add1bit:12|CO'
- -- Equation name is '_LC1_A19', type is buried
- _LC1_A19 = LCELL( _EQ031);
- _EQ031 = B15 & _LC1_B23 & !SUB
- # !B15 & _LC1_B23 & SUB
- # A15 & _LC1_B23
- # A15 & B15 & !SUB
- # A15 & !B15 & SUB;
- -- Node name is '|add32bit:7|add8bit:5|add1bit:12|:6' = '|add32bit:7|add8bit:5|add1bit:12|S'
- -- Equation name is '_LC4_A19', type is buried
- _LC4_A19 = LCELL( _EQ032);
- _EQ032 = A15 & B15 & _LC1_B23 & !SUB
- # A15 & !B15 & _LC1_B23 & SUB
- # !A15 & B15 & _LC1_B23 & SUB
- # !A15 & !B15 & _LC1_B23 & !SUB
- # A15 & B15 & !_LC1_B23 & SUB
- # A15 & !B15 & !_LC1_B23 & !SUB
- # !A15 & B15 & !_LC1_B23 & !SUB
- # !A15 & !B15 & !_LC1_B23 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:5|:11' = '|add32bit:7|add8bit:6|add1bit:5|CO'
- -- Equation name is '_LC3_A19', type is buried
- _LC3_A19 = LCELL( _EQ033);
- _EQ033 = B16 & _LC1_A19 & !SUB
- # !B16 & _LC1_A19 & SUB
- # A16 & _LC1_A19
- # A16 & B16 & !SUB
- # A16 & !B16 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:5|:6' = '|add32bit:7|add8bit:6|add1bit:5|S'
- -- Equation name is '_LC2_A19', type is buried
- _LC2_A19 = LCELL( _EQ034);
- _EQ034 = A16 & B16 & _LC1_A19 & !SUB
- # A16 & !B16 & _LC1_A19 & SUB
- # !A16 & B16 & _LC1_A19 & SUB
- # !A16 & !B16 & _LC1_A19 & !SUB
- # A16 & B16 & !_LC1_A19 & SUB
- # A16 & !B16 & !_LC1_A19 & !SUB
- # !A16 & B16 & !_LC1_A19 & !SUB
- # !A16 & !B16 & !_LC1_A19 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:6|:11' = '|add32bit:7|add8bit:6|add1bit:6|CO'
- -- Equation name is '_LC6_A19', type is buried
- _LC6_A19 = LCELL( _EQ035);
- _EQ035 = B17 & _LC3_A19 & !SUB
- # !B17 & _LC3_A19 & SUB
- # A17 & _LC3_A19
- # A17 & B17 & !SUB
- # A17 & !B17 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:6|:6' = '|add32bit:7|add8bit:6|add1bit:6|S'
- -- Equation name is '_LC5_A19', type is buried
- _LC5_A19 = LCELL( _EQ036);
- _EQ036 = A17 & B17 & _LC3_A19 & !SUB
- # A17 & !B17 & _LC3_A19 & SUB
- # !A17 & B17 & _LC3_A19 & SUB
- # !A17 & !B17 & _LC3_A19 & !SUB
- # A17 & B17 & !_LC3_A19 & SUB
- # A17 & !B17 & !_LC3_A19 & !SUB
- # !A17 & B17 & !_LC3_A19 & !SUB
- # !A17 & !B17 & !_LC3_A19 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:7|:11' = '|add32bit:7|add8bit:6|add1bit:7|CO'
- -- Equation name is '_LC7_A19', type is buried
- _LC7_A19 = LCELL( _EQ037);
- _EQ037 = B18 & _LC6_A19 & !SUB
- # !B18 & _LC6_A19 & SUB
- # A18 & _LC6_A19
- # A18 & B18 & !SUB
- # A18 & !B18 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:7|:6' = '|add32bit:7|add8bit:6|add1bit:7|S'
- -- Equation name is '_LC8_A19', type is buried
- _LC8_A19 = LCELL( _EQ038);
- _EQ038 = A18 & B18 & _LC6_A19 & !SUB
- # A18 & !B18 & _LC6_A19 & SUB
- # !A18 & B18 & _LC6_A19 & SUB
- # !A18 & !B18 & _LC6_A19 & !SUB
- # A18 & B18 & !_LC6_A19 & SUB
- # A18 & !B18 & !_LC6_A19 & !SUB
- # !A18 & B18 & !_LC6_A19 & !SUB
- # !A18 & !B18 & !_LC6_A19 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:8|:11' = '|add32bit:7|add8bit:6|add1bit:8|CO'
- -- Equation name is '_LC2_A5', type is buried
- _LC2_A5 = LCELL( _EQ039);
- _EQ039 = B19 & _LC7_A19 & !SUB
- # !B19 & _LC7_A19 & SUB
- # A19 & _LC7_A19
- # A19 & B19 & !SUB
- # A19 & !B19 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:8|:6' = '|add32bit:7|add8bit:6|add1bit:8|S'
- -- Equation name is '_LC8_A5', type is buried
- _LC8_A5 = LCELL( _EQ040);
- _EQ040 = A19 & B19 & _LC7_A19 & !SUB
- # A19 & !B19 & _LC7_A19 & SUB
- # !A19 & B19 & _LC7_A19 & SUB
- # !A19 & !B19 & _LC7_A19 & !SUB
- # A19 & B19 & !_LC7_A19 & SUB
- # A19 & !B19 & !_LC7_A19 & !SUB
- # !A19 & B19 & !_LC7_A19 & !SUB
- # !A19 & !B19 & !_LC7_A19 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:9|:11' = '|add32bit:7|add8bit:6|add1bit:9|CO'
- -- Equation name is '_LC6_A5', type is buried
- _LC6_A5 = LCELL( _EQ041);
- _EQ041 = B20 & _LC2_A5 & !SUB
- # !B20 & _LC2_A5 & SUB
- # A20 & _LC2_A5
- # A20 & B20 & !SUB
- # A20 & !B20 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:9|:6' = '|add32bit:7|add8bit:6|add1bit:9|S'
- -- Equation name is '_LC5_A5', type is buried
- _LC5_A5 = LCELL( _EQ042);
- _EQ042 = A20 & B20 & _LC2_A5 & !SUB
- # A20 & !B20 & _LC2_A5 & SUB
- # !A20 & B20 & _LC2_A5 & SUB
- # !A20 & !B20 & _LC2_A5 & !SUB
- # A20 & B20 & !_LC2_A5 & SUB
- # A20 & !B20 & !_LC2_A5 & !SUB
- # !A20 & B20 & !_LC2_A5 & !SUB
- # !A20 & !B20 & !_LC2_A5 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:10|:11' = '|add32bit:7|add8bit:6|add1bit:10|CO'
- -- Equation name is '_LC7_A5', type is buried
- _LC7_A5 = LCELL( _EQ043);
- _EQ043 = B21 & _LC6_A5 & !SUB
- # !B21 & _LC6_A5 & SUB
- # A21 & _LC6_A5
- # A21 & B21 & !SUB
- # A21 & !B21 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:10|:6' = '|add32bit:7|add8bit:6|add1bit:10|S'
- -- Equation name is '_LC4_A5', type is buried
- _LC4_A5 = LCELL( _EQ044);
- _EQ044 = A21 & B21 & _LC6_A5 & !SUB
- # A21 & !B21 & _LC6_A5 & SUB
- # !A21 & B21 & _LC6_A5 & SUB
- # !A21 & !B21 & _LC6_A5 & !SUB
- # A21 & B21 & !_LC6_A5 & SUB
- # A21 & !B21 & !_LC6_A5 & !SUB
- # !A21 & B21 & !_LC6_A5 & !SUB
- # !A21 & !B21 & !_LC6_A5 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:11|:11' = '|add32bit:7|add8bit:6|add1bit:11|CO'
- -- Equation name is '_LC1_A5', type is buried
- _LC1_A5 = LCELL( _EQ045);
- _EQ045 = B22 & _LC7_A5 & !SUB
- # !B22 & _LC7_A5 & SUB
- # A22 & _LC7_A5
- # A22 & B22 & !SUB
- # A22 & !B22 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:11|:6' = '|add32bit:7|add8bit:6|add1bit:11|S'
- -- Equation name is '_LC3_A5', type is buried
- _LC3_A5 = LCELL( _EQ046);
- _EQ046 = A22 & B22 & _LC7_A5 & !SUB
- # A22 & !B22 & _LC7_A5 & SUB
- # !A22 & B22 & _LC7_A5 & SUB
- # !A22 & !B22 & _LC7_A5 & !SUB
- # A22 & B22 & !_LC7_A5 & SUB
- # A22 & !B22 & !_LC7_A5 & !SUB
- # !A22 & B22 & !_LC7_A5 & !SUB
- # !A22 & !B22 & !_LC7_A5 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:12|:11' = '|add32bit:7|add8bit:6|add1bit:12|CO'
- -- Equation name is '_LC3_B6', type is buried
- _LC3_B6 = LCELL( _EQ047);
- _EQ047 = B23 & _LC1_A5 & !SUB
- # !B23 & _LC1_A5 & SUB
- # A23 & _LC1_A5
- # A23 & B23 & !SUB
- # A23 & !B23 & SUB;
- -- Node name is '|add32bit:7|add8bit:6|add1bit:12|:6' = '|add32bit:7|add8bit:6|add1bit:12|S'
- -- Equation name is '_LC6_B20', type is buried
- _LC6_B20 = LCELL( _EQ048);
- _EQ048 = A23 & B23 & _LC1_A5 & !SUB
- # A23 & !B23 & _LC1_A5 & SUB
- # !A23 & B23 & _LC1_A5 & SUB
- # !A23 & !B23 & _LC1_A5 & !SUB
- # A23 & B23 & !_LC1_A5 & SUB
- # A23 & !B23 & !_LC1_A5 & !SUB
- # !A23 & B23 & !_LC1_A5 & !SUB
- # !A23 & !B23 & !_LC1_A5 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:5|:11' = '|add32bit:7|add8bit:7|add1bit:5|CO'
- -- Equation name is '_LC4_B6', type is buried
- _LC4_B6 = LCELL( _EQ049);
- _EQ049 = B24 & _LC3_B6 & !SUB
- # !B24 & _LC3_B6 & SUB
- # A24 & _LC3_B6
- # A24 & B24 & !SUB
- # A24 & !B24 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:5|:6' = '|add32bit:7|add8bit:7|add1bit:5|S'
- -- Equation name is '_LC1_B6', type is buried
- _LC1_B6 = LCELL( _EQ050);
- _EQ050 = A24 & B24 & _LC3_B6 & !SUB
- # A24 & !B24 & _LC3_B6 & SUB
- # !A24 & B24 & _LC3_B6 & SUB
- # !A24 & !B24 & _LC3_B6 & !SUB
- # A24 & B24 & !_LC3_B6 & SUB
- # A24 & !B24 & !_LC3_B6 & !SUB
- # !A24 & B24 & !_LC3_B6 & !SUB
- # !A24 & !B24 & !_LC3_B6 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:6|:11' = '|add32bit:7|add8bit:7|add1bit:6|CO'
- -- Equation name is '_LC7_B6', type is buried
- _LC7_B6 = LCELL( _EQ051);
- _EQ051 = B25 & _LC4_B6 & !SUB
- # !B25 & _LC4_B6 & SUB
- # A25 & _LC4_B6
- # A25 & B25 & !SUB
- # A25 & !B25 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:6|:6' = '|add32bit:7|add8bit:7|add1bit:6|S'
- -- Equation name is '_LC6_B6', type is buried
- _LC6_B6 = LCELL( _EQ052);
- _EQ052 = A25 & B25 & _LC4_B6 & !SUB
- # A25 & !B25 & _LC4_B6 & SUB
- # !A25 & B25 & _LC4_B6 & SUB
- # !A25 & !B25 & _LC4_B6 & !SUB
- # A25 & B25 & !_LC4_B6 & SUB
- # A25 & !B25 & !_LC4_B6 & !SUB
- # !A25 & B25 & !_LC4_B6 & !SUB
- # !A25 & !B25 & !_LC4_B6 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:7|:11' = '|add32bit:7|add8bit:7|add1bit:7|CO'
- -- Equation name is '_LC2_B6', type is buried
- _LC2_B6 = LCELL( _EQ053);
- _EQ053 = B26 & _LC7_B6 & !SUB
- # !B26 & _LC7_B6 & SUB
- # A26 & _LC7_B6
- # A26 & B26 & !SUB
- # A26 & !B26 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:7|:6' = '|add32bit:7|add8bit:7|add1bit:7|S'
- -- Equation name is '_LC5_B6', type is buried
- _LC5_B6 = LCELL( _EQ054);
- _EQ054 = A26 & B26 & _LC7_B6 & !SUB
- # A26 & !B26 & _LC7_B6 & SUB
- # !A26 & B26 & _LC7_B6 & SUB
- # !A26 & !B26 & _LC7_B6 & !SUB
- # A26 & B26 & !_LC7_B6 & SUB
- # A26 & !B26 & !_LC7_B6 & !SUB
- # !A26 & B26 & !_LC7_B6 & !SUB
- # !A26 & !B26 & !_LC7_B6 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:8|:11' = '|add32bit:7|add8bit:7|add1bit:8|CO'
- -- Equation name is '_LC2_B8', type is buried
- _LC2_B8 = LCELL( _EQ055);
- _EQ055 = B27 & _LC2_B6 & !SUB
- # !B27 & _LC2_B6 & SUB
- # A27 & _LC2_B6
- # A27 & B27 & !SUB
- # A27 & !B27 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:8|:6' = '|add32bit:7|add8bit:7|add1bit:8|S'
- -- Equation name is '_LC3_B8', type is buried
- _LC3_B8 = LCELL( _EQ056);
- _EQ056 = A27 & B27 & _LC2_B6 & !SUB
- # A27 & !B27 & _LC2_B6 & SUB
- # !A27 & B27 & _LC2_B6 & SUB
- # !A27 & !B27 & _LC2_B6 & !SUB
- # A27 & B27 & !_LC2_B6 & SUB
- # A27 & !B27 & !_LC2_B6 & !SUB
- # !A27 & B27 & !_LC2_B6 & !SUB
- # !A27 & !B27 & !_LC2_B6 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:9|:11' = '|add32bit:7|add8bit:7|add1bit:9|CO'
- -- Equation name is '_LC7_B8', type is buried
- _LC7_B8 = LCELL( _EQ057);
- _EQ057 = B28 & _LC2_B8 & !SUB
- # !B28 & _LC2_B8 & SUB
- # A28 & _LC2_B8
- # A28 & B28 & !SUB
- # A28 & !B28 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:9|:6' = '|add32bit:7|add8bit:7|add1bit:9|S'
- -- Equation name is '_LC4_B8', type is buried
- _LC4_B8 = LCELL( _EQ058);
- _EQ058 = A28 & B28 & _LC2_B8 & !SUB
- # A28 & !B28 & _LC2_B8 & SUB
- # !A28 & B28 & _LC2_B8 & SUB
- # !A28 & !B28 & _LC2_B8 & !SUB
- # A28 & B28 & !_LC2_B8 & SUB
- # A28 & !B28 & !_LC2_B8 & !SUB
- # !A28 & B28 & !_LC2_B8 & !SUB
- # !A28 & !B28 & !_LC2_B8 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:10|:11' = '|add32bit:7|add8bit:7|add1bit:10|CO'
- -- Equation name is '_LC8_B8', type is buried
- _LC8_B8 = LCELL( _EQ059);
- _EQ059 = B29 & _LC7_B8 & !SUB
- # !B29 & _LC7_B8 & SUB
- # A29 & _LC7_B8
- # A29 & B29 & !SUB
- # A29 & !B29 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:10|:6' = '|add32bit:7|add8bit:7|add1bit:10|S'
- -- Equation name is '_LC6_B8', type is buried
- _LC6_B8 = LCELL( _EQ060);
- _EQ060 = A29 & B29 & _LC7_B8 & !SUB
- # A29 & !B29 & _LC7_B8 & SUB
- # !A29 & B29 & _LC7_B8 & SUB
- # !A29 & !B29 & _LC7_B8 & !SUB
- # A29 & B29 & !_LC7_B8 & SUB
- # A29 & !B29 & !_LC7_B8 & !SUB
- # !A29 & B29 & !_LC7_B8 & !SUB
- # !A29 & !B29 & !_LC7_B8 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:11|:6' = '|add32bit:7|add8bit:7|add1bit:11|S'
- -- Equation name is '_LC5_B8', type is buried
- _LC5_B8 = LCELL( _EQ061);
- _EQ061 = A30 & B30 & _LC8_B8 & !SUB
- # A30 & !B30 & _LC8_B8 & SUB
- # !A30 & B30 & _LC8_B8 & SUB
- # !A30 & !B30 & _LC8_B8 & !SUB
- # A30 & B30 & !_LC8_B8 & SUB
- # A30 & !B30 & !_LC8_B8 & !SUB
- # !A30 & B30 & !_LC8_B8 & !SUB
- # !A30 & !B30 & !_LC8_B8 & SUB;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:12|:6' = '|add32bit:7|add8bit:7|add1bit:12|S'
- -- Equation name is '_LC1_B9', type is buried
- _LC1_B9 = LCELL( _EQ062);
- _EQ062 = A31 & B31 & _LC1_B8
- # !A31 & !B31 & _LC1_B8
- # A31 & !B31 & !_LC1_B8
- # !A31 & B31 & !_LC1_B8;
- -- Node name is '|add32bit:7|add8bit:7|add1bit:12|~6~1' = '|add32bit:7|add8bit:7|add1bit:12|S~1'
- -- Equation name is '_LC1_B8', type is buried
- -- synthesized logic cell
- _LC1_B8 = LCELL( _EQ063);
- _EQ063 = B30 & _LC8_B8 & !SUB
- # A30 & B30 & !SUB
- # A30 & _LC8_B8 & !SUB
- # !A30 & B30 & SUB
- # B30 & !_LC8_B8 & SUB
- # !A30 & !_LC8_B8 & SUB;
- Project Information e:doucumentsprojectsmips__1080379086as32.rpt
- ** COMPILATION SETTINGS & TIMES **
- Processing Menu Commands
- ------------------------
- Design Doctor = off
- Logic Synthesis:
- Synthesis Type Used = Multi-Level
- Default Synthesis Style = NORMAL
- Logic option settings in 'NORMAL' style for 'FLEX10K' family
- CARRY_CHAIN = ignore
- CARRY_CHAIN_LENGTH = 32
- CASCADE_CHAIN = ignore
- CASCADE_CHAIN_LENGTH = 2
- DECOMPOSE_GATES = on
- DUPLICATE_LOGIC_EXTRACTION = on
- MINIMIZATION = full
- MULTI_LEVEL_FACTORING = on
- NOT_GATE_PUSH_BACK = on
- REDUCE_LOGIC = on
- REFACTORIZATION = on
- REGISTER_OPTIMIZATION = on
- RESYNTHESIZE_NETWORK = on
- SLOW_SLEW_RATE = off
- SUBFACTOR_EXTRACTION = on
- IGNORE_SOFT_BUFFERS = on
- USE_LPM_FOR_AHDL_OPERATORS = off
- Other logic synthesis settings:
- Automatic Global Clock = on
- Automatic Global Clear = on
- Automatic Global Preset = on
- Automatic Global Output Enable = on
- Automatic Fast I/O = off
- Automatic Register Packing = off
- Automatic Open-Drain Pins = on
- Automatic Implement in EAB = off
- Optimize = 5
- Default Timing Specifications: None
- Cut All Bidir Feedback Timing Paths = on
- Cut All Clear & Preset Timing Paths = on
- Ignore Timing Assignments = on
- Functional SNF Extractor = off
- Linked SNF Extractor = off
- Timing SNF Extractor = on
- Optimize Timing SNF = off
- Generate AHDL TDO File = off
- Fitter Settings = NORMAL
- Use Quartus Fitter = on
- Smart Recompile = off
- Total Recompile = off
- Interfaces Menu Commands
- ------------------------
- EDIF Netlist Writer = off
- Verilog Netlist Writer = off
- VHDL Netlist Writer = off
- Compilation Times
- -----------------
- Compiler Netlist Extractor 00:00:00
- Database Builder 00:00:00
- Logic Synthesizer 00:00:00
- Partitioner 00:00:01
- Fitter 00:00:01
- Timing SNF Extractor 00:00:00
- Assembler 00:00:00
- -------------------------- --------
- Total Time 00:00:02
- Memory Allocated
- -----------------
- Peak memory allocated during compilation = 10,447K
