English
add32bit.rpt
资源名称：mips.rar [点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：56k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Project Information e:doucumentsprojectsmips_1080379086add32bit.rpt
- MAX+plus II Compiler Report File
- Version 10.0 9/14/2000
- Compiled: 12/02/2008 16:56:27
- Copyright (C) 1988-2000 Altera Corporation
- Any megafunction design, and related net list (encrypted or decrypted),
- support information, device programming or simulation file, and any other
- associated documentation or information provided by Altera or a partner
- under Altera's Megafunction Partnership Program may be used only to
- program PLD devices (but not masked PLD devices) from Altera. Any other
- use of such megafunction design, net list, support information, device
- programming or simulation file, or any other related documentation or
- information is prohibited for any other purpose, including, but not
- limited to modification, reverse engineering, de-compiling, or use with
- any other silicon devices, unless such use is explicitly licensed under
- a separate agreement with Altera or a megafunction partner. Title to
- the intellectual property, including patents, copyrights, trademarks,
- trade secrets, or maskworks, embodied in any such megafunction design,
- net list, support information, device programming or simulation file, or
- any other related documentation or information provided by Altera or a
- megafunction partner, remains with Altera, the megafunction partner, or
- their respective licensors. No other licenses, including any licenses
- needed under any third party's intellectual property, are provided herein.
- ***** Project compilation was successful
- ** DEVICE SUMMARY **
- Chip/ Input Output Bidir Memory Memory LCs
- POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
- add32bit EPF10K10TC144-3 65 32 0 0 0 % 63 10 %
- User Pins: 65 32 0
- Project Information e:doucumentsprojectsmips_1080379086add32bit.rpt
- ** FILE HIERARCHY **
- |add8bit:4|
- |add8bit:4|add1bit:5|
- |add8bit:4|add1bit:12|
- |add8bit:4|add1bit:11|
- |add8bit:4|add1bit:10|
- |add8bit:4|add1bit:9|
- |add8bit:4|add1bit:8|
- |add8bit:4|add1bit:7|
- |add8bit:4|add1bit:6|
- |add8bit:7|
- |add8bit:7|add1bit:5|
- |add8bit:7|add1bit:12|
- |add8bit:7|add1bit:11|
- |add8bit:7|add1bit:10|
- |add8bit:7|add1bit:9|
- |add8bit:7|add1bit:8|
- |add8bit:7|add1bit:7|
- |add8bit:7|add1bit:6|
- |add8bit:6|
- |add8bit:6|add1bit:5|
- |add8bit:6|add1bit:12|
- |add8bit:6|add1bit:11|
- |add8bit:6|add1bit:10|
- |add8bit:6|add1bit:9|
- |add8bit:6|add1bit:8|
- |add8bit:6|add1bit:7|
- |add8bit:6|add1bit:6|
- |add8bit:5|
- |add8bit:5|add1bit:5|
- |add8bit:5|add1bit:12|
- |add8bit:5|add1bit:11|
- |add8bit:5|add1bit:10|
- |add8bit:5|add1bit:9|
- |add8bit:5|add1bit:8|
- |add8bit:5|add1bit:7|
- |add8bit:5|add1bit:6|
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ***** Logic for device 'add32bit' compiled without errors.
- Device: EPF10K10TC144-3
- FLEX 10K Configuration Scheme: Passive Serial
- Device Options:
- User-Supplied Start-Up Clock = OFF
- Auto-Restart Configuration on Frame Error = OFF
- Release Clears Before Tri-States = OFF
- Enable Chip_Wide Reset = OFF
- Enable Chip-Wide Output Enable = OFF
- Enable INIT_DONE Output = OFF
- JTAG User Code = 7f
- MultiVolt I/O = OFF
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** ERROR SUMMARY **
- Info: Chip 'add32bit' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
- R R R
- E E E
- S G V S S
- E G V G N C E V E
- R N C N D C R C R
- S V D B A C B B B D S I I V A B B A S C B V B A B B
- 2 A A B E I A A 3 1 I 3 2 2 B I 1 N C A B N E B 1 2 1 1 2 I 1 E 2 2 2 1
- 8 7 4 5 D O 8 9 1 0 O 0 9 7 6 O 0 T I 1 0 T D 1 4 3 4 6 5 O 3 D 2 0 6 8
- --------------------------------------------------------------------------_
- / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
- / 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
- #TCK | 1 108 | ^DATA0
- ^CONF_DONE | 2 107 | ^DCLK
- ^nCEO | 3 106 | ^nCE
- #TDO | 4 105 | #TDI
- VCCIO | 5 104 | GNDIO
- VCCINT | 6 103 | GNDINT
- B3 | 7 102 | S26
- S27 | 8 101 | B25
- A26 | 9 100 | A24
- S6 | 10 99 | A5
- A23 | 11 98 | S23
- S3 | 12 97 | B4
- S4 | 13 96 | A30
- S29 | 14 95 | S24
- GNDIO | 15 94 | VCCIO
- GNDINT | 16 93 | VCCINT
- B20 | 17 92 | S21
- A17 | 18 91 | S15
- A15 | 19 EPF10K10TC144-3 90 | S16
- A21 | 20 89 | S19
- B19 | 21 88 | S20
- A19 | 22 87 | S22
- B17 | 23 86 | S18
- VCCIO | 24 85 | GNDIO
- VCCINT | 25 84 | GNDINT
- S2 | 26 83 | S13
- S9 | 27 82 | S7
- S8 | 28 81 | S1
- A13 | 29 80 | S14
- B12 | 30 79 | S12
- B7 | 31 78 | A12
- B8 | 32 77 | ^MSEL0
- S11 | 33 76 | ^MSEL1
- #TMS | 34 75 | VCCINT
- ^nSTATUS | 35 74 | ^nCONFIG
- B9 | 36 73 | B21
- | 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
- 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
- ---------------------------------------------------------------------------
- S S A G B A B A V A S A R G A V V B A A G G A B V A S A A G S B B R V B
- 3 3 3 N 2 2 1 2 C 2 5 3 E N 6 C C 1 0 1 N N 2 2 C 1 0 2 2 N 1 1 2 E C 1
- 0 1 D 8 8 0 7 C 9 1 S D C C 1 1 D D C 8 5 2 D 7 6 4 S C 5
- I I E I I I I I I I E I
- O O R O N N N N O O R O
- V T T T T V
- E E
- D D
- N.C. = No Connect. This pin has no internal connection to the device.
- VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
- GNDIO = Dedicated ground pin, which MUST be connected to GND.
- RESERVED = Unused I/O pin, which MUST be left unconnected.
- ^ = Dedicated configuration pin.
- + = Reserved configuration pin, which is tri-stated during user mode.
- * = Reserved configuration pin, which drives out in user mode.
- PDn = Power Down pin.
- @ = Special-purpose pin.
- # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
- & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** RESOURCE USAGE **
- Logic Column Row
- Array Interconnect Interconnect Clears/ External
- Block Logic Cells Driven Driven Clocks Presets Interconnect
- A5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
- A16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
- A22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
- A24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
- B7 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
- B8 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
- C10 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
- C11 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
- C13 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
- C20 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
- Embedded Column Row
- Array Embedded Interconnect Interconnect Read/ External
- Block Cells Driven Driven Clocks Write Interconnect
- Total dedicated input pins used: 6/6 (100%)
- Total I/O pins used: 91/96 ( 94%)
- Total logic cells used: 63/576 ( 10%)
- Total embedded cells used: 0/24 ( 0%)
- Total EABs used: 0/3 ( 0%)
- Average fan-in: 3.00/4 ( 75%)
- Total fan-in: 189/2304 ( 8%)
- Total input pins required: 65
- Total input I/O cell registers required: 0
- Total output pins required: 32
- Total output I/O cell registers required: 0
- Total buried I/O cell registers required: 0
- Total bidirectional pins required: 0
- Total reserved pins required 0
- Total logic cells required: 63
- Total flipflops required: 0
- Total packed registers required: 0
- Total logic cells in carry chains: 0
- Total number of carry chains: 0
- Total logic cells in cascade chains: 0
- Total number of cascade chains: 0
- Total single-pin Clock Enables required: 0
- Total single-pin Output Enables required: 0
- Synthesized logic cells: 0/ 576 ( 0%)
- Logic Cell and Embedded Cell Counts
- Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
- A: 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 1 0 8 25/0
- B: 0 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
- C: 0 0 0 0 0 0 0 0 0 7 6 0 0 7 0 0 0 0 0 0 2 0 0 0 0 22/0
- Total: 0 0 0 0 8 0 8 8 0 7 6 0 0 7 0 0 8 0 0 0 2 0 1 0 8 63/0
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** INPUTS **
- Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 55 - - - -- INPUT 0 0 0 2 A0
- 125 - - - -- INPUT 0 0 0 2 A1
- 59 - - - 12 INPUT 0 0 0 2 A2
- 39 - - - 21 INPUT 0 0 0 2 A3
- 142 - - - 23 INPUT 0 0 0 2 A4
- 99 - - A -- INPUT 0 0 0 2 A5
- 51 - - - 13 INPUT 0 0 0 2 A6
- 143 - - - 24 INPUT 0 0 0 2 A7
- 138 - - - 20 INPUT 0 0 0 2 A8
- 137 - - - 19 INPUT 0 0 0 2 A9
- 135 - - - 18 INPUT 0 0 0 2 A10
- 56 - - - -- INPUT 0 0 0 2 A11
- 78 - - C -- INPUT 0 0 0 2 A12
- 29 - - C -- INPUT 0 0 0 2 A13
- 120 - - - 09 INPUT 0 0 0 2 A14
- 19 - - B -- INPUT 0 0 0 2 A15
- 117 - - - 06 INPUT 0 0 0 2 A16
- 18 - - B -- INPUT 0 0 0 2 A17
- 62 - - - 11 INPUT 0 0 0 2 A18
- 22 - - B -- INPUT 0 0 0 2 A19
- 111 - - - 02 INPUT 0 0 0 2 A20
- 20 - - B -- INPUT 0 0 0 2 A21
- 65 - - - 09 INPUT 0 0 0 2 A22
- 11 - - A -- INPUT 0 0 0 2 A23
- 100 - - A -- INPUT 0 0 0 2 A24
- 64 - - - 10 INPUT 0 0 0 2 A25
- 9 - - A -- INPUT 0 0 0 2 A26
- 44 - - - 18 INPUT 0 0 0 2 A27
- 42 - - - 19 INPUT 0 0 0 2 A28
- 46 - - - 17 INPUT 0 0 0 2 A29
- 96 - - A -- INPUT 0 0 0 2 A30
- 48 - - - 15 INPUT 0 0 0 1 A31
- 124 - - - -- INPUT 0 0 0 2 B0
- 121 - - - 10 INPUT 0 0 0 2 B1
- 60 - - - 12 INPUT 0 0 0 2 B2
- 7 - - A -- INPUT 0 0 0 2 B3
- 97 - - A -- INPUT 0 0 0 2 B4
- 141 - - - 22 INPUT 0 0 0 2 B5
- 130 - - - 14 INPUT 0 0 0 2 B6
- 31 - - C -- INPUT 0 0 0 2 B7
- 32 - - C -- INPUT 0 0 0 2 B8
- 36 - - - 24 INPUT 0 0 0 2 B9
- 43 - - - 18 INPUT 0 0 0 2 B10
- 54 - - - -- INPUT 0 0 0 2 B11
- 30 - - C -- INPUT 0 0 0 2 B12
- 114 - - - 04 INPUT 0 0 0 2 B13
- 118 - - - 07 INPUT 0 0 0 2 B14
- 72 - - - 04 INPUT 0 0 0 2 B15
- 68 - - - 07 INPUT 0 0 0 2 B16
- 23 - - B -- INPUT 0 0 0 2 B17
- 109 - - - 01 INPUT 0 0 0 2 B18
- 21 - - B -- INPUT 0 0 0 2 B19
- 17 - - B -- INPUT 0 0 0 2 B20
- 73 - - - 02 INPUT 0 0 0 2 B21
- 112 - - - 03 INPUT 0 0 0 2 B22
- 119 - - - 08 INPUT 0 0 0 2 B23
- 69 - - - 06 INPUT 0 0 0 2 B24
- 101 - - A -- INPUT 0 0 0 2 B25
- 110 - - - 01 INPUT 0 0 0 2 B26
- 131 - - - 15 INPUT 0 0 0 2 B27
- 41 - - - 20 INPUT 0 0 0 2 B28
- 132 - - - 16 INPUT 0 0 0 2 B29
- 133 - - - 17 INPUT 0 0 0 2 B30
- 136 - - - 19 INPUT 0 0 0 1 B31
- 126 - - - -- INPUT 0 0 0 2 CI
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** OUTPUTS **
- Fed By Fed By Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 63 - - - 11 OUTPUT 0 1 0 0 S0
- 81 - - C -- OUTPUT 0 1 0 0 S1
- 26 - - C -- OUTPUT 0 1 0 0 S2
- 12 - - A -- OUTPUT 0 1 0 0 S3
- 13 - - A -- OUTPUT 0 1 0 0 S4
- 47 - - - 16 OUTPUT 0 1 0 0 S5
- 10 - - A -- OUTPUT 0 1 0 0 S6
- 82 - - C -- OUTPUT 0 1 0 0 S7
- 28 - - C -- OUTPUT 0 1 0 0 S8
- 27 - - C -- OUTPUT 0 1 0 0 S9
- 128 - - - 13 OUTPUT 0 1 0 0 S10
- 33 - - C -- OUTPUT 0 1 0 0 S11
- 79 - - C -- OUTPUT 0 1 0 0 S12
- 83 - - C -- OUTPUT 0 1 0 0 S13
- 80 - - C -- OUTPUT 0 1 0 0 S14
- 91 - - B -- OUTPUT 0 1 0 0 S15
- 90 - - B -- OUTPUT 0 1 0 0 S16
- 67 - - - 08 OUTPUT 0 1 0 0 S17
- 86 - - B -- OUTPUT 0 1 0 0 S18
- 89 - - B -- OUTPUT 0 1 0 0 S19
- 88 - - B -- OUTPUT 0 1 0 0 S20
- 92 - - B -- OUTPUT 0 1 0 0 S21
- 87 - - B -- OUTPUT 0 1 0 0 S22
- 98 - - A -- OUTPUT 0 1 0 0 S23
- 95 - - A -- OUTPUT 0 1 0 0 S24
- 116 - - - 05 OUTPUT 0 1 0 0 S25
- 102 - - A -- OUTPUT 0 1 0 0 S26
- 8 - - A -- OUTPUT 0 1 0 0 S27
- 144 - - - 24 OUTPUT 0 1 0 0 S28
- 14 - - A -- OUTPUT 0 1 0 0 S29
- 37 - - - 23 OUTPUT 0 1 0 0 S30
- 38 - - - 22 OUTPUT 0 1 0 0 S31
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** BURIED LOGIC **
- Fan-In Fan-Out
- IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 2 - C 11 OR2 3 0 1 0 |add8bit:4|add1bit:5|S (|add8bit:4|add1bit:5|:6)
- - 4 - C 11 OR2 3 0 0 2 |add8bit:4|add1bit:5|CO (|add8bit:4|add1bit:5|:11)
- - 3 - C 11 OR2 2 1 1 0 |add8bit:4|add1bit:6|S (|add8bit:4|add1bit:6|:6)
- - 5 - C 11 OR2 2 1 0 2 |add8bit:4|add1bit:6|CO (|add8bit:4|add1bit:6|:11)
- - 1 - C 11 OR2 2 1 1 0 |add8bit:4|add1bit:7|S (|add8bit:4|add1bit:7|:6)
- - 8 - C 11 OR2 2 1 0 2 |add8bit:4|add1bit:7|CO (|add8bit:4|add1bit:7|:11)
- - 5 - A 16 OR2 2 1 1 0 |add8bit:4|add1bit:8|S (|add8bit:4|add1bit:8|:6)
- - 1 - A 16 OR2 2 1 0 2 |add8bit:4|add1bit:8|CO (|add8bit:4|add1bit:8|:11)
- - 6 - A 16 OR2 2 1 1 0 |add8bit:4|add1bit:9|S (|add8bit:4|add1bit:9|:6)
- - 2 - A 16 OR2 2 1 0 2 |add8bit:4|add1bit:9|CO (|add8bit:4|add1bit:9|:11)
- - 8 - A 16 OR2 2 1 1 0 |add8bit:4|add1bit:10|S (|add8bit:4|add1bit:10|:6)
- - 7 - A 16 OR2 2 1 0 2 |add8bit:4|add1bit:10|CO (|add8bit:4|add1bit:10|:11)
- - 4 - A 16 OR2 2 1 1 0 |add8bit:4|add1bit:11|S (|add8bit:4|add1bit:11|:6)
- - 3 - A 16 OR2 2 1 0 2 |add8bit:4|add1bit:11|CO (|add8bit:4|add1bit:11|:11)
- - 2 - C 20 OR2 2 1 1 0 |add8bit:4|add1bit:12|S (|add8bit:4|add1bit:12|:6)
- - 1 - C 20 OR2 2 1 0 2 |add8bit:4|add1bit:12|CO (|add8bit:4|add1bit:12|:11)
- - 3 - C 13 OR2 2 1 1 0 |add8bit:5|add1bit:5|S (|add8bit:5|add1bit:5|:6)
- - 4 - C 13 OR2 2 1 0 2 |add8bit:5|add1bit:5|CO (|add8bit:5|add1bit:5|:11)
- - 2 - C 13 OR2 2 1 1 0 |add8bit:5|add1bit:6|S (|add8bit:5|add1bit:6|:6)
- - 5 - C 13 OR2 2 1 0 2 |add8bit:5|add1bit:6|CO (|add8bit:5|add1bit:6|:11)
- - 7 - C 13 OR2 2 1 1 0 |add8bit:5|add1bit:7|S (|add8bit:5|add1bit:7|:6)
- - 1 - C 13 OR2 2 1 0 2 |add8bit:5|add1bit:7|CO (|add8bit:5|add1bit:7|:11)
- - 8 - C 13 OR2 2 1 1 0 |add8bit:5|add1bit:8|S (|add8bit:5|add1bit:8|:6)
- - 4 - C 10 OR2 2 1 0 2 |add8bit:5|add1bit:8|CO (|add8bit:5|add1bit:8|:11)
- - 5 - C 10 OR2 2 1 1 0 |add8bit:5|add1bit:9|S (|add8bit:5|add1bit:9|:6)
- - 6 - C 10 OR2 2 1 0 2 |add8bit:5|add1bit:9|CO (|add8bit:5|add1bit:9|:11)
- - 1 - C 10 OR2 2 1 1 0 |add8bit:5|add1bit:10|S (|add8bit:5|add1bit:10|:6)
- - 7 - C 10 OR2 2 1 0 2 |add8bit:5|add1bit:10|CO (|add8bit:5|add1bit:10|:11)
- - 3 - C 10 OR2 2 1 1 0 |add8bit:5|add1bit:11|S (|add8bit:5|add1bit:11|:6)
- - 2 - C 10 OR2 2 1 0 2 |add8bit:5|add1bit:11|CO (|add8bit:5|add1bit:11|:11)
- - 1 - B 08 OR2 2 1 1 0 |add8bit:5|add1bit:12|S (|add8bit:5|add1bit:12|:6)
- - 4 - B 08 OR2 2 1 0 2 |add8bit:5|add1bit:12|CO (|add8bit:5|add1bit:12|:11)
- - 3 - B 08 OR2 2 1 1 0 |add8bit:6|add1bit:5|S (|add8bit:6|add1bit:5|:6)
- - 5 - B 08 OR2 2 1 0 2 |add8bit:6|add1bit:5|CO (|add8bit:6|add1bit:5|:11)
- - 6 - B 08 OR2 2 1 1 0 |add8bit:6|add1bit:6|S (|add8bit:6|add1bit:6|:6)
- - 7 - B 08 OR2 2 1 0 2 |add8bit:6|add1bit:6|CO (|add8bit:6|add1bit:6|:11)
- - 8 - B 08 OR2 2 1 1 0 |add8bit:6|add1bit:7|S (|add8bit:6|add1bit:7|:6)
- - 2 - B 08 OR2 2 1 0 2 |add8bit:6|add1bit:7|CO (|add8bit:6|add1bit:7|:11)
- - 5 - B 07 OR2 2 1 1 0 |add8bit:6|add1bit:8|S (|add8bit:6|add1bit:8|:6)
- - 2 - B 07 OR2 2 1 0 2 |add8bit:6|add1bit:8|CO (|add8bit:6|add1bit:8|:11)
- - 6 - B 07 OR2 2 1 1 0 |add8bit:6|add1bit:9|S (|add8bit:6|add1bit:9|:6)
- - 3 - B 07 OR2 2 1 0 2 |add8bit:6|add1bit:9|CO (|add8bit:6|add1bit:9|:11)
- - 1 - B 07 OR2 2 1 1 0 |add8bit:6|add1bit:10|S (|add8bit:6|add1bit:10|:6)
- - 4 - B 07 OR2 2 1 0 2 |add8bit:6|add1bit:10|CO (|add8bit:6|add1bit:10|:11)
- - 7 - B 07 OR2 2 1 1 0 |add8bit:6|add1bit:11|S (|add8bit:6|add1bit:11|:6)
- - 8 - B 07 OR2 2 1 0 2 |add8bit:6|add1bit:11|CO (|add8bit:6|add1bit:11|:11)
- - 5 - A 05 OR2 2 1 1 0 |add8bit:6|add1bit:12|S (|add8bit:6|add1bit:12|:6)
- - 3 - A 05 OR2 2 1 0 2 |add8bit:6|add1bit:12|CO (|add8bit:6|add1bit:12|:11)
- - 8 - A 05 OR2 2 1 1 0 |add8bit:7|add1bit:5|S (|add8bit:7|add1bit:5|:6)
- - 4 - A 05 OR2 2 1 0 2 |add8bit:7|add1bit:5|CO (|add8bit:7|add1bit:5|:11)
- - 6 - A 05 OR2 2 1 1 0 |add8bit:7|add1bit:6|S (|add8bit:7|add1bit:6|:6)
- - 7 - A 05 OR2 2 1 0 2 |add8bit:7|add1bit:6|CO (|add8bit:7|add1bit:6|:11)
- - 1 - A 05 OR2 2 1 1 0 |add8bit:7|add1bit:7|S (|add8bit:7|add1bit:7|:6)
- - 2 - A 05 OR2 2 1 0 2 |add8bit:7|add1bit:7|CO (|add8bit:7|add1bit:7|:11)
- - 1 - A 24 OR2 2 1 1 0 |add8bit:7|add1bit:8|S (|add8bit:7|add1bit:8|:6)
- - 4 - A 24 OR2 2 1 0 2 |add8bit:7|add1bit:8|CO (|add8bit:7|add1bit:8|:11)
- - 3 - A 24 OR2 2 1 1 0 |add8bit:7|add1bit:9|S (|add8bit:7|add1bit:9|:6)
- - 5 - A 24 OR2 2 1 0 2 |add8bit:7|add1bit:9|CO (|add8bit:7|add1bit:9|:11)
- - 8 - A 24 OR2 2 1 1 0 |add8bit:7|add1bit:10|S (|add8bit:7|add1bit:10|:6)
- - 7 - A 24 OR2 2 1 0 2 |add8bit:7|add1bit:10|CO (|add8bit:7|add1bit:10|:11)
- - 6 - A 24 OR2 2 1 1 0 |add8bit:7|add1bit:11|S (|add8bit:7|add1bit:11|:6)
- - 2 - A 24 OR2 2 1 0 1 |add8bit:7|add1bit:11|CO (|add8bit:7|add1bit:11|:11)
- - 1 - A 22 OR2 2 1 1 0 |add8bit:7|add1bit:12|S (|add8bit:7|add1bit:12|:6)
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- p = Packed register
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** FASTTRACK INTERCONNECT UTILIZATION **
- Row FastTrack Interconnect:
- Global Left Half- Right Half-
- FastTrack FastTrack FastTrack
- Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
- A: 13/ 96( 13%) 8/ 48( 16%) 17/ 48( 35%) 8/16( 50%) 8/16( 50%) 0/16( 0%)
- B: 8/ 96( 8%) 17/ 48( 35%) 0/ 48( 0%) 7/16( 43%) 7/16( 43%) 0/16( 0%)
- C: 12/ 96( 12%) 9/ 48( 18%) 8/ 48( 16%) 5/16( 31%) 9/16( 56%) 0/16( 0%)
- Column FastTrack Interconnect:
- FastTrack
- Column Interconnect Input Pins Output Pins Bidir Pins
- 01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 07: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 08: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 10: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 11: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 13: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 15: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 16: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 17: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 18: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
- 19: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
- 20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 22: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 23: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
- 24: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
- EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- Device-Specific Information:e:doucumentsprojectsmips_1080379086add32bit.rpt
- add32bit
- ** EQUATIONS **
- A0 : INPUT;
- A1 : INPUT;
- A2 : INPUT;
- A3 : INPUT;
- A4 : INPUT;
- A5 : INPUT;
- A6 : INPUT;
- A7 : INPUT;
- A8 : INPUT;
- A9 : INPUT;
- A10 : INPUT;
- A11 : INPUT;
- A12 : INPUT;
- A13 : INPUT;
- A14 : INPUT;
- A15 : INPUT;
- A16 : INPUT;
- A17 : INPUT;
- A18 : INPUT;
- A19 : INPUT;
- A20 : INPUT;
- A21 : INPUT;
- A22 : INPUT;
- A23 : INPUT;
- A24 : INPUT;
- A25 : INPUT;
- A26 : INPUT;
- A27 : INPUT;
- A28 : INPUT;
- A29 : INPUT;
- A30 : INPUT;
- A31 : INPUT;
- B0 : INPUT;
- B1 : INPUT;
- B2 : INPUT;
- B3 : INPUT;
- B4 : INPUT;
- B5 : INPUT;
- B6 : INPUT;
- B7 : INPUT;
- B8 : INPUT;
- B9 : INPUT;
- B10 : INPUT;
- B11 : INPUT;
- B12 : INPUT;
- B13 : INPUT;
- B14 : INPUT;
- B15 : INPUT;
- B16 : INPUT;
- B17 : INPUT;
- B18 : INPUT;
- B19 : INPUT;
- B20 : INPUT;
- B21 : INPUT;
- B22 : INPUT;
- B23 : INPUT;
- B24 : INPUT;
- B25 : INPUT;
- B26 : INPUT;
- B27 : INPUT;
- B28 : INPUT;
- B29 : INPUT;
- B30 : INPUT;
- B31 : INPUT;
- CI : INPUT;
- -- Node name is 'S0'
- -- Equation name is 'S0', type is output
- S0 = _LC2_C11;
- -- Node name is 'S1'
- -- Equation name is 'S1', type is output
- S1 = _LC3_C11;
- -- Node name is 'S2'
- -- Equation name is 'S2', type is output
- S2 = _LC1_C11;
- -- Node name is 'S3'
- -- Equation name is 'S3', type is output
- S3 = _LC5_A16;
- -- Node name is 'S4'
- -- Equation name is 'S4', type is output
- S4 = _LC6_A16;
- -- Node name is 'S5'
- -- Equation name is 'S5', type is output
- S5 = _LC8_A16;
- -- Node name is 'S6'
- -- Equation name is 'S6', type is output
- S6 = _LC4_A16;
- -- Node name is 'S7'
- -- Equation name is 'S7', type is output
- S7 = _LC2_C20;
- -- Node name is 'S8'
- -- Equation name is 'S8', type is output
- S8 = _LC3_C13;
- -- Node name is 'S9'
- -- Equation name is 'S9', type is output
- S9 = _LC2_C13;
- -- Node name is 'S10'
- -- Equation name is 'S10', type is output
- S10 = _LC7_C13;
- -- Node name is 'S11'
- -- Equation name is 'S11', type is output
- S11 = _LC8_C13;
- -- Node name is 'S12'
- -- Equation name is 'S12', type is output
- S12 = _LC5_C10;
- -- Node name is 'S13'
- -- Equation name is 'S13', type is output
- S13 = _LC1_C10;
- -- Node name is 'S14'
- -- Equation name is 'S14', type is output
- S14 = _LC3_C10;
- -- Node name is 'S15'
- -- Equation name is 'S15', type is output
- S15 = _LC1_B8;
- -- Node name is 'S16'
- -- Equation name is 'S16', type is output
- S16 = _LC3_B8;
- -- Node name is 'S17'
- -- Equation name is 'S17', type is output
- S17 = _LC6_B8;
- -- Node name is 'S18'
- -- Equation name is 'S18', type is output
- S18 = _LC8_B8;
- -- Node name is 'S19'
- -- Equation name is 'S19', type is output
- S19 = _LC5_B7;
- -- Node name is 'S20'
- -- Equation name is 'S20', type is output
- S20 = _LC6_B7;
- -- Node name is 'S21'
- -- Equation name is 'S21', type is output
- S21 = _LC1_B7;
- -- Node name is 'S22'
- -- Equation name is 'S22', type is output
- S22 = _LC7_B7;
- -- Node name is 'S23'
- -- Equation name is 'S23', type is output
- S23 = _LC5_A5;
- -- Node name is 'S24'
- -- Equation name is 'S24', type is output
- S24 = _LC8_A5;
- -- Node name is 'S25'
- -- Equation name is 'S25', type is output
- S25 = _LC6_A5;
- -- Node name is 'S26'
- -- Equation name is 'S26', type is output
- S26 = _LC1_A5;
- -- Node name is 'S27'
- -- Equation name is 'S27', type is output
- S27 = _LC1_A24;
- -- Node name is 'S28'
- -- Equation name is 'S28', type is output
- S28 = _LC3_A24;
- -- Node name is 'S29'
- -- Equation name is 'S29', type is output
- S29 = _LC8_A24;
- -- Node name is 'S30'
- -- Equation name is 'S30', type is output
- S30 = _LC6_A24;
- -- Node name is 'S31'
- -- Equation name is 'S31', type is output
- S31 = _LC1_A22;
- -- Node name is '|add8bit:4|add1bit:5|:11' = '|add8bit:4|add1bit:5|CO'
- -- Equation name is '_LC4_C11', type is buried
- _LC4_C11 = LCELL( _EQ001);
- _EQ001 = A0 & B0
- # B0 & CI
- # A0 & CI;
- -- Node name is '|add8bit:4|add1bit:5|:6' = '|add8bit:4|add1bit:5|S'
- -- Equation name is '_LC2_C11', type is buried
- _LC2_C11 = LCELL( _EQ002);
- _EQ002 = A0 & B0 & CI
- # !A0 & B0 & !CI
- # A0 & !B0 & !CI
- # !A0 & !B0 & CI;
- -- Node name is '|add8bit:4|add1bit:6|:11' = '|add8bit:4|add1bit:6|CO'
- -- Equation name is '_LC5_C11', type is buried
- _LC5_C11 = LCELL( _EQ003);
- _EQ003 = B1 & _LC4_C11
- # A1 & _LC4_C11
- # A1 & B1;
- -- Node name is '|add8bit:4|add1bit:6|:6' = '|add8bit:4|add1bit:6|S'
- -- Equation name is '_LC3_C11', type is buried
- _LC3_C11 = LCELL( _EQ004);
- _EQ004 = A1 & B1 & _LC4_C11
- # !A1 & !B1 & _LC4_C11
- # !A1 & B1 & !_LC4_C11
- # A1 & !B1 & !_LC4_C11;
- -- Node name is '|add8bit:4|add1bit:7|:11' = '|add8bit:4|add1bit:7|CO'
- -- Equation name is '_LC8_C11', type is buried
- _LC8_C11 = LCELL( _EQ005);
- _EQ005 = A2 & _LC5_C11
- # B2 & _LC5_C11
- # A2 & B2;
- -- Node name is '|add8bit:4|add1bit:7|:6' = '|add8bit:4|add1bit:7|S'
- -- Equation name is '_LC1_C11', type is buried
- _LC1_C11 = LCELL( _EQ006);
- _EQ006 = A2 & B2 & _LC5_C11
- # !A2 & !B2 & _LC5_C11
- # A2 & !B2 & !_LC5_C11
- # !A2 & B2 & !_LC5_C11;
- -- Node name is '|add8bit:4|add1bit:8|:11' = '|add8bit:4|add1bit:8|CO'
- -- Equation name is '_LC1_A16', type is buried
- _LC1_A16 = LCELL( _EQ007);
- _EQ007 = A3 & _LC8_C11
- # B3 & _LC8_C11
- # A3 & B3;
- -- Node name is '|add8bit:4|add1bit:8|:6' = '|add8bit:4|add1bit:8|S'
- -- Equation name is '_LC5_A16', type is buried
- _LC5_A16 = LCELL( _EQ008);
- _EQ008 = A3 & B3 & _LC8_C11
- # !A3 & !B3 & _LC8_C11
- # A3 & !B3 & !_LC8_C11
- # !A3 & B3 & !_LC8_C11;
- -- Node name is '|add8bit:4|add1bit:9|:11' = '|add8bit:4|add1bit:9|CO'
- -- Equation name is '_LC2_A16', type is buried
- _LC2_A16 = LCELL( _EQ009);
- _EQ009 = A4 & _LC1_A16
- # B4 & _LC1_A16
- # A4 & B4;
- -- Node name is '|add8bit:4|add1bit:9|:6' = '|add8bit:4|add1bit:9|S'
- -- Equation name is '_LC6_A16', type is buried
- _LC6_A16 = LCELL( _EQ010);
- _EQ010 = A4 & B4 & _LC1_A16
- # !A4 & !B4 & _LC1_A16
- # A4 & !B4 & !_LC1_A16
- # !A4 & B4 & !_LC1_A16;
- -- Node name is '|add8bit:4|add1bit:10|:11' = '|add8bit:4|add1bit:10|CO'
- -- Equation name is '_LC7_A16', type is buried
- _LC7_A16 = LCELL( _EQ011);
- _EQ011 = A5 & _LC2_A16
- # B5 & _LC2_A16
- # A5 & B5;
- -- Node name is '|add8bit:4|add1bit:10|:6' = '|add8bit:4|add1bit:10|S'
- -- Equation name is '_LC8_A16', type is buried
- _LC8_A16 = LCELL( _EQ012);
- _EQ012 = A5 & B5 & _LC2_A16
- # !A5 & !B5 & _LC2_A16
- # A5 & !B5 & !_LC2_A16
- # !A5 & B5 & !_LC2_A16;
- -- Node name is '|add8bit:4|add1bit:11|:11' = '|add8bit:4|add1bit:11|CO'
- -- Equation name is '_LC3_A16', type is buried
- _LC3_A16 = LCELL( _EQ013);
- _EQ013 = A6 & _LC7_A16
- # B6 & _LC7_A16
- # A6 & B6;
- -- Node name is '|add8bit:4|add1bit:11|:6' = '|add8bit:4|add1bit:11|S'
- -- Equation name is '_LC4_A16', type is buried
- _LC4_A16 = LCELL( _EQ014);
- _EQ014 = A6 & B6 & _LC7_A16
- # !A6 & !B6 & _LC7_A16
- # A6 & !B6 & !_LC7_A16
- # !A6 & B6 & !_LC7_A16;
- -- Node name is '|add8bit:4|add1bit:12|:11' = '|add8bit:4|add1bit:12|CO'
- -- Equation name is '_LC1_C20', type is buried
- _LC1_C20 = LCELL( _EQ015);
- _EQ015 = A7 & _LC3_A16
- # B7 & _LC3_A16
- # A7 & B7;
- -- Node name is '|add8bit:4|add1bit:12|:6' = '|add8bit:4|add1bit:12|S'
- -- Equation name is '_LC2_C20', type is buried
- _LC2_C20 = LCELL( _EQ016);
- _EQ016 = A7 & B7 & _LC3_A16
- # !A7 & !B7 & _LC3_A16
- # A7 & !B7 & !_LC3_A16
- # !A7 & B7 & !_LC3_A16;
- -- Node name is '|add8bit:5|add1bit:5|:11' = '|add8bit:5|add1bit:5|CO'
- -- Equation name is '_LC4_C13', type is buried
- _LC4_C13 = LCELL( _EQ017);
- _EQ017 = A8 & _LC1_C20
- # B8 & _LC1_C20
- # A8 & B8;
- -- Node name is '|add8bit:5|add1bit:5|:6' = '|add8bit:5|add1bit:5|S'
- -- Equation name is '_LC3_C13', type is buried
- _LC3_C13 = LCELL( _EQ018);
- _EQ018 = A8 & B8 & _LC1_C20
- # !A8 & !B8 & _LC1_C20
- # A8 & !B8 & !_LC1_C20
- # !A8 & B8 & !_LC1_C20;
- -- Node name is '|add8bit:5|add1bit:6|:11' = '|add8bit:5|add1bit:6|CO'
- -- Equation name is '_LC5_C13', type is buried
- _LC5_C13 = LCELL( _EQ019);
- _EQ019 = A9 & _LC4_C13
- # B9 & _LC4_C13
- # A9 & B9;
- -- Node name is '|add8bit:5|add1bit:6|:6' = '|add8bit:5|add1bit:6|S'
- -- Equation name is '_LC2_C13', type is buried
- _LC2_C13 = LCELL( _EQ020);
- _EQ020 = A9 & B9 & _LC4_C13
- # !A9 & !B9 & _LC4_C13
- # A9 & !B9 & !_LC4_C13
- # !A9 & B9 & !_LC4_C13;
- -- Node name is '|add8bit:5|add1bit:7|:11' = '|add8bit:5|add1bit:7|CO'
- -- Equation name is '_LC1_C13', type is buried
- _LC1_C13 = LCELL( _EQ021);
- _EQ021 = A10 & _LC5_C13
- # B10 & _LC5_C13
- # A10 & B10;
- -- Node name is '|add8bit:5|add1bit:7|:6' = '|add8bit:5|add1bit:7|S'
- -- Equation name is '_LC7_C13', type is buried
- _LC7_C13 = LCELL( _EQ022);
- _EQ022 = A10 & B10 & _LC5_C13
- # !A10 & !B10 & _LC5_C13
- # A10 & !B10 & !_LC5_C13
- # !A10 & B10 & !_LC5_C13;
- -- Node name is '|add8bit:5|add1bit:8|:11' = '|add8bit:5|add1bit:8|CO'
- -- Equation name is '_LC4_C10', type is buried
- _LC4_C10 = LCELL( _EQ023);
- _EQ023 = A11 & _LC1_C13
- # B11 & _LC1_C13
- # A11 & B11;
- -- Node name is '|add8bit:5|add1bit:8|:6' = '|add8bit:5|add1bit:8|S'
- -- Equation name is '_LC8_C13', type is buried
- _LC8_C13 = LCELL( _EQ024);
- _EQ024 = A11 & B11 & _LC1_C13
- # !A11 & !B11 & _LC1_C13
- # A11 & !B11 & !_LC1_C13
- # !A11 & B11 & !_LC1_C13;
- -- Node name is '|add8bit:5|add1bit:9|:11' = '|add8bit:5|add1bit:9|CO'
- -- Equation name is '_LC6_C10', type is buried
- _LC6_C10 = LCELL( _EQ025);
- _EQ025 = A12 & _LC4_C10
- # B12 & _LC4_C10
- # A12 & B12;
- -- Node name is '|add8bit:5|add1bit:9|:6' = '|add8bit:5|add1bit:9|S'
- -- Equation name is '_LC5_C10', type is buried
- _LC5_C10 = LCELL( _EQ026);
- _EQ026 = A12 & B12 & _LC4_C10
- # !A12 & !B12 & _LC4_C10
- # A12 & !B12 & !_LC4_C10
- # !A12 & B12 & !_LC4_C10;
- -- Node name is '|add8bit:5|add1bit:10|:11' = '|add8bit:5|add1bit:10|CO'
- -- Equation name is '_LC7_C10', type is buried
- _LC7_C10 = LCELL( _EQ027);
- _EQ027 = A13 & _LC6_C10
- # B13 & _LC6_C10
- # A13 & B13;
- -- Node name is '|add8bit:5|add1bit:10|:6' = '|add8bit:5|add1bit:10|S'
- -- Equation name is '_LC1_C10', type is buried
- _LC1_C10 = LCELL( _EQ028);
- _EQ028 = A13 & B13 & _LC6_C10
- # !A13 & !B13 & _LC6_C10
- # A13 & !B13 & !_LC6_C10
- # !A13 & B13 & !_LC6_C10;
- -- Node name is '|add8bit:5|add1bit:11|:11' = '|add8bit:5|add1bit:11|CO'
- -- Equation name is '_LC2_C10', type is buried
- _LC2_C10 = LCELL( _EQ029);
- _EQ029 = A14 & _LC7_C10
- # B14 & _LC7_C10
- # A14 & B14;
- -- Node name is '|add8bit:5|add1bit:11|:6' = '|add8bit:5|add1bit:11|S'
- -- Equation name is '_LC3_C10', type is buried
- _LC3_C10 = LCELL( _EQ030);
- _EQ030 = A14 & B14 & _LC7_C10
- # !A14 & !B14 & _LC7_C10
- # A14 & !B14 & !_LC7_C10
- # !A14 & B14 & !_LC7_C10;
- -- Node name is '|add8bit:5|add1bit:12|:11' = '|add8bit:5|add1bit:12|CO'
- -- Equation name is '_LC4_B8', type is buried
- _LC4_B8 = LCELL( _EQ031);
- _EQ031 = A15 & _LC2_C10
- # B15 & _LC2_C10
- # A15 & B15;
- -- Node name is '|add8bit:5|add1bit:12|:6' = '|add8bit:5|add1bit:12|S'
- -- Equation name is '_LC1_B8', type is buried
- _LC1_B8 = LCELL( _EQ032);
- _EQ032 = A15 & B15 & _LC2_C10
- # !A15 & !B15 & _LC2_C10
- # A15 & !B15 & !_LC2_C10
- # !A15 & B15 & !_LC2_C10;
- -- Node name is '|add8bit:6|add1bit:5|:11' = '|add8bit:6|add1bit:5|CO'
- -- Equation name is '_LC5_B8', type is buried
- _LC5_B8 = LCELL( _EQ033);
- _EQ033 = A16 & _LC4_B8
- # B16 & _LC4_B8
- # A16 & B16;
- -- Node name is '|add8bit:6|add1bit:5|:6' = '|add8bit:6|add1bit:5|S'
- -- Equation name is '_LC3_B8', type is buried
- _LC3_B8 = LCELL( _EQ034);
- _EQ034 = A16 & B16 & _LC4_B8
- # !A16 & !B16 & _LC4_B8
- # A16 & !B16 & !_LC4_B8
- # !A16 & B16 & !_LC4_B8;
- -- Node name is '|add8bit:6|add1bit:6|:11' = '|add8bit:6|add1bit:6|CO'
- -- Equation name is '_LC7_B8', type is buried
- _LC7_B8 = LCELL( _EQ035);
- _EQ035 = A17 & _LC5_B8
- # B17 & _LC5_B8
- # A17 & B17;
- -- Node name is '|add8bit:6|add1bit:6|:6' = '|add8bit:6|add1bit:6|S'
- -- Equation name is '_LC6_B8', type is buried
- _LC6_B8 = LCELL( _EQ036);
- _EQ036 = A17 & B17 & _LC5_B8
- # !A17 & !B17 & _LC5_B8
- # A17 & !B17 & !_LC5_B8
- # !A17 & B17 & !_LC5_B8;
- -- Node name is '|add8bit:6|add1bit:7|:11' = '|add8bit:6|add1bit:7|CO'
- -- Equation name is '_LC2_B8', type is buried
- _LC2_B8 = LCELL( _EQ037);
- _EQ037 = A18 & _LC7_B8
- # B18 & _LC7_B8
- # A18 & B18;
- -- Node name is '|add8bit:6|add1bit:7|:6' = '|add8bit:6|add1bit:7|S'
- -- Equation name is '_LC8_B8', type is buried
- _LC8_B8 = LCELL( _EQ038);
- _EQ038 = A18 & B18 & _LC7_B8
- # !A18 & !B18 & _LC7_B8
- # A18 & !B18 & !_LC7_B8
- # !A18 & B18 & !_LC7_B8;
- -- Node name is '|add8bit:6|add1bit:8|:11' = '|add8bit:6|add1bit:8|CO'
- -- Equation name is '_LC2_B7', type is buried
- _LC2_B7 = LCELL( _EQ039);
- _EQ039 = A19 & _LC2_B8
- # B19 & _LC2_B8
- # A19 & B19;
- -- Node name is '|add8bit:6|add1bit:8|:6' = '|add8bit:6|add1bit:8|S'
- -- Equation name is '_LC5_B7', type is buried
- _LC5_B7 = LCELL( _EQ040);
- _EQ040 = A19 & B19 & _LC2_B8
- # !A19 & !B19 & _LC2_B8
- # A19 & !B19 & !_LC2_B8
- # !A19 & B19 & !_LC2_B8;
- -- Node name is '|add8bit:6|add1bit:9|:11' = '|add8bit:6|add1bit:9|CO'
- -- Equation name is '_LC3_B7', type is buried
- _LC3_B7 = LCELL( _EQ041);
- _EQ041 = A20 & _LC2_B7
- # B20 & _LC2_B7
- # A20 & B20;
- -- Node name is '|add8bit:6|add1bit:9|:6' = '|add8bit:6|add1bit:9|S'
- -- Equation name is '_LC6_B7', type is buried
- _LC6_B7 = LCELL( _EQ042);
- _EQ042 = A20 & B20 & _LC2_B7
- # !A20 & !B20 & _LC2_B7
- # A20 & !B20 & !_LC2_B7
- # !A20 & B20 & !_LC2_B7;
- -- Node name is '|add8bit:6|add1bit:10|:11' = '|add8bit:6|add1bit:10|CO'
- -- Equation name is '_LC4_B7', type is buried
- _LC4_B7 = LCELL( _EQ043);
- _EQ043 = A21 & _LC3_B7
- # B21 & _LC3_B7
- # A21 & B21;
- -- Node name is '|add8bit:6|add1bit:10|:6' = '|add8bit:6|add1bit:10|S'
- -- Equation name is '_LC1_B7', type is buried
- _LC1_B7 = LCELL( _EQ044);
- _EQ044 = A21 & B21 & _LC3_B7
- # !A21 & !B21 & _LC3_B7
- # A21 & !B21 & !_LC3_B7
- # !A21 & B21 & !_LC3_B7;
- -- Node name is '|add8bit:6|add1bit:11|:11' = '|add8bit:6|add1bit:11|CO'
- -- Equation name is '_LC8_B7', type is buried
- _LC8_B7 = LCELL( _EQ045);
- _EQ045 = A22 & _LC4_B7
- # B22 & _LC4_B7
- # A22 & B22;
- -- Node name is '|add8bit:6|add1bit:11|:6' = '|add8bit:6|add1bit:11|S'
- -- Equation name is '_LC7_B7', type is buried
- _LC7_B7 = LCELL( _EQ046);
- _EQ046 = A22 & B22 & _LC4_B7
- # !A22 & !B22 & _LC4_B7
- # A22 & !B22 & !_LC4_B7
- # !A22 & B22 & !_LC4_B7;
- -- Node name is '|add8bit:6|add1bit:12|:11' = '|add8bit:6|add1bit:12|CO'
- -- Equation name is '_LC3_A5', type is buried
- _LC3_A5 = LCELL( _EQ047);
- _EQ047 = A23 & _LC8_B7
- # B23 & _LC8_B7
- # A23 & B23;
- -- Node name is '|add8bit:6|add1bit:12|:6' = '|add8bit:6|add1bit:12|S'
- -- Equation name is '_LC5_A5', type is buried
- _LC5_A5 = LCELL( _EQ048);
- _EQ048 = A23 & B23 & _LC8_B7
- # !A23 & !B23 & _LC8_B7
- # A23 & !B23 & !_LC8_B7
- # !A23 & B23 & !_LC8_B7;
- -- Node name is '|add8bit:7|add1bit:5|:11' = '|add8bit:7|add1bit:5|CO'
- -- Equation name is '_LC4_A5', type is buried
- _LC4_A5 = LCELL( _EQ049);
- _EQ049 = A24 & _LC3_A5
- # B24 & _LC3_A5
- # A24 & B24;
- -- Node name is '|add8bit:7|add1bit:5|:6' = '|add8bit:7|add1bit:5|S'
- -- Equation name is '_LC8_A5', type is buried
- _LC8_A5 = LCELL( _EQ050);
- _EQ050 = A24 & B24 & _LC3_A5
- # !A24 & !B24 & _LC3_A5
- # A24 & !B24 & !_LC3_A5
- # !A24 & B24 & !_LC3_A5;
- -- Node name is '|add8bit:7|add1bit:6|:11' = '|add8bit:7|add1bit:6|CO'
- -- Equation name is '_LC7_A5', type is buried
- _LC7_A5 = LCELL( _EQ051);
- _EQ051 = A25 & _LC4_A5
- # B25 & _LC4_A5
- # A25 & B25;
- -- Node name is '|add8bit:7|add1bit:6|:6' = '|add8bit:7|add1bit:6|S'
- -- Equation name is '_LC6_A5', type is buried
- _LC6_A5 = LCELL( _EQ052);
- _EQ052 = A25 & B25 & _LC4_A5
- # !A25 & !B25 & _LC4_A5
- # A25 & !B25 & !_LC4_A5
- # !A25 & B25 & !_LC4_A5;
- -- Node name is '|add8bit:7|add1bit:7|:11' = '|add8bit:7|add1bit:7|CO'
- -- Equation name is '_LC2_A5', type is buried
- _LC2_A5 = LCELL( _EQ053);
- _EQ053 = A26 & _LC7_A5
- # B26 & _LC7_A5
- # A26 & B26;
- -- Node name is '|add8bit:7|add1bit:7|:6' = '|add8bit:7|add1bit:7|S'
- -- Equation name is '_LC1_A5', type is buried
- _LC1_A5 = LCELL( _EQ054);
- _EQ054 = A26 & B26 & _LC7_A5
- # !A26 & !B26 & _LC7_A5
- # A26 & !B26 & !_LC7_A5
- # !A26 & B26 & !_LC7_A5;
- -- Node name is '|add8bit:7|add1bit:8|:11' = '|add8bit:7|add1bit:8|CO'
- -- Equation name is '_LC4_A24', type is buried
- _LC4_A24 = LCELL( _EQ055);
- _EQ055 = A27 & _LC2_A5
- # B27 & _LC2_A5
- # A27 & B27;
- -- Node name is '|add8bit:7|add1bit:8|:6' = '|add8bit:7|add1bit:8|S'
- -- Equation name is '_LC1_A24', type is buried
- _LC1_A24 = LCELL( _EQ056);
- _EQ056 = A27 & B27 & _LC2_A5
- # !A27 & !B27 & _LC2_A5
- # A27 & !B27 & !_LC2_A5
- # !A27 & B27 & !_LC2_A5;
- -- Node name is '|add8bit:7|add1bit:9|:11' = '|add8bit:7|add1bit:9|CO'
- -- Equation name is '_LC5_A24', type is buried
- _LC5_A24 = LCELL( _EQ057);
- _EQ057 = A28 & _LC4_A24
- # B28 & _LC4_A24
- # A28 & B28;
- -- Node name is '|add8bit:7|add1bit:9|:6' = '|add8bit:7|add1bit:9|S'
- -- Equation name is '_LC3_A24', type is buried
- _LC3_A24 = LCELL( _EQ058);
- _EQ058 = A28 & B28 & _LC4_A24
- # !A28 & !B28 & _LC4_A24
- # A28 & !B28 & !_LC4_A24
- # !A28 & B28 & !_LC4_A24;
- -- Node name is '|add8bit:7|add1bit:10|:11' = '|add8bit:7|add1bit:10|CO'
- -- Equation name is '_LC7_A24', type is buried
- _LC7_A24 = LCELL( _EQ059);
- _EQ059 = A29 & _LC5_A24
- # B29 & _LC5_A24
- # A29 & B29;
- -- Node name is '|add8bit:7|add1bit:10|:6' = '|add8bit:7|add1bit:10|S'
- -- Equation name is '_LC8_A24', type is buried
- _LC8_A24 = LCELL( _EQ060);
- _EQ060 = A29 & B29 & _LC5_A24
- # !A29 & !B29 & _LC5_A24
- # A29 & !B29 & !_LC5_A24
- # !A29 & B29 & !_LC5_A24;
- -- Node name is '|add8bit:7|add1bit:11|:11' = '|add8bit:7|add1bit:11|CO'
- -- Equation name is '_LC2_A24', type is buried
- _LC2_A24 = LCELL( _EQ061);
- _EQ061 = A30 & _LC7_A24
- # B30 & _LC7_A24
- # A30 & B30;
- -- Node name is '|add8bit:7|add1bit:11|:6' = '|add8bit:7|add1bit:11|S'
- -- Equation name is '_LC6_A24', type is buried
- _LC6_A24 = LCELL( _EQ062);
- _EQ062 = A30 & B30 & _LC7_A24
- # !A30 & !B30 & _LC7_A24
- # A30 & !B30 & !_LC7_A24
- # !A30 & B30 & !_LC7_A24;
- -- Node name is '|add8bit:7|add1bit:12|:6' = '|add8bit:7|add1bit:12|S'
- -- Equation name is '_LC1_A22', type is buried
- _LC1_A22 = LCELL( _EQ063);
- _EQ063 = A31 & B31 & _LC2_A24
- # !A31 & !B31 & _LC2_A24
- # A31 & !B31 & !_LC2_A24
- # !A31 & B31 & !_LC2_A24;
- Project Information e:doucumentsprojectsmips_1080379086add32bit.rpt
- ** COMPILATION SETTINGS & TIMES **
- Processing Menu Commands
- ------------------------
- Design Doctor = off
- Logic Synthesis:
- Synthesis Type Used = Multi-Level
- Default Synthesis Style = NORMAL
- Logic option settings in 'NORMAL' style for 'FLEX10K' family
- CARRY_CHAIN = ignore
- CARRY_CHAIN_LENGTH = 32
- CASCADE_CHAIN = ignore
- CASCADE_CHAIN_LENGTH = 2
- DECOMPOSE_GATES = on
- DUPLICATE_LOGIC_EXTRACTION = on
- MINIMIZATION = full
- MULTI_LEVEL_FACTORING = on
- NOT_GATE_PUSH_BACK = on
- REDUCE_LOGIC = on
- REFACTORIZATION = on
- REGISTER_OPTIMIZATION = on
- RESYNTHESIZE_NETWORK = on
- SLOW_SLEW_RATE = off
- SUBFACTOR_EXTRACTION = on
- IGNORE_SOFT_BUFFERS = on
- USE_LPM_FOR_AHDL_OPERATORS = off
- Other logic synthesis settings:
- Automatic Global Clock = on
- Automatic Global Clear = on
- Automatic Global Preset = on
- Automatic Global Output Enable = on
- Automatic Fast I/O = off
- Automatic Register Packing = off
- Automatic Open-Drain Pins = on
- Automatic Implement in EAB = off
- Optimize = 5
- Default Timing Specifications: None
- Cut All Bidir Feedback Timing Paths = on
- Cut All Clear & Preset Timing Paths = on
- Ignore Timing Assignments = on
- Functional SNF Extractor = off
- Linked SNF Extractor = off
- Timing SNF Extractor = on
- Optimize Timing SNF = off
- Generate AHDL TDO File = off
- Fitter Settings = NORMAL
- Use Quartus Fitter = on
- Smart Recompile = off
- Total Recompile = off
- Interfaces Menu Commands
- ------------------------
- EDIF Netlist Writer = off
- Verilog Netlist Writer = off
- VHDL Netlist Writer = off
- Compilation Times
- -----------------
- Compiler Netlist Extractor 00:00:00
- Database Builder 00:00:00
- Logic Synthesizer 00:00:00
- Partitioner 00:00:00
- Fitter 00:00:01
- Timing SNF Extractor 00:00:00
- Assembler 00:00:00
- -------------------------- --------
- Total Time 00:00:01
- Memory Allocated
- -----------------
- Peak memory allocated during compilation = 12,168K
