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equ.acf
资源名称：mips.rar　[点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：15k
源码类别：

VHDL/FPGA/Verilog

开发平台：

VHDL

equ.acf：源码内容
  1. --
  2. --  Copyright (C) 1988-2000 Altera Corporation
  3. --  Any megafunction design, and related net list (encrypted or decrypted),
  4. --  support information, device programming or simulation file, and any other
  5. --  associated documentation or information provided by Altera or a partner
  6. --  under Altera's Megafunction Partnership Program may be used only to
  7. --  program PLD devices (but not masked PLD devices) from Altera.  Any other
  8. --  use of such megafunction design, net list, support information, device
  9. --  programming or simulation file, or any other related documentation or
  10. --  information is prohibited for any other purpose, including, but not
  11. --  limited to modification, reverse engineering, de-compiling, or use with
  12. --  any other silicon devices, unless such use is explicitly licensed under
  13. --  a separate agreement with Altera or a megafunction partner.  Title to
  14. --  the intellectual property, including patents, copyrights, trademarks,
  15. --  trade secrets, or maskworks, embodied in any such megafunction design,
  16. --  net list, support information, device programming or simulation file, or
  17. --  any other related documentation or information provided by Altera or a
  18. --  megafunction partner, remains with Altera, the megafunction partner, or
  19. --  their respective licensors.  No other licenses, including any licenses
  20. --  needed under any third party's intellectual property, are provided herein.
  21. --
  22. DEFAULT_DEVICES
  23. BEGIN
  24. AUTO_DEVICE = EPF10K70RC240-2;
  25. AUTO_DEVICE = EPF10K50BC356-3;
  26. AUTO_DEVICE = EPF10K50RC240-3;
  27. AUTO_DEVICE = EPF10K40RC240-3;
  28. AUTO_DEVICE = EPF10K40RC208-3;
  29. AUTO_DEVICE = EPF10K30BC356-3;
  30. AUTO_DEVICE = EPF10K30RC240-3;
  31. AUTO_DEVICE = EPF10K30RC208-3;
  32. AUTO_DEVICE = EPF10K20RC240-3;
  33. AUTO_DEVICE = EPF10K20RC208-3;
  34. AUTO_DEVICE = EPF10K20TC144-3;
  35. AUTO_DEVICE = EPF10K10QC208-3;
  36. AUTO_DEVICE = EPF10K10TC144-3;
  37. AUTO_DEVICE = EPF10K10LC84-3;
  38. ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
  39. END;
  41. TIMING_POINT
  42. BEGIN
  43. DEVICE_FOR_TIMING_SYNTHESIS = FLEX10K;
  44. MAINTAIN_STABLE_SYNTHESIS = OFF;
  45. CUT_ALL_CLEAR_PRESET = ON;
  46. CUT_ALL_BIDIR = ON;
  47. END;
  49. IGNORED_ASSIGNMENTS
  50. BEGIN
  51. FIT_IGNORE_TIMING = ON;
  52. DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
  53. IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
  54. IGNORE_DEVICE_ASSIGNMENTS = OFF;
  55. IGNORE_LC_ASSIGNMENTS = OFF;
  56. IGNORE_PIN_ASSIGNMENTS = OFF;
  57. IGNORE_CHIP_ASSIGNMENTS = OFF;
  58. IGNORE_TIMING_ASSIGNMENTS = OFF;
  59. IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
  60. IGNORE_CLIQUE_ASSIGNMENTS = OFF;
  61. END;
  63. GLOBAL_PROJECT_DEVICE_OPTIONS
  64. BEGIN
  65. MAX7000B_ENABLE_VREFB = OFF;
  66. MAX7000B_ENABLE_VREFA = OFF;
  67. MAX7000B_VCCIO_IOBANK2 = 3.3V;
  68. MAX7000B_VCCIO_IOBANK1 = 3.3V;
  69. CONFIG_EPROM_PULLUP_RESISTOR = ON;
  70. CONFIG_EPROM_USER_CODE = FFFFFFFF;
  71. FLEX_CONFIGURATION_EPROM = AUTO;
  72. MAX7000AE_ENABLE_JTAG = ON;
  73. MAX7000AE_USER_CODE = FFFFFFFF;
  74. FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  75. FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
  76. FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
  77. FLEX6000_ENABLE_JTAG = OFF;
  78. CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
  79. MULTIVOLT_IO = OFF;
  80. MAX7000S_ENABLE_JTAG = ON;
  81. FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
  82. MAX7000S_USER_CODE = FFFF;
  83. CONFIG_SCHEME_10K = PASSIVE_SERIAL;
  84. FLEX10K_JTAG_USER_CODE = 7F;
  85. ENABLE_INIT_DONE_OUTPUT = OFF;
  86. ENABLE_CHIP_WIDE_OE = OFF;
  87. ENABLE_CHIP_WIDE_RESET = OFF;
  88. nCEO = UNRESERVED;
  89. CLKUSR = UNRESERVED;
  90. ADD17 = UNRESERVED;
  91. ADD16 = UNRESERVED;
  92. ADD15 = UNRESERVED;
  93. ADD14 = UNRESERVED;
  94. ADD13 = UNRESERVED;
  95. ADD0_TO_ADD12 = UNRESERVED;
  96. SDOUT = RESERVED_DRIVES_OUT;
  97. RDCLK = UNRESERVED;
  98. RDYnBUSY = UNRESERVED;
  99. nWS_nRS_nCS_CS = UNRESERVED;
  100. DATA1_TO_DATA7 = UNRESERVED;
  101. DATA0 = RESERVED_TRI_STATED;
  102. FLEX8000_ENABLE_JTAG = OFF;
  103. CONFIG_SCHEME = ACTIVE_SERIAL;
  104. DISABLE_TIME_OUT = OFF;
  105. ENABLE_DCLK_OUTPUT = OFF;
  106. RELEASE_CLEARS = OFF;
  107. AUTO_RESTART = OFF;
  108. USER_CLOCK = OFF;
  109. SECURITY_BIT = OFF;
  110. RESERVED_PINS_PERCENT = 0;
  111. RESERVED_LCELLS_PERCENT = 0;
  112. END;
  114. GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
  115. BEGIN
  116. MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
  117. AUTO_IMPLEMENT_IN_EAB = OFF;
  118. AUTO_OPEN_DRAIN_PINS = ON;
  119. ONE_HOT_STATE_MACHINE_ENCODING = OFF;
  120. AUTO_REGISTER_PACKING = OFF;
  121. DEVICE_FAMILY = FLEX10K;
  122. STYLE = NORMAL;
  123. AUTO_FAST_IO = OFF;
  124. AUTO_GLOBAL_OE = ON;
  125. AUTO_GLOBAL_PRESET = ON;
  126. AUTO_GLOBAL_CLEAR = ON;
  127. AUTO_GLOBAL_CLOCK = ON;
  128. MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
  129. OPTIMIZE_FOR_SPEED = 5;
  130. END;
  132. COMPILER_PROCESSING_CONFIGURATION
  133. BEGIN
  134. PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
  135. FITTER_SETTINGS = NORMAL;
  136. SMART_RECOMPILE = OFF;
  137. GENERATE_AHDL_TDO_FILE = OFF;
  138. RPT_FILE_USER_ASSIGNMENTS = ON;
  139. RPT_FILE_LCELL_INTERCONNECT = ON;
  140. RPT_FILE_HIERARCHY = ON;
  141. RPT_FILE_EQUATIONS = ON;
  142. LINKED_SNF_EXTRACTOR = OFF;
  143. OPTIMIZE_TIMING_SNF = OFF;
  144. TIMING_SNF_EXTRACTOR = ON;
  145. FUNCTIONAL_SNF_EXTRACTOR = OFF;
  146. DESIGN_DOCTOR_RULES = EPLD;
  147. DESIGN_DOCTOR = OFF;
  148. END;
  150. COMPILER_INTERFACES_CONFIGURATION
  151. BEGIN
  152. NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
  153. EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
  154. EDIF_BUS_DELIMITERS = [];
  155. EDIF_FLATTEN_BUS = OFF;
  156. EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
  157. EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
  158. EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
  159. EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
  160. EDIF_OUTPUT_USE_EDC = OFF;
  161. EDIF_INPUT_USE_LMF2 = OFF;
  162. EDIF_INPUT_USE_LMF1 = OFF;
  163. EDIF_OUTPUT_GND = GND;
  164. EDIF_OUTPUT_VCC = VCC;
  165. EDIF_INPUT_GND = GND;
  166. EDIF_INPUT_VCC = VCC;
  167. EDIF_OUTPUT_EDC_FILE = *.edc;
  168. EDIF_INPUT_LMF2 = *.lmf;
  169. EDIF_INPUT_LMF1 = *.lmf;
  170. VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
  171. VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
  172. VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
  173. VHDL_FLATTEN_BUS = OFF;
  174. VERILOG_FLATTEN_BUS = OFF;
  175. EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
  176. VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
  177. VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
  178. VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
  179. VHDL_WRITER_VERSION = VHDL93;
  180. VHDL_READER_VERSION = VHDL93;
  181. SYNOPSYS_MAPPING_EFFORT = MEDIUM;
  182. SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
  183. SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
  184. SYNOPSYS_DESIGNWARE = OFF;
  185. SYNOPSYS_COMPILER = DESIGN;
  186. USE_SYNOPSYS_SYNTHESIS = OFF;
  187. VHDL_NETLIST_WRITER = OFF;
  188. VERILOG_NETLIST_WRITER = OFF;
  189. XNF_GENERATE_AHDL_TDX_FILE = ON;
  190. XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
  191. XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
  192. EDIF_OUTPUT_VERSION = 200;
  193. EDIF_NETLIST_WRITER = OFF;
  194. END;
  196. CUSTOM_DESIGN_DOCTOR_RULES
  197. BEGIN
  198. MASTER_RESET = OFF;
  199. EXPANDER_NETWORKS = ON;
  200. RACE_CONDITIONS = ON;
  201. DELAY_CHAINS = ON;
  202. ASYNCHRONOUS_INPUTS = ON;
  203. PRESET_CLEAR_NETWORKS = ON;
  204. STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
  205. STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
  206. MULTI_CLOCK_NETWORKS = ON;
  207. MULTI_LEVEL_CLOCKS = ON;
  208. GATED_CLOCKS = ON;
  209. RIPPLE_CLOCKS = ON;
  210. END;
  212. SIMULATOR_CONFIGURATION
  213. BEGIN
  214. BIDIR_PIN = STRONG;
  215. END_TIME = 0.0ns;
  216. START_TIME = 0.0ns;
  217. GLITCH_TIME = 0.0ns;
  218. GLITCH = OFF;
  219. OSCILLATION_TIME = 0.0ns;
  220. OSCILLATION = OFF;
  221. CHECK_OUTPUTS = OFF;
  222. SETUP_HOLD = OFF;
  223. USE_DEVICE = OFF;
  224. END;
  226. TIMING_ANALYZER_CONFIGURATION
  227. BEGIN
  228. CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
  229. LIST_PATH_FREQUENCY = 10MHz;
  230. LIST_PATH_COUNT = 10;
  231. REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
  232. INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
  233. INCLUDE_PATHS_LESS_THAN = OFF;
  234. INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
  235. INCLUDE_PATHS_GREATER_THAN = OFF;
  236. DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
  237. CELL_WIDTH = 18;
  238. LIST_ONLY_LONGEST_PATH = ON;
  239. CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
  240. CUT_OFF_IO_PIN_FEEDBACK = ON;
  241. AUTO_RECALCULATE = OFF;
  242. ANALYSIS_MODE = DELAY_MATRIX;
  243. END;
  245. OTHER_CONFIGURATION
  246. BEGIN
  247. EXPLICIT_FAMILY = 1;
  248. LAST_MAXPLUS2_VERSION = 10.0;
  249. FLEX_10K_52_COLUMNS = 40;
  250. DEFAULT_9K_EXP_PER_LCELL = 1/2;
  251. LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
  252. LCELLS_PER_ROW_PERCENT = 100;
  253. FAN_IN_PER_LCELL_PERCENT = 100;
  254. EXP_PER_LCELL_PERCENT = 100;
  255. ROW_PINS_PERCENT = 50;
  256. ORIGINAL_MAXPLUS2_VERSION = 10.0;
  257. COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
  258. END;
  260. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
  261. BEGIN
  262. REGISTER_OPTIMIZATION = ON;
  263. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  264. RESYNTHESIZE_NETWORK = ON;
  265. MULTI_LEVEL_FACTORING = ON;
  266. SUBFACTOR_EXTRACTION = ON;
  267. REFACTORIZATION = ON;
  268. NOT_GATE_PUSH_BACK = ON;
  269. DUPLICATE_LOGIC_EXTRACTION = ON;
  270. REDUCE_LOGIC = ON;
  271. DECOMPOSE_GATES = ON;
  272. SOFT_BUFFER_INSERTION = ON;
  273. FAST_IO = OFF;
  274. IGNORE_SOFT_BUFFERS = OFF;
  275. PARALLEL_EXPANDERS = OFF;
  276. TURBO_BIT = OFF;
  277. XOR_SYNTHESIS = ON;
  278. SLOW_SLEW_RATE = OFF;
  279. MINIMIZATION = FULL;
  280. CARRY_CHAIN_LENGTH = -1;
  281. CARRY_CHAIN = IGNORE;
  282. CASCADE_CHAIN_LENGTH = -1;
  283. CASCADE_CHAIN = IGNORE;
  284. END;
  286. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
  287. BEGIN
  288. REGISTER_OPTIMIZATION = ON;
  289. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  290. RESYNTHESIZE_NETWORK = ON;
  291. MULTI_LEVEL_FACTORING = ON;
  292. SUBFACTOR_EXTRACTION = ON;
  293. REFACTORIZATION = ON;
  294. NOT_GATE_PUSH_BACK = ON;
  295. DUPLICATE_LOGIC_EXTRACTION = ON;
  296. REDUCE_LOGIC = ON;
  297. DECOMPOSE_GATES = ON;
  298. SOFT_BUFFER_INSERTION = ON;
  299. FAST_IO = OFF;
  300. IGNORE_SOFT_BUFFERS = OFF;
  301. PARALLEL_EXPANDERS = OFF;
  302. TURBO_BIT = ON;
  303. XOR_SYNTHESIS = ON;
  304. SLOW_SLEW_RATE = OFF;
  305. MINIMIZATION = FULL;
  306. CARRY_CHAIN_LENGTH = -1;
  307. CARRY_CHAIN = IGNORE;
  308. CASCADE_CHAIN_LENGTH = -1;
  309. CASCADE_CHAIN = IGNORE;
  310. END;
  312. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
  313. BEGIN
  314. REGISTER_OPTIMIZATION = OFF;
  315. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  316. RESYNTHESIZE_NETWORK = ON;
  317. MULTI_LEVEL_FACTORING = OFF;
  318. SUBFACTOR_EXTRACTION = OFF;
  319. REFACTORIZATION = OFF;
  320. NOT_GATE_PUSH_BACK = ON;
  321. DUPLICATE_LOGIC_EXTRACTION = OFF;
  322. REDUCE_LOGIC = OFF;
  323. DECOMPOSE_GATES = ON;
  324. SOFT_BUFFER_INSERTION = ON;
  325. FAST_IO = OFF;
  326. IGNORE_SOFT_BUFFERS = OFF;
  327. PARALLEL_EXPANDERS = OFF;
  328. TURBO_BIT = ON;
  329. XOR_SYNTHESIS = OFF;
  330. SLOW_SLEW_RATE = OFF;
  331. MINIMIZATION = FULL;
  332. CARRY_CHAIN_LENGTH = -1;
  333. CARRY_CHAIN = IGNORE;
  334. CASCADE_CHAIN_LENGTH = -1;
  335. CASCADE_CHAIN = IGNORE;
  336. END;
  338. DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
  339. BEGIN
  340. REGISTER_OPTIMIZATION = ON;
  341. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  342. RESYNTHESIZE_NETWORK = ON;
  343. MULTI_LEVEL_FACTORING = ON;
  344. SUBFACTOR_EXTRACTION = ON;
  345. REFACTORIZATION = ON;
  346. NOT_GATE_PUSH_BACK = ON;
  347. DUPLICATE_LOGIC_EXTRACTION = ON;
  348. REDUCE_LOGIC = ON;
  349. DECOMPOSE_GATES = ON;
  350. SOFT_BUFFER_INSERTION = ON;
  351. IGNORE_SOFT_BUFFERS = ON;
  352. PARALLEL_EXPANDERS = OFF;
  353. TURBO_BIT = OFF;
  354. XOR_SYNTHESIS = OFF;
  355. SLOW_SLEW_RATE = OFF;
  356. MINIMIZATION = FULL;
  357. CARRY_CHAIN_LENGTH = 32;
  358. CARRY_CHAIN = IGNORE;
  359. CASCADE_CHAIN_LENGTH = 2;
  360. CASCADE_CHAIN = IGNORE;
  361. END;
  363. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
  364. BEGIN
  365. REGISTER_OPTIMIZATION = ON;
  366. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  367. RESYNTHESIZE_NETWORK = ON;
  368. MULTI_LEVEL_FACTORING = ON;
  369. SUBFACTOR_EXTRACTION = OFF;
  370. REFACTORIZATION = OFF;
  371. NOT_GATE_PUSH_BACK = ON;
  372. DUPLICATE_LOGIC_EXTRACTION = ON;
  373. REDUCE_LOGIC = ON;
  374. DECOMPOSE_GATES = ON;
  375. SOFT_BUFFER_INSERTION = ON;
  376. FAST_IO = OFF;
  377. IGNORE_SOFT_BUFFERS = OFF;
  378. PARALLEL_EXPANDERS = OFF;
  379. TURBO_BIT = OFF;
  380. XOR_SYNTHESIS = ON;
  381. SLOW_SLEW_RATE = OFF;
  382. MINIMIZATION = FULL;
  383. CARRY_CHAIN_LENGTH = -1;
  384. CARRY_CHAIN = IGNORE;
  385. CASCADE_CHAIN_LENGTH = -1;
  386. CASCADE_CHAIN = IGNORE;
  387. END;
  389. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
  390. BEGIN
  391. REGISTER_OPTIMIZATION = ON;
  392. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  393. RESYNTHESIZE_NETWORK = ON;
  394. MULTI_LEVEL_FACTORING = ON;
  395. SUBFACTOR_EXTRACTION = OFF;
  396. REFACTORIZATION = OFF;
  397. NOT_GATE_PUSH_BACK = ON;
  398. DUPLICATE_LOGIC_EXTRACTION = ON;
  399. REDUCE_LOGIC = ON;
  400. DECOMPOSE_GATES = ON;
  401. SOFT_BUFFER_INSERTION = ON;
  402. FAST_IO = OFF;
  403. IGNORE_SOFT_BUFFERS = OFF;
  404. PARALLEL_EXPANDERS = ON;
  405. TURBO_BIT = ON;
  406. XOR_SYNTHESIS = ON;
  407. SLOW_SLEW_RATE = OFF;
  408. MINIMIZATION = FULL;
  409. CARRY_CHAIN_LENGTH = -1;
  410. CARRY_CHAIN = IGNORE;
  411. CASCADE_CHAIN_LENGTH = -1;
  412. CASCADE_CHAIN = IGNORE;
  413. END;
  415. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
  416. BEGIN
  417. REGISTER_OPTIMIZATION = OFF;
  418. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  419. RESYNTHESIZE_NETWORK = ON;
  420. MULTI_LEVEL_FACTORING = OFF;
  421. SUBFACTOR_EXTRACTION = OFF;
  422. REFACTORIZATION = OFF;
  423. NOT_GATE_PUSH_BACK = ON;
  424. DUPLICATE_LOGIC_EXTRACTION = OFF;
  425. REDUCE_LOGIC = OFF;
  426. DECOMPOSE_GATES = ON;
  427. SOFT_BUFFER_INSERTION = ON;
  428. FAST_IO = OFF;
  429. IGNORE_SOFT_BUFFERS = OFF;
  430. PARALLEL_EXPANDERS = OFF;
  431. TURBO_BIT = ON;
  432. XOR_SYNTHESIS = OFF;
  433. SLOW_SLEW_RATE = OFF;
  434. MINIMIZATION = FULL;
  435. CARRY_CHAIN_LENGTH = -1;
  436. CARRY_CHAIN = IGNORE;
  437. CASCADE_CHAIN_LENGTH = -1;
  438. CASCADE_CHAIN = IGNORE;
  439. END;
  441. DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
  442. BEGIN
  443. REGISTER_OPTIMIZATION = ON;
  444. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  445. RESYNTHESIZE_NETWORK = ON;
  446. MULTI_LEVEL_FACTORING = ON;
  447. SUBFACTOR_EXTRACTION = OFF;
  448. REFACTORIZATION = OFF;
  449. NOT_GATE_PUSH_BACK = ON;
  450. DUPLICATE_LOGIC_EXTRACTION = ON;
  451. REDUCE_LOGIC = ON;
  452. DECOMPOSE_GATES = ON;
  453. SOFT_BUFFER_INSERTION = ON;
  454. IGNORE_SOFT_BUFFERS = ON;
  455. PARALLEL_EXPANDERS = OFF;
  456. TURBO_BIT = OFF;
  457. XOR_SYNTHESIS = OFF;
  458. SLOW_SLEW_RATE = OFF;
  459. MINIMIZATION = FULL;
  460. CARRY_CHAIN_LENGTH = 32;
  461. CARRY_CHAIN = AUTO;
  462. CASCADE_CHAIN_LENGTH = 2;
  463. CASCADE_CHAIN = AUTO;
  464. END;
  466. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
  467. BEGIN
  468. REGISTER_OPTIMIZATION = OFF;
  469. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  470. RESYNTHESIZE_NETWORK = OFF;
  471. MULTI_LEVEL_FACTORING = OFF;
  472. SUBFACTOR_EXTRACTION = OFF;
  473. REFACTORIZATION = OFF;
  474. NOT_GATE_PUSH_BACK = ON;
  475. DUPLICATE_LOGIC_EXTRACTION = OFF;
  476. REDUCE_LOGIC = OFF;
  477. DECOMPOSE_GATES = OFF;
  478. SOFT_BUFFER_INSERTION = OFF;
  479. FAST_IO = OFF;
  480. IGNORE_SOFT_BUFFERS = OFF;
  481. PARALLEL_EXPANDERS = OFF;
  482. TURBO_BIT = OFF;
  483. XOR_SYNTHESIS = OFF;
  484. SLOW_SLEW_RATE = OFF;
  485. MINIMIZATION = PARTIAL;
  486. CARRY_CHAIN_LENGTH = -1;
  487. CARRY_CHAIN = IGNORE;
  488. CASCADE_CHAIN_LENGTH = -1;
  489. CASCADE_CHAIN = IGNORE;
  490. END;
  492. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
  493. BEGIN
  494. REGISTER_OPTIMIZATION = OFF;
  495. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  496. RESYNTHESIZE_NETWORK = OFF;
  497. MULTI_LEVEL_FACTORING = OFF;
  498. SUBFACTOR_EXTRACTION = OFF;
  499. REFACTORIZATION = OFF;
  500. NOT_GATE_PUSH_BACK = ON;
  501. DUPLICATE_LOGIC_EXTRACTION = OFF;
  502. REDUCE_LOGIC = OFF;
  503. DECOMPOSE_GATES = OFF;
  504. SOFT_BUFFER_INSERTION = OFF;
  505. FAST_IO = OFF;
  506. IGNORE_SOFT_BUFFERS = OFF;
  507. PARALLEL_EXPANDERS = OFF;
  508. TURBO_BIT = ON;
  509. XOR_SYNTHESIS = OFF;
  510. SLOW_SLEW_RATE = OFF;
  511. MINIMIZATION = PARTIAL;
  512. CARRY_CHAIN_LENGTH = -1;
  513. CARRY_CHAIN = IGNORE;
  514. CASCADE_CHAIN_LENGTH = -1;
  515. CASCADE_CHAIN = IGNORE;
  516. END;
  518. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
  519. BEGIN
  520. REGISTER_OPTIMIZATION = OFF;
  521. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  522. RESYNTHESIZE_NETWORK = ON;
  523. MULTI_LEVEL_FACTORING = OFF;
  524. SUBFACTOR_EXTRACTION = OFF;
  525. REFACTORIZATION = OFF;
  526. NOT_GATE_PUSH_BACK = ON;
  527. DUPLICATE_LOGIC_EXTRACTION = OFF;
  528. REDUCE_LOGIC = OFF;
  529. DECOMPOSE_GATES = ON;
  530. SOFT_BUFFER_INSERTION = OFF;
  531. FAST_IO = OFF;
  532. IGNORE_SOFT_BUFFERS = OFF;
  533. PARALLEL_EXPANDERS = OFF;
  534. TURBO_BIT = ON;
  535. XOR_SYNTHESIS = OFF;
  536. SLOW_SLEW_RATE = OFF;
  537. MINIMIZATION = PARTIAL;
  538. CARRY_CHAIN_LENGTH = -1;
  539. CARRY_CHAIN = IGNORE;
  540. CASCADE_CHAIN_LENGTH = -1;
  541. CASCADE_CHAIN = IGNORE;
  542. END;
  544. DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
  545. BEGIN
  546. REGISTER_OPTIMIZATION = OFF;
  547. USE_LPM_FOR_AHDL_OPERATORS = OFF;
  548. RESYNTHESIZE_NETWORK = OFF;
  549. MULTI_LEVEL_FACTORING = OFF;
  550. SUBFACTOR_EXTRACTION = OFF;
  551. REFACTORIZATION = OFF;
  552. NOT_GATE_PUSH_BACK = ON;
  553. DUPLICATE_LOGIC_EXTRACTION = OFF;
  554. REDUCE_LOGIC = OFF;
  555. DECOMPOSE_GATES = OFF;
  556. SOFT_BUFFER_INSERTION = ON;
  557. IGNORE_SOFT_BUFFERS = ON;
  558. PARALLEL_EXPANDERS = OFF;
  559. TURBO_BIT = OFF;
  560. XOR_SYNTHESIS = OFF;
  561. SLOW_SLEW_RATE = OFF;
  562. MINIMIZATION = PARTIAL;
  563. CARRY_CHAIN_LENGTH = 32;
  564. CARRY_CHAIN = MANUAL;
  565. CASCADE_CHAIN_LENGTH = 2;
  566. CASCADE_CHAIN = MANUAL;
  567. END;