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pipecu.rpt
资源名称：mips.rar [点击查看]
上传用户：huang_5966
上传日期：2022-08-09
资源大小：439k
文件大小：39k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Project Information e:doucumentsprojectsmips__1080379086pipecu.rpt
- MAX+plus II Compiler Report File
- Version 10.0 9/14/2000
- Compiled: 12/13/2008 01:29:43
- Copyright (C) 1988-2000 Altera Corporation
- Any megafunction design, and related net list (encrypted or decrypted),
- support information, device programming or simulation file, and any other
- associated documentation or information provided by Altera or a partner
- under Altera's Megafunction Partnership Program may be used only to
- program PLD devices (but not masked PLD devices) from Altera. Any other
- use of such megafunction design, net list, support information, device
- programming or simulation file, or any other related documentation or
- information is prohibited for any other purpose, including, but not
- limited to modification, reverse engineering, de-compiling, or use with
- any other silicon devices, unless such use is explicitly licensed under
- a separate agreement with Altera or a megafunction partner. Title to
- the intellectual property, including patents, copyrights, trademarks,
- trade secrets, or maskworks, embodied in any such megafunction design,
- net list, support information, device programming or simulation file, or
- any other related documentation or information provided by Altera or a
- megafunction partner, remains with Altera, the megafunction partner, or
- their respective licensors. No other licenses, including any licenses
- needed under any third party's intellectual property, are provided herein.
- ***** Project compilation was successful
- ** DEVICE SUMMARY **
- Chip/ Input Output Bidir Memory Memory LCs
- POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
- pipecu EPF10K10LC84-3 35 18 0 0 0 % 48 8 %
- User Pins: 35 18 0
- Project Information e:doucumentsprojectsmips__1080379086pipecu.rpt
- ** PROJECT COMPILATION MESSAGES **
- Warning: Ignored unnecessary INPUT pin 'FUNC4'
- Warning: Ignored unnecessary INPUT pin 'FUNC3'
- Project Information e:doucumentsprojectsmips__1080379086pipecu.rpt
- ** FILE HIERARCHY **
- |instdec:31|
- |equ5:55|
- |equ5:58|
- |equ5:57|
- |equ5:56|
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ***** Logic for device 'pipecu' compiled without errors.
- Device: EPF10K10LC84-3
- FLEX 10K Configuration Scheme: Passive Serial
- Device Options:
- User-Supplied Start-Up Clock = OFF
- Auto-Restart Configuration on Frame Error = OFF
- Release Clears Before Tri-States = OFF
- Enable Chip_Wide Reset = OFF
- Enable Chip-Wide Output Enable = OFF
- Enable INIT_DONE Output = OFF
- JTAG User Code = 7f
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** ERROR SUMMARY **
- Info: Chip 'pipecu' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
- ^
- C
- R R O
- E E N
- E E S E S V G M F
- D D E D E C F F A N D M _ ^
- E E R E R C U U L D E W # D n
- S R S R V S V I R O N N U I S R R R T O C
- R T R T E R E N S P C C C N R E S T C N E
- 2 2 3 3 D 4 D T 3 0 0 5 0 T 1 G 4 4 K E O
- -----------------------------------------------------------------_
- / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
- ^DATA0 | 12 74 | #TDO
- ^DCLK | 13 73 | WPCIR
- ^nCE | 14 72 | RESERVED
- #TDI | 15 71 | ALUC3
- RESERVED | 16 70 | WREG
- FWDA0 | 17 69 | ALUIMM
- RESERVED | 18 68 | GNDINT
- RESERVED | 19 67 | ALUC2
- VCCINT | 20 66 | SEXT
- OP4 | 21 65 | BRANCH
- SHIFT | 22 EPF10K10LC84-3 64 | RSRTEQU
- FUNC2 | 23 63 | VCCINT
- OP1 | 24 62 | EM2REG
- OP5 | 25 61 | FWDA1
- GNDINT | 26 60 | FWDB1
- MDESR4 | 27 59 | EWREG
- EDESR0 | 28 58 | WMEM
- MM2REG | 29 57 | #TMS
- MDESR0 | 30 56 | #TRST
- ^MSEL0 | 31 55 | ^nSTATUS
- ^MSEL1 | 32 54 | RS1
- |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
- ------------------------------------------------------------------
- V ^ R M R M R V G O F O V G R F A J M R E
- C n T D S D T C N P U P C N E W L U 2 S D
- C C 1 E 2 E 0 C D 3 N 2 C D G D U M R 0 E
- I O S S I I C I I R B C P E S
- N N R R N N 1 N N T 0 1 G R
- T F 3 2 T T T T 1
- I
- G
- N.C. = No Connect. This pin has no internal connection to the device.
- VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
- GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
- GNDIO = Dedicated ground pin, which MUST be connected to GND.
- RESERVED = Unused I/O pin, which MUST be left unconnected.
- ^ = Dedicated configuration pin.
- + = Reserved configuration pin, which is tri-stated during user mode.
- * = Reserved configuration pin, which drives out in user mode.
- PDn = Power Down pin.
- @ = Special-purpose pin.
- # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
- & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** RESOURCE USAGE **
- Logic Column Row
- Array Interconnect Interconnect Clears/ External
- Block Logic Cells Driven Driven Clocks Presets Interconnect
- B14 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
- B16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
- B17 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
- B18 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
- B21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
- C8 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
- C13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
- C16 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
- Embedded Column Row
- Array Embedded Interconnect Interconnect Read/ External
- Block Cells Driven Driven Clocks Write Interconnect
- Total dedicated input pins used: 6/6 (100%)
- Total I/O pins used: 47/53 ( 88%)
- Total logic cells used: 48/576 ( 8%)
- Total embedded cells used: 0/24 ( 0%)
- Total EABs used: 0/3 ( 0%)
- Average fan-in: 3.47/4 ( 86%)
- Total fan-in: 167/2304 ( 7%)
- Total input pins required: 35
- Total input I/O cell registers required: 0
- Total output pins required: 18
- Total output I/O cell registers required: 0
- Total buried I/O cell registers required: 0
- Total bidirectional pins required: 0
- Total reserved pins required 0
- Total logic cells required: 48
- Total flipflops required: 0
- Total packed registers required: 0
- Total logic cells in carry chains: 0
- Total number of carry chains: 0
- Total logic cells in cascade chains: 0
- Total number of cascade chains: 0
- Total single-pin Clock Enables required: 0
- Total single-pin Output Enables required: 0
- Synthesized logic cells: 25/ 576 ( 4%)
- Logic Cell and Embedded Cell Counts
- Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
- A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
- B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 8 3 0 0 1 0 0 0 28/0
- C: 0 0 0 0 0 0 0 4 0 0 0 0 0 8 0 0 8 0 0 0 0 0 0 0 0 20/0
- Total: 0 0 0 0 0 0 0 4 0 0 0 0 0 8 8 0 16 8 3 0 0 1 0 0 0 48/0
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** INPUTS **
- Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 28 - - C -- INPUT 0 0 0 2 EDESR0
- 53 - - - 20 INPUT 0 0 0 2 EDESR1
- 11 - - - 01 INPUT 0 0 0 2 EDESR2
- 9 - - - 02 INPUT 0 0 0 2 EDESR3
- 6 - - - 04 INPUT 0 0 0 2 EDESR4
- 62 - - C -- INPUT 0 0 0 3 EM2REG
- 59 - - C -- INPUT 0 0 0 3 EWREG
- 1 - - - -- INPUT 0 0 0 4 FUNC0
- 43 - - - -- INPUT 0 0 0 4 FUNC1
- 23 - - B -- INPUT 0 0 0 2 FUNC2
- 84 - - - -- INPUT 0 0 0 4 FUNC5
- 30 - - C -- INPUT 0 0 0 2 MDESR0
- 81 - - - 22 INPUT 0 0 0 2 MDESR1
- 38 - - - 10 INPUT 0 0 0 2 MDESR2
- 36 - - - 07 INPUT 0 0 0 2 MDESR3
- 27 - - C -- INPUT 0 0 0 2 MDESR4
- 29 - - C -- INPUT 0 0 0 2 MM2REG
- 80 - - - 23 INPUT 0 0 0 2 MWREG
- 2 - - - -- INPUT 0 0 0 10 OP0
- 24 - - B -- INPUT 0 0 0 4 OP1
- 44 - - - -- INPUT 0 0 0 5 OP2
- 42 - - - -- INPUT 0 0 0 7 OP3
- 21 - - B -- INPUT 0 0 0 4 OP4
- 25 - - B -- INPUT 0 0 0 4 OP5
- 64 - - B -- INPUT 0 0 0 1 RSRTEQU
- 52 - - - 19 INPUT 0 0 0 2 RS0
- 54 - - - 21 INPUT 0 0 0 2 RS1
- 37 - - - 09 INPUT 0 0 0 2 RS2
- 3 - - - 12 INPUT 0 0 0 2 RS3
- 79 - - - 24 INPUT 0 0 0 2 RS4
- 39 - - - 11 INPUT 0 0 0 2 RT0
- 35 - - - 06 INPUT 0 0 0 2 RT1
- 10 - - - 01 INPUT 0 0 0 2 RT2
- 8 - - - 03 INPUT 0 0 0 2 RT3
- 78 - - - 24 INPUT 0 0 0 2 RT4
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** OUTPUTS **
- Fed By Fed By Fan-In Fan-Out
- Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 83 - - - 13 OUTPUT 0 1 0 0 ALUC0
- 49 - - - 16 OUTPUT 0 1 0 0 ALUC1
- 67 - - B -- OUTPUT 0 1 0 0 ALUC2
- 71 - - A -- OUTPUT 0 1 0 0 ALUC3
- 69 - - A -- OUTPUT 0 1 0 0 ALUIMM
- 65 - - B -- OUTPUT 0 1 0 0 BRANCH
- 17 - - A -- OUTPUT 0 1 0 0 FWDA0
- 61 - - C -- OUTPUT 0 1 0 0 FWDA1
- 48 - - - 15 OUTPUT 0 1 0 0 FWDB0
- 60 - - C -- OUTPUT 0 1 0 0 FWDB1
- 50 - - - 17 OUTPUT 0 1 0 0 JUMP
- 51 - - - 18 OUTPUT 0 1 0 0 M2REG
- 47 - - - 14 OUTPUT 0 1 0 0 REGRT
- 66 - - B -- OUTPUT 0 1 0 0 SEXT
- 22 - - B -- OUTPUT 0 1 0 0 SHIFT
- 58 - - C -- OUTPUT 0 1 0 0 WMEM
- 73 - - A -- OUTPUT 0 1 0 0 WPCIR
- 70 - - A -- OUTPUT 0 1 0 0 WREG
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- @ = Uses single-pin Clock Enable
- & = Uses single-pin Output Enable
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** BURIED LOGIC **
- Fan-In Fan-Out
- IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 2 - C 13 OR2 s ! 4 0 0 1 |equ5:56|EQU~1 (|equ5:56|~23~1)
- - 1 - C 08 OR2 s ! 4 0 0 1 |equ5:56|EQU~2 (|equ5:56|~23~2)
- - 4 - C 16 OR2 ! 2 2 0 2 |equ5:56|EQU (|equ5:56|:23)
- - 1 - C 13 OR2 s ! 4 0 0 1 |equ5:58|EQU~1 (|equ5:58|~23~1)
- - 2 - C 08 OR2 s ! 4 0 0 1 |equ5:58|EQU~2 (|equ5:58|~23~2)
- - 5 - C 16 OR2 ! 2 2 0 2 |equ5:58|EQU (|equ5:58|:23)
- - 6 - B 17 AND2 s 3 0 0 3 |instdec:31|R~1 (|instdec:31|~20~1)
- - 3 - B 18 AND2 0 2 0 1 |instdec:31|R (|instdec:31|:20)
- - 2 - B 18 AND2 s 1 2 0 3 |instdec:31|ADD~1 (|instdec:31|~24~1)
- - 5 - B 16 AND2 s 2 1 0 3 |instdec:31|ADD~2 (|instdec:31|~24~2)
- - 1 - B 18 AND2 s 3 1 0 2 |instdec:31|AND~1 (|instdec:31|~26~1)
- - 7 - B 16 AND2 s 2 1 0 3 |instdec:31|SLL~1 (|instdec:31|~28~1)
- - 4 - B 16 AND2 3 1 1 2 |instdec:31|SRA (|instdec:31|:30)
- - 1 - B 17 AND2 s 4 0 0 2 |instdec:31|ADDI~1 (|instdec:31|~32~1)
- - 5 - B 14 AND2 s 1 1 0 3 |instdec:31|ANDI~1 (|instdec:31|~33~1)
- - 7 - B 14 AND2 1 1 0 3 |instdec:31|ORI (|instdec:31|:34)
- - 3 - B 14 AND2 2 1 0 1 |instdec:31|LW (|instdec:31|:35)
- - 2 - B 17 AND2 s 4 0 0 4 |instdec:31|SW~1 (|instdec:31|~36~1)
- - 3 - B 17 AND2 3 1 1 1 |instdec:31|J (|instdec:31|:39)
- - 8 - B 17 OR2 s 3 0 0 1 ~34~1
- - 4 - B 17 AND2 s 3 0 0 3 ~34~2
- - 5 - B 17 OR2 1 3 1 2 :34
- - 2 - B 14 OR2 2 2 1 2 :36
- - 1 - B 16 OR2 1 3 1 1 :38
- - 2 - B 16 OR2 0 2 1 2 :39
- - 4 - B 14 OR2 s 2 2 0 2 ~46~1
- - 1 - B 14 OR2 1 3 1 1 :46
- - 8 - B 14 OR2 1 3 1 0 :49
- - 5 - C 13 OR2 s 4 0 0 1 ~59~1
- - 6 - C 13 OR2 s 3 0 0 1 ~59~2
- - 5 - C 08 OR2 s 4 0 0 1 ~59~3
- - 3 - C 13 AND2 0 3 1 1 :59
- - 2 - C 16 OR2 1 3 1 0 :63
- - 8 - C 16 OR2 1 3 1 0 :67
- - 7 - C 13 OR2 s 4 0 0 1 ~69~1
- - 8 - C 13 OR2 s 3 0 0 1 ~69~2
- - 8 - C 08 OR2 s 4 0 0 1 ~69~3
- - 4 - C 13 AND2 0 3 1 1 :69
- - 1 - C 16 OR2 2 2 1 1 :73
- - 7 - C 16 AND2 s 2 0 0 2 ~77~1
- - 7 - B 17 OR2 2 2 1 0 :85
- - 6 - C 16 AND2 2 2 1 0 :86
- - 3 - C 16 OR2 s 2 1 0 2 ~89~1
- - 8 - B 16 OR2 s 1 2 0 1 ~89~2
- - 3 - B 16 OR2 s 0 3 0 1 ~89~3
- - 5 - B 21 OR2 0 4 1 0 :89
- - 6 - B 16 OR2 0 3 1 0 :90
- - 6 - B 14 OR2 1 3 1 0 :91
- Code:
- s = Synthesized pin or logic cell
- + = Synchronous flipflop
- / = Slow slew-rate output
- ! = NOT gate push-back
- r = Fitter-inserted logic cell
- p = Packed register
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** FASTTRACK INTERCONNECT UTILIZATION **
- Row FastTrack Interconnect:
- Global Left Half- Right Half-
- FastTrack FastTrack FastTrack
- Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
- A: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
- B: 9/ 96( 9%) 0/ 48( 0%) 9/ 48( 18%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
- C: 15/ 96( 15%) 8/ 48( 16%) 11/ 48( 22%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
- Column FastTrack Interconnect:
- FastTrack
- Column Interconnect Input Pins Output Pins Bidir Pins
- 01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- 02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- 09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 16: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
- 19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 22: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
- 24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
- EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
- Device-Specific Information:e:doucumentsprojectsmips__1080379086pipecu.rpt
- pipecu
- ** EQUATIONS **
- EDESR0 : INPUT;
- EDESR1 : INPUT;
- EDESR2 : INPUT;
- EDESR3 : INPUT;
- EDESR4 : INPUT;
- EM2REG : INPUT;
- EWREG : INPUT;
- FUNC0 : INPUT;
- FUNC1 : INPUT;
- FUNC2 : INPUT;
- FUNC5 : INPUT;
- MDESR0 : INPUT;
- MDESR1 : INPUT;
- MDESR2 : INPUT;
- MDESR3 : INPUT;
- MDESR4 : INPUT;
- MM2REG : INPUT;
- MWREG : INPUT;
- OP0 : INPUT;
- OP1 : INPUT;
- OP2 : INPUT;
- OP3 : INPUT;
- OP4 : INPUT;
- OP5 : INPUT;
- RSRTEQU : INPUT;
- RS0 : INPUT;
- RS1 : INPUT;
- RS2 : INPUT;
- RS3 : INPUT;
- RS4 : INPUT;
- RT0 : INPUT;
- RT1 : INPUT;
- RT2 : INPUT;
- RT3 : INPUT;
- RT4 : INPUT;
- -- Node name is 'ALUC0'
- -- Equation name is 'ALUC0', type is output
- ALUC0 = _LC6_B14;
- -- Node name is 'ALUC1'
- -- Equation name is 'ALUC1', type is output
- ALUC1 = _LC6_B16;
- -- Node name is 'ALUC2'
- -- Equation name is 'ALUC2', type is output
- ALUC2 = _LC1_B16;
- -- Node name is 'ALUC3'
- -- Equation name is 'ALUC3', type is output
- ALUC3 = _LC4_B16;
- -- Node name is 'ALUIMM'
- -- Equation name is 'ALUIMM', type is output
- ALUIMM = _LC8_B14;
- -- Node name is 'BRANCH'
- -- Equation name is 'BRANCH', type is output
- BRANCH = _LC5_B17;
- -- Node name is 'FWDA0'
- -- Equation name is 'FWDA0', type is output
- FWDA0 = _LC2_C16;
- -- Node name is 'FWDA1'
- -- Equation name is 'FWDA1', type is output
- FWDA1 = _LC3_C13;
- -- Node name is 'FWDB0'
- -- Equation name is 'FWDB0', type is output
- FWDB0 = _LC8_C16;
- -- Node name is 'FWDB1'
- -- Equation name is 'FWDB1', type is output
- FWDB1 = _LC4_C13;
- -- Node name is 'JUMP'
- -- Equation name is 'JUMP', type is output
- JUMP = _LC3_B17;
- -- Node name is 'M2REG'
- -- Equation name is 'M2REG', type is output
- M2REG = _LC7_B17;
- -- Node name is 'REGRT'
- -- Equation name is 'REGRT', type is output
- REGRT = _LC1_B14;
- -- Node name is 'SEXT'
- -- Equation name is 'SEXT', type is output
- SEXT = _LC2_B14;
- -- Node name is 'SHIFT'
- -- Equation name is 'SHIFT', type is output
- SHIFT = _LC2_B16;
- -- Node name is 'WMEM'
- -- Equation name is 'WMEM', type is output
- WMEM = _LC6_C16;
- -- Node name is 'WPCIR'
- -- Equation name is 'WPCIR', type is output
- WPCIR = _LC1_C16;
- -- Node name is 'WREG'
- -- Equation name is 'WREG', type is output
- WREG = _LC5_B21;
- -- Node name is '|equ5:56|:23' = '|equ5:56|EQU'
- -- Equation name is '_LC4_C16', type is buried
- !_LC4_C16 = _LC4_C16~NOT;
- _LC4_C16~NOT = LCELL( _EQ001);
- _EQ001 = !_LC2_C13
- # !_LC1_C8
- # !EDESR4 & RS4
- # EDESR4 & !RS4;
- -- Node name is '|equ5:56|~23~1' = '|equ5:56|EQU~1'
- -- Equation name is '_LC2_C13', type is buried
- -- synthesized logic cell
- !_LC2_C13 = _LC2_C13~NOT;
- _LC2_C13~NOT = LCELL( _EQ002);
- _EQ002 = !EDESR1 & RS1
- # EDESR1 & !RS1
- # !EDESR0 & RS0
- # EDESR0 & !RS0;
- -- Node name is '|equ5:56|~23~2' = '|equ5:56|EQU~2'
- -- Equation name is '_LC1_C8', type is buried
- -- synthesized logic cell
- !_LC1_C8 = _LC1_C8~NOT;
- _LC1_C8~NOT = LCELL( _EQ003);
- _EQ003 = !EDESR3 & RS3
- # EDESR3 & !RS3
- # !EDESR2 & RS2
- # EDESR2 & !RS2;
- -- Node name is '|equ5:58|:23' = '|equ5:58|EQU'
- -- Equation name is '_LC5_C16', type is buried
- !_LC5_C16 = _LC5_C16~NOT;
- _LC5_C16~NOT = LCELL( _EQ004);
- _EQ004 = !_LC1_C13
- # !_LC2_C8
- # EDESR4 & !RT4
- # !EDESR4 & RT4;
- -- Node name is '|equ5:58|~23~1' = '|equ5:58|EQU~1'
- -- Equation name is '_LC1_C13', type is buried
- -- synthesized logic cell
- !_LC1_C13 = _LC1_C13~NOT;
- _LC1_C13~NOT = LCELL( _EQ005);
- _EQ005 = EDESR1 & !RT1
- # !EDESR1 & RT1
- # EDESR0 & !RT0
- # !EDESR0 & RT0;
- -- Node name is '|equ5:58|~23~2' = '|equ5:58|EQU~2'
- -- Equation name is '_LC2_C8', type is buried
- -- synthesized logic cell
- !_LC2_C8 = _LC2_C8~NOT;
- _LC2_C8~NOT = LCELL( _EQ006);
- _EQ006 = EDESR3 & !RT3
- # !EDESR3 & RT3
- # EDESR2 & !RT2
- # !EDESR2 & RT2;
- -- Node name is '|instdec:31|~32~1' = '|instdec:31|ADDI~1'
- -- Equation name is '_LC1_B17', type is buried
- -- synthesized logic cell
- _LC1_B17 = LCELL( _EQ007);
- _EQ007 = !OP1 & OP3 & !OP4 & !OP5;
- -- Node name is '|instdec:31|~24~1' = '|instdec:31|ADD~1'
- -- Equation name is '_LC2_B18', type is buried
- -- synthesized logic cell
- _LC2_B18 = LCELL( _EQ008);
- _EQ008 = !FUNC2 & _LC4_B17 & _LC6_B17;
- -- Node name is '|instdec:31|~24~2' = '|instdec:31|ADD~2'
- -- Equation name is '_LC5_B16', type is buried
- -- synthesized logic cell
- _LC5_B16 = LCELL( _EQ009);
- _EQ009 = !FUNC0 & FUNC5 & _LC2_B18;
- -- Node name is '|instdec:31|~33~1' = '|instdec:31|ANDI~1'
- -- Equation name is '_LC5_B14', type is buried
- -- synthesized logic cell
- _LC5_B14 = LCELL( _EQ010);
- _EQ010 = _LC1_B17 & OP2;
- -- Node name is '|instdec:31|~26~1' = '|instdec:31|AND~1'
- -- Equation name is '_LC1_B18', type is buried
- -- synthesized logic cell
- _LC1_B18 = LCELL( _EQ011);
- _EQ011 = !FUNC1 & FUNC2 & FUNC5 & _LC3_B18;
- -- Node name is '|instdec:31|:39' = '|instdec:31|J'
- -- Equation name is '_LC3_B17', type is buried
- _LC3_B17 = LCELL( _EQ012);
- _EQ012 = _LC6_B17 & OP1 & !OP4 & !OP5;
- -- Node name is '|instdec:31|:35' = '|instdec:31|LW'
- -- Equation name is '_LC3_B14', type is buried
- _LC3_B14 = LCELL( _EQ013);
- _EQ013 = _LC2_B17 & OP0 & !OP3;
- -- Node name is '|instdec:31|:34' = '|instdec:31|ORI'
- -- Equation name is '_LC7_B14', type is buried
- _LC7_B14 = LCELL( _EQ014);
- _EQ014 = _LC5_B14 & OP0;
- -- Node name is '|instdec:31|:20' = '|instdec:31|R'
- -- Equation name is '_LC3_B18', type is buried
- _LC3_B18 = LCELL( _EQ015);
- _EQ015 = _LC4_B17 & _LC6_B17;
- -- Node name is '|instdec:31|~20~1' = '|instdec:31|R~1'
- -- Equation name is '_LC6_B17', type is buried
- -- synthesized logic cell
- _LC6_B17 = LCELL( _EQ016);
- _EQ016 = !OP0 & !OP2 & !OP3;
- -- Node name is '|instdec:31|~28~1' = '|instdec:31|SLL~1'
- -- Equation name is '_LC7_B16', type is buried
- -- synthesized logic cell
- _LC7_B16 = LCELL( _EQ017);
- _EQ017 = !FUNC0 & !FUNC5 & _LC2_B18;
- -- Node name is '|instdec:31|:30' = '|instdec:31|SRA'
- -- Equation name is '_LC4_B16', type is buried
- _LC4_B16 = LCELL( _EQ018);
- _EQ018 = FUNC0 & FUNC1 & !FUNC5 & _LC2_B18;
- -- Node name is '|instdec:31|~36~1' = '|instdec:31|SW~1'
- -- Equation name is '_LC2_B17', type is buried
- -- synthesized logic cell
- _LC2_B17 = LCELL( _EQ019);
- _EQ019 = OP1 & !OP2 & !OP4 & OP5;
- -- Node name is '~34~1'
- -- Equation name is '~34~1', location is LC8_B17, type is buried.
- -- synthesized logic cell
- _LC8_B17 = LCELL( _EQ020);
- _EQ020 = !OP0 & OP2 & RSRTEQU
- # OP0 & OP2 & !RSRTEQU;
- -- Node name is '~34~2'
- -- Equation name is '~34~2', location is LC4_B17, type is buried.
- -- synthesized logic cell
- _LC4_B17 = LCELL( _EQ021);
- _EQ021 = !OP1 & !OP4 & !OP5;
- -- Node name is ':34'
- -- Equation name is '_LC5_B17', type is buried
- _LC5_B17 = LCELL( _EQ022);
- _EQ022 = _LC3_B17
- # _LC4_B17 & _LC8_B17 & !OP3;
- -- Node name is ':36'
- -- Equation name is '_LC2_B14', type is buried
- _LC2_B14 = LCELL( _EQ023);
- _EQ023 = _LC2_B17 & OP0 & OP3
- # _LC4_B14;
- -- Node name is ':38'
- -- Equation name is '_LC1_B16', type is buried
- _LC1_B16 = LCELL( _EQ024);
- _EQ024 = FUNC1 & _LC5_B16
- # _LC4_B16
- # FUNC1 & _LC7_B16;
- -- Node name is ':39'
- -- Equation name is '_LC2_B16', type is buried
- _LC2_B16 = LCELL( _EQ025);
- _EQ025 = _LC4_B16
- # _LC7_B16;
- -- Node name is '~46~1'
- -- Equation name is '~46~1', location is LC4_B14, type is buried.
- -- synthesized logic cell
- _LC4_B14 = LCELL( _EQ026);
- _EQ026 = _LC3_B14
- # _LC1_B17 & !OP0 & !OP2;
- -- Node name is ':46'
- -- Equation name is '_LC1_B14', type is buried
- _LC1_B14 = LCELL( _EQ027);
- _EQ027 = _LC4_B14
- # _LC7_B14
- # _LC5_B14 & !OP0;
- -- Node name is ':49'
- -- Equation name is '_LC8_B14', type is buried
- _LC8_B14 = LCELL( _EQ028);
- _EQ028 = _LC2_B14
- # _LC5_B14 & !OP0
- # _LC7_B14;
- -- Node name is '~59~1'
- -- Equation name is '~59~1', location is LC5_C13, type is buried.
- -- synthesized logic cell
- _LC5_C13 = LCELL( _EQ029);
- _EQ029 = MDESR0 & MDESR1 & RS0 & RS1
- # MDESR0 & !MDESR1 & RS0 & !RS1
- # !MDESR0 & MDESR1 & !RS0 & RS1
- # !MDESR0 & !MDESR1 & !RS0 & !RS1;
- -- Node name is '~59~2'
- -- Equation name is '~59~2', location is LC6_C13, type is buried.
- -- synthesized logic cell
- _LC6_C13 = LCELL( _EQ030);
- _EQ030 = MDESR4 & MWREG & RS4
- # !MDESR4 & MWREG & !RS4;
- -- Node name is '~59~3'
- -- Equation name is '~59~3', location is LC5_C8, type is buried.
- -- synthesized logic cell
- _LC5_C8 = LCELL( _EQ031);
- _EQ031 = MDESR2 & MDESR3 & RS2 & RS3
- # MDESR2 & !MDESR3 & RS2 & !RS3
- # !MDESR2 & MDESR3 & !RS2 & RS3
- # !MDESR2 & !MDESR3 & !RS2 & !RS3;
- -- Node name is ':59'
- -- Equation name is '_LC3_C13', type is buried
- _LC3_C13 = LCELL( _EQ032);
- _EQ032 = _LC5_C8 & _LC5_C13 & _LC6_C13;
- -- Node name is ':63'
- -- Equation name is '_LC2_C16', type is buried
- _LC2_C16 = LCELL( _EQ033);
- _EQ033 = _LC3_C13 & MM2REG
- # _LC4_C16 & _LC7_C16;
- -- Node name is ':67'
- -- Equation name is '_LC8_C16', type is buried
- _LC8_C16 = LCELL( _EQ034);
- _EQ034 = _LC4_C13 & MM2REG
- # _LC5_C16 & _LC7_C16;
- -- Node name is '~69~1'
- -- Equation name is '~69~1', location is LC7_C13, type is buried.
- -- synthesized logic cell
- _LC7_C13 = LCELL( _EQ035);
- _EQ035 = MDESR0 & MDESR1 & RT0 & RT1
- # MDESR0 & !MDESR1 & RT0 & !RT1
- # !MDESR0 & MDESR1 & !RT0 & RT1
- # !MDESR0 & !MDESR1 & !RT0 & !RT1;
- -- Node name is '~69~2'
- -- Equation name is '~69~2', location is LC8_C13, type is buried.
- -- synthesized logic cell
- _LC8_C13 = LCELL( _EQ036);
- _EQ036 = MDESR4 & MWREG & RT4
- # !MDESR4 & MWREG & !RT4;
- -- Node name is '~69~3'
- -- Equation name is '~69~3', location is LC8_C8, type is buried.
- -- synthesized logic cell
- _LC8_C8 = LCELL( _EQ037);
- _EQ037 = MDESR2 & MDESR3 & RT2 & RT3
- # MDESR2 & !MDESR3 & RT2 & !RT3
- # !MDESR2 & MDESR3 & !RT2 & RT3
- # !MDESR2 & !MDESR3 & !RT2 & !RT3;
- -- Node name is ':69'
- -- Equation name is '_LC4_C13', type is buried
- _LC4_C13 = LCELL( _EQ038);
- _EQ038 = _LC7_C13 & _LC8_C8 & _LC8_C13;
- -- Node name is ':73'
- -- Equation name is '_LC1_C16', type is buried
- _LC1_C16 = LCELL( _EQ039);
- _EQ039 = !_LC4_C16 & !_LC5_C16
- # !EWREG
- # !EM2REG;
- -- Node name is '~77~1'
- -- Equation name is '~77~1', location is LC7_C16, type is buried.
- -- synthesized logic cell
- _LC7_C16 = LCELL( _EQ040);
- _EQ040 = !EM2REG & EWREG;
- -- Node name is ':85'
- -- Equation name is '_LC7_B17', type is buried
- _LC7_B17 = LCELL( _EQ041);
- _EQ041 = _LC2_B17 & OP0 & !OP3
- # _LC5_B17;
- -- Node name is ':86'
- -- Equation name is '_LC6_C16', type is buried
- _LC6_C16 = LCELL( _EQ042);
- _EQ042 = _LC2_B17 & _LC3_C16 & OP0 & OP3;
- -- Node name is '~89~1'
- -- Equation name is '~89~1', location is LC3_C16, type is buried.
- -- synthesized logic cell
- _LC3_C16 = LCELL( _EQ043);
- _EQ043 = EWREG & _LC1_C16
- # !EM2REG & _LC1_C16;
- -- Node name is '~89~2'
- -- Equation name is '~89~2', location is LC8_B16, type is buried.
- -- synthesized logic cell
- _LC8_B16 = LCELL( _EQ044);
- _EQ044 = !FUNC1 & _LC5_B16
- # !FUNC1 & _LC7_B16;
- -- Node name is '~89~3'
- -- Equation name is '~89~3', location is LC3_B16, type is buried.
- -- synthesized logic cell
- _LC3_B16 = LCELL( _EQ045);
- _EQ045 = _LC1_B14
- # _LC8_B16
- # _LC1_B18;
- -- Node name is ':89'
- -- Equation name is '_LC5_B21', type is buried
- _LC5_B21 = LCELL( _EQ046);
- _EQ046 = _LC1_B16 & _LC3_C16 & !_LC5_B17
- # _LC3_B16 & _LC3_C16 & !_LC5_B17;
- -- Node name is ':90'
- -- Equation name is '_LC6_B16', type is buried
- _LC6_B16 = LCELL( _EQ047);
- _EQ047 = _LC5_B16
- # _LC2_B14
- # _LC2_B16;
- -- Node name is ':91'
- -- Equation name is '_LC6_B14', type is buried
- _LC6_B14 = LCELL( _EQ048);
- _EQ048 = FUNC0 & _LC1_B18
- # _LC7_B14
- # _LC2_B16;
- Project Information e:doucumentsprojectsmips__1080379086pipecu.rpt
- ** COMPILATION SETTINGS & TIMES **
- Processing Menu Commands
- ------------------------
- Design Doctor = off
- Logic Synthesis:
- Synthesis Type Used = Multi-Level
- Default Synthesis Style = NORMAL
- Logic option settings in 'NORMAL' style for 'FLEX10K' family
- CARRY_CHAIN = ignore
- CARRY_CHAIN_LENGTH = 32
- CASCADE_CHAIN = ignore
- CASCADE_CHAIN_LENGTH = 2
- DECOMPOSE_GATES = on
- DUPLICATE_LOGIC_EXTRACTION = on
- MINIMIZATION = full
- MULTI_LEVEL_FACTORING = on
- NOT_GATE_PUSH_BACK = on
- REDUCE_LOGIC = on
- REFACTORIZATION = on
- REGISTER_OPTIMIZATION = on
- RESYNTHESIZE_NETWORK = on
- SLOW_SLEW_RATE = off
- SUBFACTOR_EXTRACTION = on
- IGNORE_SOFT_BUFFERS = on
- USE_LPM_FOR_AHDL_OPERATORS = off
- Other logic synthesis settings:
- Automatic Global Clock = on
- Automatic Global Clear = on
- Automatic Global Preset = on
- Automatic Global Output Enable = on
- Automatic Fast I/O = off
- Automatic Register Packing = off
- Automatic Open-Drain Pins = on
- Automatic Implement in EAB = off
- Optimize = 5
- Default Timing Specifications: None
- Cut All Bidir Feedback Timing Paths = on
- Cut All Clear & Preset Timing Paths = on
- Ignore Timing Assignments = on
- Functional SNF Extractor = off
- Linked SNF Extractor = off
- Timing SNF Extractor = on
- Optimize Timing SNF = off
- Generate AHDL TDO File = off
- Fitter Settings = NORMAL
- Use Quartus Fitter = on
- Smart Recompile = off
- Total Recompile = off
- Interfaces Menu Commands
- ------------------------
- EDIF Netlist Writer = off
- Verilog Netlist Writer = off
- VHDL Netlist Writer = off
- Compilation Times
- -----------------
- Compiler Netlist Extractor 00:00:00
- Database Builder 00:00:00
- Logic Synthesizer 00:00:00
- Partitioner 00:00:00
- Fitter 00:00:01
- Timing SNF Extractor 00:00:00
- Assembler 00:00:01
- -------------------------- --------
- Total Time 00:00:02
- Memory Allocated
- -----------------
- Peak memory allocated during compilation = 9,899K
