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count23.tan.rpt
资源名称：count23.rar [点击查看]
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上传日期：2022-08-10
资源大小：285k
文件大小：25k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Classic Timing Analyzer report for count23
- Wed Mar 04 15:53:20 2009
- Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Timing Analyzer Settings
- 4. Clock Settings Summary
- 5. Clock Setup: 'ck'
- 6. tco
- 7. Timing Analyzer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Summary ;
- +------------------------------+-------+---------------+------------------------------------------------+----------+------------+------------+----------+--------------+
- ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
- +------------------------------+-------+---------------+------------------------------------------------+----------+------------+------------+----------+--------------+
- ; Worst-case tco ; N/A ; None ; 6.694 ns ; count[6] ; count23[6] ; ck ; -- ; 0 ;
- ; Clock Setup: 'ck' ; N/A ; None ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[3] ; ck ; ck ; 0 ;
- ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
- +------------------------------+-------+---------------+------------------------------------------------+----------+------------+------------+----------+--------------+
- +---------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Settings ;
- +----------------------------------------------------------------+--------------------+------+----+-------------+
- ; Option ; Setting ; From ; To ; Entity Name ;
- +----------------------------------------------------------------+--------------------+------+----+-------------+
- ; Device Name ; EP2S15F484C3 ; ; ; ;
- ; Timing Models ; Final ; ; ; ;
- ; Default hold multicycle ; Same as Multicycle ; ; ; ;
- ; Cut paths between unrelated clock domains ; On ; ; ; ;
- ; Cut off read during write signal paths ; On ; ; ; ;
- ; Cut off feedback from I/O pins ; On ; ; ; ;
- ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
- ; Ignore Clock Settings ; Off ; ; ; ;
- ; Analyze latches as synchronous elements ; On ; ; ; ;
- ; Enable Recovery/Removal analysis ; Off ; ; ; ;
- ; Enable Clock Latency ; Off ; ; ; ;
- ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
- ; Number of source nodes to report per destination node ; 10 ; ; ; ;
- ; Number of destination nodes to report ; 10 ; ; ; ;
- ; Number of paths to report ; 200 ; ; ; ;
- ; Report Minimum Timing Checks ; Off ; ; ; ;
- ; Use Fast Timing Models ; Off ; ; ; ;
- ; Report IO Paths Separately ; Off ; ; ; ;
- ; Perform Multicorner Analysis ; On ; ; ; ;
- ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
- +----------------------------------------------------------------+--------------------+------+----+-------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Settings Summary ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; ck ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Setup: 'ck' ;
- +-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
- +-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[0] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[6] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[7] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[5] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[4] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[2] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[1] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[2] ; count[3] ; ck ; ck ; None ; None ; 1.338 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[0] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[6] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[7] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[5] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[4] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[2] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[1] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[1] ; count[3] ; ck ; ck ; None ; None ; 1.303 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[0] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[6] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[7] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[5] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[4] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[2] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[1] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[6] ; count[3] ; ck ; ck ; None ; None ; 1.252 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[0] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[6] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[7] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[5] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[4] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[2] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[1] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[7] ; count[3] ; ck ; ck ; None ; None ; 1.218 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[0] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[6] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[7] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[5] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[4] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[2] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[1] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[3] ; count[3] ; ck ; ck ; None ; None ; 1.211 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[0] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[6] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[7] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[5] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[4] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[2] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[1] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[5] ; count[3] ; ck ; ck ; None ; None ; 1.172 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[0] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[6] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[7] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[5] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[4] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[2] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[1] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[4] ; count[3] ; ck ; ck ; None ; None ; 1.054 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[7] ; ck ; ck ; None ; None ; 0.890 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[6] ; ck ; ck ; None ; None ; 0.855 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[5] ; ck ; ck ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[4] ; ck ; ck ; None ; None ; 0.785 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[3] ; ck ; ck ; None ; None ; 0.750 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[2] ; ck ; ck ; None ; None ; 0.715 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[1] ; ck ; ck ; None ; None ; 0.680 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count[0] ; count[0] ; ck ; ck ; None ; None ; 0.609 ns ;
- +-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
- +------------------------------------------------------------------------+
- ; tco ;
- +-------+--------------+------------+----------+------------+------------+
- ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
- +-------+--------------+------------+----------+------------+------------+
- ; N/A ; None ; 6.694 ns ; count[6] ; count23[6] ; ck ;
- ; N/A ; None ; 6.645 ns ; count[4] ; count23[4] ; ck ;
- ; N/A ; None ; 6.638 ns ; count[7] ; count23[7] ; ck ;
- ; N/A ; None ; 6.209 ns ; count[1] ; count23[1] ; ck ;
- ; N/A ; None ; 5.341 ns ; count[0] ; count23[0] ; ck ;
- ; N/A ; None ; 5.207 ns ; count[3] ; count23[3] ; ck ;
- ; N/A ; None ; 5.155 ns ; count[2] ; count23[2] ; ck ;
- ; N/A ; None ; 5.151 ns ; count[5] ; count23[5] ; ck ;
- +-------+--------------+------------+----------+------------+------------+
- +--------------------------+
- ; Timing Analyzer Messages ;
- +--------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Classic Timing Analyzer
- Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
- Info: Processing started: Wed Mar 04 15:53:19 2009
- Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count23 -c count23 --timing_analysis_only
- Warning: Found pins functioning as undefined clocks and/or memory enables
- Info: Assuming node "ck" is an undefined clock
- Info: Clock "ck" Internal fmax is restricted to 500.0 MHz between source register "count[2]" and destination register "count[0]"
- Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
- Info: + Longest register to register delay is 1.338 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y23_N5; Fanout = 4; REG Node = 'count[2]'
- Info: 2: + IC(0.253 ns) + CELL(0.228 ns) = 0.481 ns; Loc. = LCCOMB_X10_Y23_N26; Fanout = 1; COMB Node = 'LessThan0~107'
- Info: 3: + IC(0.195 ns) + CELL(0.053 ns) = 0.729 ns; Loc. = LCCOMB_X10_Y23_N24; Fanout = 8; COMB Node = 'LessThan0~108'
- Info: 4: + IC(0.212 ns) + CELL(0.397 ns) = 1.338 ns; Loc. = LCFF_X10_Y23_N1; Fanout = 3; REG Node = 'count[0]'
- Info: Total cell delay = 0.678 ns ( 50.67 % )
- Info: Total interconnect delay = 0.660 ns ( 49.33 % )
- Info: - Smallest clock skew is 0.000 ns
- Info: + Shortest clock path from clock "ck" to destination register is 2.495 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'ck'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'ck~clkctrl'
- Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X10_Y23_N1; Fanout = 3; REG Node = 'count[0]'
- Info: Total cell delay = 1.472 ns ( 59.00 % )
- Info: Total interconnect delay = 1.023 ns ( 41.00 % )
- Info: - Longest clock path from clock "ck" to source register is 2.495 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'ck'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'ck~clkctrl'
- Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X10_Y23_N5; Fanout = 4; REG Node = 'count[2]'
- Info: Total cell delay = 1.472 ns ( 59.00 % )
- Info: Total interconnect delay = 1.023 ns ( 41.00 % )
- Info: + Micro clock to output delay of source is 0.094 ns
- Info: + Micro setup delay of destination is 0.090 ns
- Info: tco from clock "ck" to destination pin "count23[6]" through register "count[6]" is 6.694 ns
- Info: + Longest clock path from clock "ck" to source register is 2.495 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'ck'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'ck~clkctrl'
- Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X10_Y23_N13; Fanout = 4; REG Node = 'count[6]'
- Info: Total cell delay = 1.472 ns ( 59.00 % )
- Info: Total interconnect delay = 1.023 ns ( 41.00 % )
- Info: + Micro clock to output delay of source is 0.094 ns
- Info: + Longest register to pin delay is 4.105 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y23_N13; Fanout = 4; REG Node = 'count[6]'
- Info: 2: + IC(2.123 ns) + CELL(1.982 ns) = 4.105 ns; Loc. = PIN_Y18; Fanout = 0; PIN Node = 'count23[6]'
- Info: Total cell delay = 1.982 ns ( 48.28 % )
- Info: Total interconnect delay = 2.123 ns ( 51.72 % )
- Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
- Info: Allocated 145 megabytes of memory during processing
- Info: Processing ended: Wed Mar 04 15:53:20 2009
- Info: Elapsed time: 00:00:01
