count23.hier_info
资源名称:count23.rar [点击查看]
上传用户:sh57280931
上传日期:2022-08-10
资源大小:285k
文件大小:1k
源码类别:
VHDL/FPGA/Verilog
开发平台:
VHDL
- |count23
- ck => count[7].CLK
- ck => count[6].CLK
- ck => count[5].CLK
- ck => count[4].CLK
- ck => count[3].CLK
- ck => count[2].CLK
- ck => count[1].CLK
- ck => count[0].CLK
- count23[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
- count23[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
- count23[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
- count23[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
- count23[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
- count23[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
- count23[6] <= count[6].DB_MAX_OUTPUT_PORT_TYPE
- count23[7] <= count[7].DB_MAX_OUTPUT_PORT_TYPE