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count23.sim.rpt
资源名称：count23.rar [点击查看]
上传用户：sh57280931
上传日期：2022-08-10
资源大小：285k
文件大小：12k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Simulator report for count23
- Wed Mar 04 15:48:16 2009
- Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Simulator Summary
- 3. Simulator Settings
- 4. Simulation Waveforms
- 5. Coverage Summary
- 6. Complete 1/0-Value Coverage
- 7. Missing 1-Value Coverage
- 8. Missing 0-Value Coverage
- 9. Simulator INI Usage
- 10. Simulator Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +--------------------------------------------+
- ; Simulator Summary ;
- +-----------------------------+--------------+
- ; Type ; Value ;
- +-----------------------------+--------------+
- ; Simulation Start Time ; 0 ps ;
- ; Simulation End Time ; 1.0 us ;
- ; Simulation Netlist Size ; 28 nodes ;
- ; Simulation Coverage ; 68.57 % ;
- ; Total Number of Transitions ; 1619 ;
- ; Simulation Breakpoints ; 0 ;
- ; Family ; Stratix II ;
- ; Device ; EP2S15F484C3 ;
- +-----------------------------+--------------+
- +--------------------------------------------------------------------------------------------------------------------------+
- ; Simulator Settings ;
- +--------------------------------------------------------------------------------------------+-------------+---------------+
- ; Option ; Setting ; Default Value ;
- +--------------------------------------------------------------------------------------------+-------------+---------------+
- ; Simulation mode ; Timing ; Timing ;
- ; Start time ; 0 ns ; 0 ns ;
- ; Simulation results format ; CVWF ; ;
- ; Vector input source ; count23.vwf ; ;
- ; Add pins automatically to simulation output waveforms ; On ; On ;
- ; Check outputs ; Off ; Off ;
- ; Report simulation coverage ; On ; On ;
- ; Display complete 1/0 value coverage report ; On ; On ;
- ; Display missing 1-value coverage report ; On ; On ;
- ; Display missing 0-value coverage report ; On ; On ;
- ; Detect setup and hold time violations ; Off ; Off ;
- ; Detect glitches ; Off ; Off ;
- ; Disable timing delays in Timing Simulation ; Off ; Off ;
- ; Generate Signal Activity File ; Off ; Off ;
- ; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
- ; Group bus channels in simulation results ; Off ; Off ;
- ; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
- ; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
- ; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
- ; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
- ; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
- +--------------------------------------------------------------------------------------------+-------------+---------------+
- +----------------------+
- ; Simulation Waveforms ;
- +----------------------+
- Waveform report data cannot be output to ASCII.
- Please use Quartus II to view the waveform report data.
- +--------------------------------------------------------------------+
- ; Coverage Summary ;
- +-----------------------------------------------------+--------------+
- ; Type ; Value ;
- +-----------------------------------------------------+--------------+
- ; Total coverage as a percentage ; 68.57 % ;
- ; Total nodes checked ; 28 ;
- ; Total output ports checked ; 35 ;
- ; Total output ports with complete 1/0-value coverage ; 24 ;
- ; Total output ports with no 1/0-value coverage ; 11 ;
- ; Total output ports with no 1-value coverage ; 11 ;
- ; Total output ports with no 0-value coverage ; 11 ;
- +-----------------------------------------------------+--------------+
- The following table displays output ports that toggle between 1 and 0 during simulation.
- +--------------------------------------------------------------------+
- ; Complete 1/0-Value Coverage ;
- +------------------------+------------------------+------------------+
- ; Node Name ; Output Port Name ; Output Port Type ;
- +------------------------+------------------------+------------------+
- ; |count23|count[0] ; |count23|count[0] ; regout ;
- ; |count23|count[1] ; |count23|count[1] ; regout ;
- ; |count23|count[2] ; |count23|count[2] ; regout ;
- ; |count23|count[3] ; |count23|count[3] ; regout ;
- ; |count23|count[4] ; |count23|count[4] ; regout ;
- ; |count23|Add0~121 ; |count23|Add0~121 ; sumout ;
- ; |count23|Add0~121 ; |count23|Add0~122 ; cout ;
- ; |count23|Add0~125 ; |count23|Add0~125 ; sumout ;
- ; |count23|Add0~125 ; |count23|Add0~126 ; cout ;
- ; |count23|Add0~129 ; |count23|Add0~129 ; sumout ;
- ; |count23|Add0~129 ; |count23|Add0~130 ; cout ;
- ; |count23|Add0~133 ; |count23|Add0~133 ; sumout ;
- ; |count23|Add0~133 ; |count23|Add0~134 ; cout ;
- ; |count23|Add0~137 ; |count23|Add0~137 ; sumout ;
- ; |count23|Add0~137 ; |count23|Add0~138 ; cout ;
- ; |count23|LessThan0~107 ; |count23|LessThan0~107 ; combout ;
- ; |count23|LessThan0~108 ; |count23|LessThan0~108 ; combout ;
- ; |count23|count23[0] ; |count23|count23[0] ; padio ;
- ; |count23|count23[1] ; |count23|count23[1] ; padio ;
- ; |count23|count23[2] ; |count23|count23[2] ; padio ;
- ; |count23|count23[3] ; |count23|count23[3] ; padio ;
- ; |count23|count23[4] ; |count23|count23[4] ; padio ;
- ; |count23|ck ; |count23|ck~corein ; combout ;
- ; |count23|ck~clkctrl ; |count23|ck~clkctrl ; outclk ;
- +------------------------+------------------------+------------------+
- The following table displays output ports that do not toggle to 1 during simulation.
- +--------------------------------------------------------------+
- ; Missing 1-Value Coverage ;
- +---------------------+---------------------+------------------+
- ; Node Name ; Output Port Name ; Output Port Type ;
- +---------------------+---------------------+------------------+
- ; |count23|count[5] ; |count23|count[5] ; regout ;
- ; |count23|count[6] ; |count23|count[6] ; regout ;
- ; |count23|count[7] ; |count23|count[7] ; regout ;
- ; |count23|Add0~141 ; |count23|Add0~141 ; sumout ;
- ; |count23|Add0~141 ; |count23|Add0~142 ; cout ;
- ; |count23|Add0~145 ; |count23|Add0~145 ; sumout ;
- ; |count23|Add0~145 ; |count23|Add0~146 ; cout ;
- ; |count23|Add0~149 ; |count23|Add0~149 ; sumout ;
- ; |count23|count23[5] ; |count23|count23[5] ; padio ;
- ; |count23|count23[6] ; |count23|count23[6] ; padio ;
- ; |count23|count23[7] ; |count23|count23[7] ; padio ;
- +---------------------+---------------------+------------------+
- The following table displays output ports that do not toggle to 0 during simulation.
- +--------------------------------------------------------------+
- ; Missing 0-Value Coverage ;
- +---------------------+---------------------+------------------+
- ; Node Name ; Output Port Name ; Output Port Type ;
- +---------------------+---------------------+------------------+
- ; |count23|count[5] ; |count23|count[5] ; regout ;
- ; |count23|count[6] ; |count23|count[6] ; regout ;
- ; |count23|count[7] ; |count23|count[7] ; regout ;
- ; |count23|Add0~141 ; |count23|Add0~141 ; sumout ;
- ; |count23|Add0~141 ; |count23|Add0~142 ; cout ;
- ; |count23|Add0~145 ; |count23|Add0~145 ; sumout ;
- ; |count23|Add0~145 ; |count23|Add0~146 ; cout ;
- ; |count23|Add0~149 ; |count23|Add0~149 ; sumout ;
- ; |count23|count23[5] ; |count23|count23[5] ; padio ;
- ; |count23|count23[6] ; |count23|count23[6] ; padio ;
- ; |count23|count23[7] ; |count23|count23[7] ; padio ;
- +---------------------+---------------------+------------------+
- +---------------------+
- ; Simulator INI Usage ;
- +--------+------------+
- ; Option ; Usage ;
- +--------+------------+
- +--------------------+
- ; Simulator Messages ;
- +--------------------+
- Info: *******************************************************************
- Info: Running Quartus II Simulator
- Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
- Info: Processing started: Wed Mar 04 15:48:14 2009
- Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off count23 -c count23
- Info: Using vector source file "C:/Users/QY/Desktop/VHDL/count23/count23.vwf"
- Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
- Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
- Info: Simulation partitioned into 1 sub-simulations
- Info: Simulation coverage is 68.57 %
- Info: Number of transitions in simulation is 1619
- Info: Quartus II Simulator was successful. 0 errors, 0 warnings
- Info: Allocated 126 megabytes of memory during processing
- Info: Processing ended: Wed Mar 04 15:48:16 2009
- Info: Elapsed time: 00:00:02
