count23.flow.rpt
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VHDL/FPGA/Verilog

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VHDL

  1. Flow report for count23
  2. Wed Mar 04 15:53:20 2009
  3. Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
  4. ---------------------
  5. ; Table of Contents ;
  6. ---------------------
  7.   1. Legal Notice
  8.   2. Flow Summary
  9.   3. Flow Settings
  10.   4. Flow Non-Default Global Settings
  11.   5. Flow Elapsed Time
  12.   6. Flow Log
  13. ----------------
  14. ; Legal Notice ;
  15. ----------------
  16. Copyright (C) 1991-2007 Altera Corporation
  17. Your use of Altera Corporation's design tools, logic functions 
  18. and other software and tools, and its AMPP partner logic 
  19. functions, and any output files from any of the foregoing 
  20. (including device programming or simulation files), and any 
  21. associated documentation or information are expressly subject 
  22. to the terms and conditions of the Altera Program License 
  23. Subscription Agreement, Altera MegaCore Function License 
  24. Agreement, or other applicable license agreement, including, 
  25. without limitation, that your use is for the sole purpose of 
  26. programming logic devices manufactured by Altera and sold by 
  27. Altera or its authorized distributors.  Please refer to the 
  28. applicable agreement for further details.
  29. +--------------------------------------------------------------------------+
  30. ; Flow Summary                                                             ;
  31. +-------------------------------+------------------------------------------+
  32. ; Flow Status                   ; Successful - Wed Mar 04 15:53:20 2009    ;
  33. ; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
  34. ; Revision Name                 ; count23                                  ;
  35. ; Top-level Entity Name         ; count23                                  ;
  36. ; Family                        ; Stratix II                               ;
  37. ; Met timing requirements       ; Yes                                      ;
  38. ; Logic utilization             ; < 1 %                                    ;
  39. ;     Combinational ALUTs       ; 10 / 12,480 ( < 1 % )                    ;
  40. ;     Dedicated logic registers ; 8 / 12,480 ( < 1 % )                     ;
  41. ; Total registers               ; 8                                        ;
  42. ; Total pins                    ; 9 / 343 ( 3 % )                          ;
  43. ; Total virtual pins            ; 0                                        ;
  44. ; Total block memory bits       ; 0 / 419,328 ( 0 % )                      ;
  45. ; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                           ;
  46. ; Total PLLs                    ; 0 / 6 ( 0 % )                            ;
  47. ; Total DLLs                    ; 0 / 2 ( 0 % )                            ;
  48. ; Device                        ; EP2S15F484C3                             ;
  49. ; Timing Models                 ; Final                                    ;
  50. +-------------------------------+------------------------------------------+
  51. +-----------------------------------------+
  52. ; Flow Settings                           ;
  53. +-------------------+---------------------+
  54. ; Option            ; Setting             ;
  55. +-------------------+---------------------+
  56. ; Start date & time ; 03/04/2009 15:53:04 ;
  57. ; Main task         ; Compilation         ;
  58. ; Revision Name     ; count23             ;
  59. +-------------------+---------------------+
  60. +-----------------------------------------------------------------------------------------+
  61. ; Flow Non-Default Global Settings                                                        ;
  62. +------------------------------------+---------+---------------+-------------+------------+
  63. ; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ;
  64. +------------------------------------+---------+---------------+-------------+------------+
  65. ; PARTITION_COLOR                    ; 2147039 ; --            ; --          ; Top        ;
  66. ; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; --          ; Top        ;
  67. ; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ;
  68. +------------------------------------+---------+---------------+-------------+------------+
  69. +------------------------------------------------------------------+
  70. ; Flow Elapsed Time                                                ;
  71. +-------------------------+--------------+-------------------------+
  72. ; Module Name             ; Elapsed Time ; Average Processors Used ;
  73. +-------------------------+--------------+-------------------------+
  74. ; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ;
  75. ; Fitter                  ; 00:00:05     ; 1.0                     ;
  76. ; Assembler               ; 00:00:06     ; 1.0                     ;
  77. ; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ;
  78. ; Total                   ; 00:00:14     ; --                      ;
  79. +-------------------------+--------------+-------------------------+
  80. ------------
  81. ; Flow Log ;
  82. ------------
  83. quartus_map --read_settings_files=on --write_settings_files=off count23 -c count23
  84. quartus_fit --read_settings_files=off --write_settings_files=off count23 -c count23
  85. quartus_asm --read_settings_files=off --write_settings_files=off count23 -c count23
  86. quartus_tan --read_settings_files=off --write_settings_files=off count23 -c count23 --timing_analysis_only