wed.wsf
资源名称:fj.rar [点击查看]
上传用户:whhc027
上传日期:2022-08-10
资源大小:410k
文件大小:5k
源码类别:
VHDL/FPGA/Verilog
开发平台:
VHDL
- /*
- WARNING: Do NOT edit the input and output ports in this file in a text
- editor if you plan to continue editing the block that represents it in
- the Block Editor! File corruption is VERY likely to occur.
- */
- /*
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- */
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- CLOCK{
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- DUTY_CYCLE = 50;
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- FLAG = N;
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- FORMAT = E;
- SCALE = 1;
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- FLAG = N;
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- SIGNAL = "oe";
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- FORMAT = E;
- SCALE = 1;
- VISIBLE = Y;
- FLAG = N;
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- FORMAT = E;
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- FLAG = N;
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- INDEX = 6;
- FORMAT = E;
- SCALE = 1;
- VISIBLE = Y;
- FLAG = N;
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- LINE{
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- FORMAT = E;
- SCALE = 1;
- VISIBLE = Y;
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- FORMAT = E;
- SCALE = 1;
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- FLAG = N;
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- SCALE = 1;
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- FLAG = N;
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