English
fj.map.rpt
资源名称：fj.rar [点击查看]
上传用户：whhc027
上传日期：2022-08-10
资源大小：410k
文件大小：18k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Analysis & Synthesis report for fj
- Thu Mar 05 01:07:54 2009
- Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Analysis & Synthesis Source Files Read
- 5. Analysis & Synthesis Resource Usage Summary
- 6. Analysis & Synthesis Resource Utilization by Entity
- 7. General Register Statistics
- 8. Inverted Register Statistics
- 9. Analysis & Synthesis Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +--------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +-------------------------------+------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Thu Mar 05 01:07:54 2009 ;
- ; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
- ; Revision Name ; fj ;
- ; Top-level Entity Name ; fj ;
- ; Family ; Stratix II ;
- ; Logic utilization ; N/A ;
- ; Combinational ALUTs ; 77 ;
- ; Dedicated logic registers ; 52 ;
- ; Total registers ; 52 ;
- ; Total pins ; 9 ;
- ; Total virtual pins ; 0 ;
- ; Total block memory bits ; 0 ;
- ; DSP block 9-bit elements ; 0 ;
- ; Total PLLs ; 0 ;
- ; Total DLLs ; 0 ;
- +-------------------------------+------------------------------------------+
- +-----------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +-----------------------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +-----------------------------------------------------------------------------+--------------------+--------------------+
- ; Top-level entity name ; fj ; fj ;
- ; Family name ; Stratix II ; Stratix II ;
- ; Use Generated Physical Constraints File ; Off ; ;
- ; Use smart compilation ; Off ; Off ;
- ; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL93 ; VHDL93 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Safe State Machine ; Off ; Off ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Parallel Synthesis ; Off ; Off ;
- ; DSP Block Balancing ; Auto ; Auto ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique -- Stratix II/III/HardCopy II/Stratix II GX/Arria GX ; Balanced ; Balanced ;
- ; Carry Chain Length -- Stratix II/Stratix III ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto Open-Drain Pins ; On ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
- ; Perform gate-level register retiming ; Off ; Off ;
- ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto DSP Block Replacement ; On ; On ;
- ; Auto Shift Register Replacement ; Auto ; Auto ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto RAM Block Balancing ; On ; On ;
- ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; HDL message level ; Level2 ; Level2 ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Clock MUX Protection ; On ; On ;
- ; Block Design Naming ; Auto ; Auto ;
- +-----------------------------------------------------------------------------+--------------------+--------------------+
- +---------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +----------------------------------+-----------------+-----------------+----------------------------------------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
- +----------------------------------+-----------------+-----------------+----------------------------------------+
- ; fj.vhd ; yes ; User VHDL File ; C:/Users/QY/Desktop/06124317/fj/fj.vhd ;
- +----------------------------------+-----------------+-----------------+----------------------------------------+
- +-------------------------------------------------------+
- ; Analysis & Synthesis Resource Usage Summary ;
- +-----------------------------------------------+-------+
- ; Resource ; Usage ;
- +-----------------------------------------------+-------+
- ; Estimated ALUTs Used ; 77 ;
- ; Dedicated logic registers ; 52 ;
- ; ; ;
- ; Estimated ALUTs Unavailable ; 7 ;
- ; ; ;
- ; Total combinational functions ; 77 ;
- ; Combinational ALUT usage by number of inputs ; ;
- ; -- 7 input functions ; 0 ;
- ; -- 6 input functions ; 2 ;
- ; -- 5 input functions ; 10 ;
- ; -- 4 input functions ; 4 ;
- ; -- <=3 input functions ; 61 ;
- ; ; ;
- ; Combinational ALUTs by mode ; ;
- ; -- normal mode ; 33 ;
- ; -- extended LUT mode ; 0 ;
- ; -- arithmetic mode ; 44 ;
- ; -- shared arithmetic mode ; 0 ;
- ; ; ;
- ; Estimated ALUT/register pairs used ; 84 ;
- ; ; ;
- ; Total registers ; 52 ;
- ; -- Dedicated logic registers ; 52 ;
- ; -- I/O registers ; 0 ;
- ; ; ;
- ; Estimated ALMs: partially or completely used ; 42 ;
- ; ; ;
- ; I/O pins ; 9 ;
- ; Maximum fan-out node ; clk ;
- ; Maximum fan-out ; 42 ;
- ; Total fan-out ; 340 ;
- ; Average fan-out ; 2.46 ;
- +-----------------------------------------------+-------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Utilization by Entity ;
- +----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
- ; |fj ; 77 (77) ; 52 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |fj ; work ;
- +----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +------------------------------------------------------+
- ; General Register Statistics ;
- +----------------------------------------------+-------+
- ; Statistic ; Value ;
- +----------------------------------------------+-------+
- ; Total registers ; 52 ;
- ; Number of registers using Synchronous Clear ; 32 ;
- ; Number of registers using Synchronous Load ; 0 ;
- ; Number of registers using Asynchronous Clear ; 0 ;
- ; Number of registers using Asynchronous Load ; 0 ;
- ; Number of registers using Clock Enable ; 0 ;
- ; Number of registers using Preset ; 0 ;
- +----------------------------------------------+-------+
- +--------------------------------------------------+
- ; Inverted Register Statistics ;
- +----------------------------------------+---------+
- ; Inverted Register ; Fan out ;
- +----------------------------------------+---------+
- ; cv1[10] ; 2 ;
- ; cv1[11] ; 3 ;
- ; cv1[8] ; 3 ;
- ; cv1[5] ; 3 ;
- ; cv1[6] ; 3 ;
- ; cv1[7] ; 3 ;
- ; cv1[3] ; 2 ;
- ; Total number of inverted registers = 7 ; ;
- +----------------------------------------+---------+
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Analysis & Synthesis
- Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
- Info: Processing started: Thu Mar 05 01:07:51 2009
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fj -c fj
- Info: Found 2 design units, including 1 entities, in source file fj.vhd
- Info: Found design unit 1: fj-a
- Info: Found entity 1: fj
- Info: Found 1 design units, including 1 entities, in source file Block1.bdf
- Info: Found entity 1: Block1
- Info: Elaborating entity "fj" for the top level hierarchy
- Info: Implemented 87 device resources after synthesis - the final resource count might be different
- Info: Implemented 2 input pins
- Info: Implemented 7 output pins
- Info: Implemented 78 logic cells
- Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Allocated 180 megabytes of memory during processing
- Info: Processing ended: Thu Mar 05 01:07:54 2009
- Info: Elapsed time: 00:00:03
