VHDL/FPGA/Verilog

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VHDL

fj.fit.rpt：源码内容

; U6 ; 179 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U7 ; 180 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U8 ; 173 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U9 ; 171 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U10 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U11 ; ; ; VCCD_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; U12 ; 130 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U13 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U14 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U15 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U16 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; U17 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; U18 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; U19 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; U20 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; U21 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; U22 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V1 ; 203 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V2 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V3 ; 198 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V4 ; 196 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V5 ; 188 ; 7 ; ^PORSEL ; ; ; ; -- ; ; -- ; -- ;
; V6 ; 185 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V7 ; 175 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V8 ; 166 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V9 ; 149 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V10 ; 165 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V11 ; 132 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V12 ; 134 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V13 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V14 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V15 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V16 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; V17 ; 90 ; 8 ; ^VCCSEL ; ; ; ; -- ; ; -- ; -- ;
; V18 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V19 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;
; V21 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; V22 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W1 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W2 ; 197 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W3 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W4 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W5 ; 182 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W6 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;
; W7 ; 177 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W8 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;
; W9 ; 148 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W10 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W11 ; 133 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W12 ; 135 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W13 ; 128 ; 8 ; fmc ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; W14 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W15 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W16 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W17 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; W18 ; 88 ; 8 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; W19 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W20 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W21 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; W22 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; Y1 ; 195 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; Y2 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; Y3 ; 184 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y4 ; 189 ; 7 ; PLL_ENA ; ; ; ; -- ; ; -- ; -- ;
; Y5 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y6 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y7 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y8 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y9 ; 146 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y10 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y11 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y12 ; 136 ; 8 ; sv ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; Y13 ; 131 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y14 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y15 ; 126 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y16 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y17 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y18 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y19 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;
; Y20 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; Y21 ; 82 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; Y22 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+-------------------------------------------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+----------------------------------+-------+------------------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+----------------------------------+-------+------------------------------------+
; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
; LVDS ; 0 pF ; 100 Ohm (Differential) ;
; HyperTransport ; 0 pF ; 100 Ohm (Differential) ;
; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
; 3.3-V LVTTL ; 0 pF ; Not Available ;
; 3.3-V LVCMOS ; 0 pF ; Not Available ;
; 2.5 V ; 0 pF ; Not Available ;
; 1.8 V ; 0 pF ; Not Available ;
; 1.5 V ; 0 pF ; Not Available ;
; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
; 1.2-V HSTL ; 0 pF ; Not Available ;
; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
; Differential 1.2-V HSTL ; 0 pF ; Not Available ;
+----------------------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+---------------------+---------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; ALMs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Combinational with no register ; Register-Only ; Combinational with a register ; Full Hierarchy Name ; Library Name ;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ALUT/register pair ; ALUT/register pair ; ALUT/register pair ; ; ;
+----------------------------+---------------------+---------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------+--------------+
; |fj ; 78 (78) ; 40 (40) ; 52 (52) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; 25 (25) ; 0 (0) ; 52 (52) ; |fj ; work ;
+----------------------------+---------------------+---------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; DQS bus ; NDQS bus ; DQS output ;
+------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+
; fmc ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; fmc1 ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; sh ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; ah ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; sv ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; av ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; oe ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; clk ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; s ; Input ; 7 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
+------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+
+---------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; clk ; ; ;
; s ; ; ;
; - sv1 ; 1 ; 0 ;
; - cs0[0] ; 0 ; 7 ;
; - cs0[1] ; 0 ; 7 ;
; - cs0[2] ; 0 ; 7 ;
; - cs0[3] ; 0 ; 7 ;
; - cs0[4] ; 0 ; 7 ;
; - cs0[6] ; 0 ; 7 ;
; - cs0[7] ; 0 ; 7 ;
; - cs0[5] ; 0 ; 7 ;
; - process0~0 ; 0 ; 7 ;
+---------------------+-------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+--------------+-------------------+---------+--------------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------+-------------------+---------+--------------------+--------+----------------------+------------------+---------------------------+
; LessThan1~82 ; LCCOMB_X15_Y9_N22 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;
; clk ; PIN_N20 ; 42 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
; fmcb ; LCFF_X15_Y9_N29 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ;
; process6~173 ; LCCOMB_X13_Y9_N24 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;
; s ; PIN_M21 ; 11 ; Clock, Sync. clear ; no ; -- ; -- ; -- ;
; s ; PIN_M21 ; 8 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ;
; sv1 ; LCFF_X13_Y9_N23 ; 4 ; Clock ; no ; -- ; -- ; -- ;
+--------------+-------------------+---------+--------------------+--------+----------------------+------------------+---------------------------+
+-------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------+----------+---------+----------------------+------------------+---------------------------+
; clk ; PIN_N20 ; 42 ; Global Clock ; GCLK3 ; -- ;
; s ; PIN_M21 ; 8 ; Global Clock ; GCLK1 ; -- ;
+------+----------+---------+----------------------+------------------+---------------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+--------------+------------------+
; Name ; Fan-Out ;
+--------------+------------------+
; fmcc~0 ; 13 ;
; s ; 10 ;
; fmcb ; 9 ;
; process6~173 ; 8 ;
; LessThan1~82 ; 8 ;
; sv1 ; 4 ;
; cf1[4] ; 4 ;
; cf1[1] ; 4 ;
; cv1[7] ; 3 ;
; cv1[9] ; 3 ;
; cv1[4] ; 3 ;
; cv1[6] ; 3 ;
; cv1[5] ; 3 ;
; cv1[8] ; 3 ;
; cv1[11] ; 3 ;
; LessThan1~80 ; 3 ;
; csh1[7] ; 3 ;
; csh1[2] ; 3 ;
; csh1[1] ; 3 ;
; csh1[3] ; 3 ;
; csh1[4] ; 3 ;
; cs1[5] ; 3 ;
; cs1[7] ; 3 ;
; cs1[4] ; 3 ;
; cs1[6] ; 3 ;
; cs1[1] ; 3 ;
; cs1[3] ; 3 ;
; cs1[2] ; 3 ;
; cf1[7] ; 3 ;
; cf1[2] ; 3 ;
; cf1[0] ; 3 ;
; cf1[3] ; 3 ;
; cv1[1] ; 2 ;
; cv1[3] ; 2 ;
; cv1[2] ; 2 ;
; cv1[0] ; 2 ;
; cv1[10] ; 2 ;
; process3~166 ; 2 ;
; process2~29 ; 2 ;
; ah1 ; 2 ;
; cs0[4] ; 2 ;
; cs0[0] ; 2 ;
; cs0[3] ; 2 ;
; cs0[5] ; 2 ;
; cs0[7] ; 2 ;
; cs0[6] ; 2 ;
; cs0[2] ; 2 ;
; cs0[1] ; 2 ;
; csh1[5] ; 2 ;
; csh1[6] ; 2 ;
+--------------+------------------+
+-------------------------------------------------------------------+
; Interconnect Usage Summary ;
+-------------------------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+-------------------------------------------+-----------------------+
; Block interconnects ; 63 / 51,960 ( < 1 % ) ;
; C16 interconnects ; 0 / 1,680 ( 0 % ) ;
; C4 interconnects ; 20 / 38,400 ( < 1 % ) ;
; DPA clocks ; 0 / 4 ( 0 % ) ;
; DQS bus muxes ; 0 / 18 ( 0 % ) ;
; DQS-18 I/O buses ; 0 / 4 ( 0 % ) ;
; DQS-4 I/O buses ; 0 / 18 ( 0 % ) ;
; DQS-9 I/O buses ; 0 / 8 ( 0 % ) ;
; Differential I/O clocks ; 0 / 32 ( 0 % ) ;
; Direct links ; 42 / 51,960 ( < 1 % ) ;
; Global clocks ; 2 / 16 ( 13 % ) ;
; Local interconnects ; 38 / 12,480 ( < 1 % ) ;
; NDQS bus muxes ; 0 / 18 ( 0 % ) ;
; NDQS-18 I/O buses ; 0 / 4 ( 0 % ) ;
; NDQS-4 I/O buses ; 0 / 18 ( 0 % ) ;
; NDQS-9 I/O buses ; 0 / 8 ( 0 % ) ;
; PLL transmitter or receiver load enables ; 0 / 8 ( 0 % ) ;
; PLL transmitter or receiver synch. clocks ; 0 / 8 ( 0 % ) ;
; R24 interconnects ; 2 / 1,664 ( < 1 % ) ;
; R24/C16 interconnect drivers ; 0 / 4,160 ( 0 % ) ;
; R4 interconnects ; 34 / 59,488 ( < 1 % ) ;
; Regional clocks ; 0 / 32 ( 0 % ) ;
+-------------------------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 6.67) ; Number of LABs (Total = 6) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 4 ;
; 8 ; 1 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 6) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 4 ;
; 1 Sync. clear ; 2 ;
; 2 Clocks ; 2 ;
+------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 14.17) ; Number of LABs (Total = 6) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 23 ; 0 ;
; 24 ; 0 ;
; 25 ; 0 ;
; 26 ; 0 ;
; 27 ; 0 ;
; 28 ; 0 ;
; 29 ; 1 ;
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.17) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 8.00) ; Number of LABs (Total = 6) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 1 ;
+---------------------------------------------+-----------------------------+
+------------------------------------------+
; I/O Rules Summary ;
+----------------------------------+-------+
; I/O Rules Statistic ; Total ;
+----------------------------------+-------+
; Total I/O Rules ; 31 ;
; Number of I/O Rules Passed ; 4 ;
; Number of I/O Rules Failed ; 0 ;
; Number of I/O Rules Unchecked ; 0 ;
; Number of I/O Rules Inapplicable ; 27 ;
+----------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details ;
+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000032 ; I/O Properties Checks for Multiple I/Os ; I/O registers and SERDES should not be used at the same XY location. ; Critical ; No I/O Registers or Differential I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 1 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000037 ; SI Related Distance Checks ; Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000038 ; SI Related SSO Limit Checks ; Single-ended outputs and High-speed LVDS should not coexist in an I/O bank. ; High ; No High-speed LVDS found. ; I/O ; ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000040 ; SI Related SSO Limit Checks ; The total drive strength of single ended outputs in a DPA bank should not exceed 120mA. ; High ; No DPA found. ; I/O ; ;
+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000032 ; IO_000033 ; IO_000034 ; IO_000037 ; IO_000038 ; IO_000042 ; IO_000040 ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 9 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 9 ; 9 ; 9 ; 9 ; 9 ; 0 ; 9 ; 9 ; 0 ; 0 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 9 ; 0 ; 9 ; 9 ; 9 ; 9 ; 9 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; fmc ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; fmc1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; sh ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; ah ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; sv ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; av ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; oe ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; s ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Error detection CRC ; Off ;
; nWS, nRS, nCS, CS ; Unreserved ;
; RDYnBUSY ; Unreserved ;
; Data[7..1] ; Unreserved ;
; Data[0] ; As input tri-stated ;
; ASDO,nCSO ; Unreserved ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------------------------+
; Operating Settings and Conditions ;
+---------------------------+--------+
; Setting ; Value ;
+---------------------------+--------+
; Nominal Core Voltage ; 1.20 V ;
; Low Junction Temperature ; 0 癈 ;
; High Junction Temperature ; 85 癈 ;
+---------------------------+--------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+----------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------+-------------+
; Name ; Value ;
+--------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -3654 ;
; Internal Atom Count - Fit Attempt 1 ; 130 ;
; LE/ALM Count - Fit Attempt 1 ; 41 ;
; LAB Count - Fit Attempt 1 ; 7 ;
; Outputs per Lab - Fit Attempt 1 ; 6.143 ;
; Inputs per LAB - Fit Attempt 1 ; 6.000 ;
; Global Inputs per LAB - Fit Attempt 1 ; 1.143 ;
; LAB Constraint 'CE + async load' - Fit Attempt 1 ; 0:7 ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:5;1:2 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:3;1:2;2:2 ;
; LAB Constraint 'deterministic LABSMUXA/LABSMUXB overuse' - Fit Attempt 1 ; 0:5;1:2 ;
; LAB Constraint 'deterministic LABSMUXE/LABSMUXF overuse' - Fit Attempt 1 ; 0:3;1:4 ;
; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:1;1:4;2:2 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:7 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:2;2:4 ;
; LAB Constraint 'clock constraint' - Fit Attempt 1 ; 0:1;1:2;2:4 ;
; LAB Constraint 'carry chain tie-off constraint' - Fit Attempt 1 ; 0:2;1:4;2:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:7 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:1;1:6 ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2;1:5 ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:3;1:4 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:7 ;
; LEs in Chains - Fit Attempt 1 ; 44 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 5 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.003 ;
+--------------------------------------------------------------------------+-------------+
+---------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; -4373 ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -2194 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Late Slack - Fit Attempt 1 ; -2194 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.010 ;
+-------------------------------------+-------+
+---------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1 ; -1584 ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -1654 ;
; Late Slack - Fit Attempt 1 ; -1654 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.025 ;
+-------------------------------------+-------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Mar 05 01:07:55 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fj -c fj
Info: Automatically selected device EP2S15F484C3 for design fj
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
Info: Previous placement does not exist for 138 of 138 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2S30F484C3 is compatible
Info: Device EP2S60F484C3 is compatible
Info: Device EP2S60F484C3ES is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
Info: Pin ~DATA0~ is reserved at location E13
Warning: No exact pin location assignment(s) for 9 pins of 9 total pins
Info: Pin fmc not assigned to an exact location on the device
Info: Pin fmc1 not assigned to an exact location on the device
Info: Pin sh not assigned to an exact location on the device
Info: Pin ah not assigned to an exact location on the device
Info: Pin sv not assigned to an exact location on the device
Info: Pin av not assigned to an exact location on the device
Info: Pin oe not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin s not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Automatically promoted node clk (placed in PIN N20 (CLK3p, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node s (placed in PIN M21 (CLK1p, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node sv1
Info: Destination node cs0[0]
Info: Destination node cs0[1]
Info: Destination node cs0[2]
Info: Destination node cs0[3]
Info: Destination node cs0[4]
Info: Destination node cs0[6]
Info: Destination node cs0[7]
Info: Destination node cs0[5]
Info: Destination node process0~0
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 0 input, 7 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins available
Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available
Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available
Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available
Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available
Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 1.761 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y14; Fanout = 3; REG Node = 'cv1[0]'
Info: 2: + IC(0.225 ns) + CELL(0.350 ns) = 0.575 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~182'
Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.610 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~186'
Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.645 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~190'
Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.680 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~194'
Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.715 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~198'
Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.750 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~202'
Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 0.785 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~206'
Info: 9: + IC(0.000 ns) + CELL(0.035 ns) = 0.820 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~210'
Info: 10: + IC(0.061 ns) + CELL(0.035 ns) = 0.916 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~214'
Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 0.951 ns; Loc. = LAB_X22_Y14; Fanout = 2; COMB Node = 'Add4~218'
Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 0.986 ns; Loc. = LAB_X22_Y14; Fanout = 1; COMB Node = 'Add4~222'
Info: 13: + IC(0.000 ns) + CELL(0.125 ns) = 1.111 ns; Loc. = LAB_X22_Y14; Fanout = 1; COMB Node = 'Add4~225'
Info: 14: + IC(0.117 ns) + CELL(0.378 ns) = 1.606 ns; Loc. = LAB_X21_Y14; Fanout = 1; COMB Node = 'cv1~339'
Info: 15: + IC(0.000 ns) + CELL(0.155 ns) = 1.761 ns; Loc. = LAB_X21_Y14; Fanout = 3; REG Node = 'cv1[11]'
Info: Total cell delay = 1.358 ns ( 77.12 % )
Info: Total interconnect delay = 0.403 ns ( 22.88 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 7 output pins without output pin load capacitance assignment
Info: Pin "fmc" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fmc1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sh" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ah" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sv" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "av" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "oe" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file C:/Users/QY/Desktop/06124317/fj/fj.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 5 warnings
Info: Allocated 216 megabytes of memory during processing
Info: Processing ended: Thu Mar 05 01:08:01 2009
Info: Elapsed time: 00:00:06
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Users/QY/Desktop/06124317/fj/fj.fit.smsg.