English
fj.tan.rpt
资源名称：fj.rar [点击查看]
上传用户：whhc027
上传日期：2022-08-10
资源大小：410k
文件大小：80k
源码类别：
VHDL/FPGA/Verilog
开发平台：
VHDL
- Classic Timing Analyzer report for fj
- Thu Mar 05 01:08:10 2009
- Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Timing Analyzer Settings
- 4. Clock Settings Summary
- 5. Clock Setup: 'clk'
- 6. Clock Setup: 's'
- 7. tsu
- 8. tco
- 9. th
- 10. Timing Analyzer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +--------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Summary ;
- +------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
- ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
- +------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
- ; Worst-case tsu ; N/A ; None ; 3.730 ns ; s ; fmca ; -- ; clk ; 0 ;
- ; Worst-case tco ; N/A ; None ; 8.813 ns ; sv1 ; fmc1 ; s ; -- ; 0 ;
- ; Worst-case th ; N/A ; None ; -3.048 ns ; s ; cs0[5] ; -- ; clk ; 0 ;
- ; Clock Setup: 'clk' ; N/A ; None ; 351.62 MHz ( period = 2.844 ns ) ; cf1[0] ; fmcb ; clk ; clk ; 0 ;
- ; Clock Setup: 's' ; N/A ; None ; 492.37 MHz ( period = 2.031 ns ) ; cs1[2] ; cs1[7] ; s ; s ; 0 ;
- ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
- +------------------------------+-------+---------------+----------------------------------+--------+--------+------------+----------+--------------+
- +---------------------------------------------------------------------------------------------------------------+
- ; Timing Analyzer Settings ;
- +----------------------------------------------------------------+--------------------+------+----+-------------+
- ; Option ; Setting ; From ; To ; Entity Name ;
- +----------------------------------------------------------------+--------------------+------+----+-------------+
- ; Device Name ; EP2S15F484C3 ; ; ; ;
- ; Timing Models ; Final ; ; ; ;
- ; Default hold multicycle ; Same as Multicycle ; ; ; ;
- ; Cut paths between unrelated clock domains ; On ; ; ; ;
- ; Cut off read during write signal paths ; On ; ; ; ;
- ; Cut off feedback from I/O pins ; On ; ; ; ;
- ; Report Combined Fast/Slow Timing ; Off ; ; ; ;
- ; Ignore Clock Settings ; Off ; ; ; ;
- ; Analyze latches as synchronous elements ; On ; ; ; ;
- ; Enable Recovery/Removal analysis ; Off ; ; ; ;
- ; Enable Clock Latency ; Off ; ; ; ;
- ; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
- ; Number of source nodes to report per destination node ; 10 ; ; ; ;
- ; Number of destination nodes to report ; 10 ; ; ; ;
- ; Number of paths to report ; 200 ; ; ; ;
- ; Report Minimum Timing Checks ; Off ; ; ; ;
- ; Use Fast Timing Models ; Off ; ; ; ;
- ; Report IO Paths Separately ; Off ; ; ; ;
- ; Perform Multicorner Analysis ; On ; ; ; ;
- ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
- +----------------------------------------------------------------+--------------------+------+----+-------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Settings Summary ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- ; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
- ; s ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
- +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Setup: 'clk' ;
- +-----------------------------------------+-----------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
- +-----------------------------------------+-----------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; N/A ; 351.62 MHz ( period = 2.844 ns ) ; cf1[0] ; fmcb ; clk ; clk ; None ; None ; 1.238 ns ;
- ; N/A ; 358.68 MHz ( period = 2.788 ns ) ; cf1[7] ; fmcb ; clk ; clk ; None ; None ; 1.210 ns ;
- ; N/A ; 392.16 MHz ( period = 2.550 ns ) ; cf1[3] ; fmcb ; clk ; clk ; None ; None ; 1.091 ns ;
- ; N/A ; 437.83 MHz ( period = 2.284 ns ) ; cf1[5] ; fmcb ; clk ; clk ; None ; None ; 0.958 ns ;
- ; N/A ; 459.14 MHz ( period = 2.178 ns ) ; cf1[2] ; fmcb ; clk ; clk ; None ; None ; 0.905 ns ;
- ; N/A ; 466.20 MHz ( period = 2.145 ns ) ; cv1[0] ; cv1[9] ; clk ; clk ; None ; None ; 1.961 ns ;
- ; N/A ; 473.48 MHz ( period = 2.112 ns ) ; cv1[2] ; cv1[9] ; clk ; clk ; None ; None ; 1.928 ns ;
- ; N/A ; 476.19 MHz ( period = 2.100 ns ) ; cv1[1] ; cv1[9] ; clk ; clk ; None ; None ; 1.916 ns ;
- ; N/A ; 483.56 MHz ( period = 2.068 ns ) ; sv11 ; cv1[3] ; clk ; clk ; None ; None ; 0.850 ns ;
- ; N/A ; 484.03 MHz ( period = 2.066 ns ) ; sv11 ; cv1[9] ; clk ; clk ; None ; None ; 0.849 ns ;
- ; N/A ; 484.50 MHz ( period = 2.064 ns ) ; sv11 ; cv1[2] ; clk ; clk ; None ; None ; 0.848 ns ;
- ; N/A ; 484.97 MHz ( period = 2.062 ns ) ; sv11 ; cv1[4] ; clk ; clk ; None ; None ; 0.847 ns ;
- ; N/A ; 484.97 MHz ( period = 2.062 ns ) ; sv11 ; cv1[7] ; clk ; clk ; None ; None ; 0.847 ns ;
- ; N/A ; 485.44 MHz ( period = 2.060 ns ) ; sv11 ; cv1[0] ; clk ; clk ; None ; None ; 0.846 ns ;
- ; N/A ; 485.91 MHz ( period = 2.058 ns ) ; cv1[0] ; cv1[11] ; clk ; clk ; None ; None ; 1.874 ns ;
- ; N/A ; 486.14 MHz ( period = 2.057 ns ) ; cv1[0] ; cv1[10] ; clk ; clk ; None ; None ; 1.873 ns ;
- ; N/A ; 486.38 MHz ( period = 2.056 ns ) ; cf1[6] ; fmcb ; clk ; clk ; None ; None ; 0.844 ns ;
- ; N/A ; 486.38 MHz ( period = 2.056 ns ) ; sv11 ; cv1[6] ; clk ; clk ; None ; None ; 0.844 ns ;
- ; N/A ; 486.85 MHz ( period = 2.054 ns ) ; sv11 ; cv1[5] ; clk ; clk ; None ; None ; 0.843 ns ;
- ; N/A ; 487.80 MHz ( period = 2.050 ns ) ; cv1[4] ; cv1[9] ; clk ; clk ; None ; None ; 1.866 ns ;
- ; N/A ; 489.72 MHz ( period = 2.042 ns ) ; sv11 ; cv1[11] ; clk ; clk ; None ; None ; 0.837 ns ;
- ; N/A ; 490.68 MHz ( period = 2.038 ns ) ; sv11 ; cv1[1] ; clk ; clk ; None ; None ; 0.835 ns ;
- ; N/A ; 490.68 MHz ( period = 2.038 ns ) ; sv11 ; cv1[8] ; clk ; clk ; None ; None ; 0.835 ns ;
- ; N/A ; 491.64 MHz ( period = 2.034 ns ) ; sv11 ; cv1[10] ; clk ; clk ; None ; None ; 0.833 ns ;
- ; N/A ; 492.37 MHz ( period = 2.031 ns ) ; cv1[3] ; cv1[9] ; clk ; clk ; None ; None ; 1.847 ns ;
- ; N/A ; 493.83 MHz ( period = 2.025 ns ) ; cv1[2] ; cv1[11] ; clk ; clk ; None ; None ; 1.841 ns ;
- ; N/A ; 494.07 MHz ( period = 2.024 ns ) ; cv1[2] ; cv1[10] ; clk ; clk ; None ; None ; 1.840 ns ;
- ; N/A ; 494.56 MHz ( period = 2.022 ns ) ; cv1[0] ; cv1[7] ; clk ; clk ; None ; None ; 1.838 ns ;
- ; N/A ; 496.77 MHz ( period = 2.013 ns ) ; cv1[1] ; cv1[11] ; clk ; clk ; None ; None ; 1.829 ns ;
- ; N/A ; 497.02 MHz ( period = 2.012 ns ) ; cv1[1] ; cv1[10] ; clk ; clk ; None ; None ; 1.828 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[8] ; clk ; clk ; None ; None ; 1.806 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[7] ; clk ; clk ; None ; None ; 1.805 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; fmcb ; clk ; clk ; None ; None ; 0.805 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[7] ; clk ; clk ; None ; None ; 1.793 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[9] ; clk ; clk ; None ; None ; 1.779 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[11] ; clk ; clk ; None ; None ; 1.779 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[10] ; clk ; clk ; None ; None ; 1.778 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[8] ; clk ; clk ; None ; None ; 1.773 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[8] ; clk ; clk ; None ; None ; 1.761 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[11] ; clk ; clk ; None ; None ; 1.760 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[10] ; clk ; clk ; None ; None ; 1.759 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; cv1[9] ; clk ; clk ; None ; None ; 1.746 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[7] ; clk ; clk ; None ; None ; 1.743 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[7] ; cv1[9] ; clk ; clk ; None ; None ; 1.728 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[7] ; clk ; clk ; None ; None ; 1.724 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[8] ; clk ; clk ; None ; None ; 1.711 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; fmca ; fmcb ; clk ; clk ; None ; None ; 0.754 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[8] ; clk ; clk ; None ; None ; 1.692 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[11] ; clk ; clk ; None ; None ; 1.692 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[10] ; clk ; clk ; None ; None ; 1.691 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[3] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[7] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[0] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[4] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[2] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[5] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[6] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; cf1[1] ; clk ; clk ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; cv1[11] ; clk ; clk ; None ; None ; 1.659 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; cv1[10] ; clk ; clk ; None ; None ; 1.658 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[7] ; clk ; clk ; None ; None ; 1.656 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[7] ; cv1[11] ; clk ; clk ; None ; None ; 1.641 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[7] ; cv1[10] ; clk ; clk ; None ; None ; 1.640 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[5] ; clk ; clk ; None ; None ; 1.639 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[6] ; clk ; clk ; None ; None ; 1.632 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; av1 ; clk ; clk ; None ; None ; 1.633 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[8] ; clk ; clk ; None ; None ; 1.624 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; cv1[7] ; clk ; clk ; None ; None ; 1.623 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[8] ; cv1[9] ; clk ; clk ; None ; None ; 1.614 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[7] ; cv1[7] ; clk ; clk ; None ; None ; 1.610 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[5] ; clk ; clk ; None ; None ; 1.606 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[4] ; clk ; clk ; None ; None ; 1.600 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[6] ; clk ; clk ; None ; None ; 1.599 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; av1 ; clk ; clk ; None ; None ; 1.601 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[5] ; clk ; clk ; None ; None ; 1.594 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; cv1[8] ; clk ; clk ; None ; None ; 1.591 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[6] ; clk ; clk ; None ; None ; 1.587 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[7] ; cv1[8] ; clk ; clk ; None ; None ; 1.573 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[4] ; clk ; clk ; None ; None ; 1.567 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[3] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[7] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[0] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[4] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[2] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[5] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[6] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; cf1[1] ; clk ; clk ; None ; None ; 1.558 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[4] ; clk ; clk ; None ; None ; 1.555 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[5] ; clk ; clk ; None ; None ; 1.544 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[9] ; cv1[9] ; clk ; clk ; None ; None ; 1.540 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[6] ; clk ; clk ; None ; None ; 1.537 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[3] ; clk ; clk ; None ; None ; 1.535 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[2] ; clk ; clk ; None ; None ; 1.529 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[8] ; cv1[11] ; clk ; clk ; None ; None ; 1.527 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[8] ; cv1[10] ; clk ; clk ; None ; None ; 1.526 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[5] ; clk ; clk ; None ; None ; 1.525 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[6] ; clk ; clk ; None ; None ; 1.518 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[3] ; clk ; clk ; None ; None ; 1.502 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[10] ; cv1[11] ; clk ; clk ; None ; None ; 1.499 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[3] ; clk ; clk ; None ; None ; 1.490 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[4] ; clk ; clk ; None ; None ; 1.486 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[2] ; clk ; clk ; None ; None ; 1.484 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[4] ; cv1[4] ; clk ; clk ; None ; None ; 1.483 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[9] ; cv1[11] ; clk ; clk ; None ; None ; 1.481 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[9] ; cv1[10] ; clk ; clk ; None ; None ; 1.480 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[10] ; cv1[10] ; clk ; clk ; None ; None ; 1.476 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; cv1[2] ; clk ; clk ; None ; None ; 1.474 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[1] ; clk ; clk ; None ; None ; 1.460 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[6] ; clk ; clk ; None ; None ; 1.450 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[7] ; av1 ; clk ; clk ; None ; None ; 1.440 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[8] ; cv1[8] ; clk ; clk ; None ; None ; 1.431 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; cv1[5] ; clk ; clk ; None ; None ; 1.429 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; fmcb ; clk ; clk ; None ; None ; 0.619 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[5] ; av1 ; clk ; clk ; None ; None ; 1.416 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; cv1[0] ; clk ; clk ; None ; None ; 1.406 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[9] ; av1 ; clk ; clk ; None ; None ; 1.409 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[11] ; cv1[11] ; clk ; clk ; None ; None ; 1.396 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; cv1[3] ; clk ; clk ; None ; None ; 1.393 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[6] ; cv1[6] ; clk ; clk ; None ; None ; 1.389 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; cv1[1] ; clk ; clk ; None ; None ; 1.387 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[3] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[7] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[0] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[4] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[2] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[5] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[6] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[2] ; cf1[1] ; clk ; clk ; None ; None ; 1.352 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[3] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[7] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[0] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[4] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[2] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[5] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[6] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; cf1[1] ; clk ; clk ; None ; None ; 1.346 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[3] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[7] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[0] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[4] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[2] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[5] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[6] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; cf1[1] ; clk ; clk ; None ; None ; 1.344 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[11] ; av1 ; clk ; clk ; None ; None ; 1.292 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[3] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[7] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[0] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[4] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[2] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[5] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[6] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; cf1[1] ; clk ; clk ; None ; None ; 1.236 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[3] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[7] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[0] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[4] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[2] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[5] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[6] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; cf1[1] ; clk ; clk ; None ; None ; 1.213 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[3] ; av1 ; clk ; clk ; None ; None ; 1.191 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[3] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[7] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[0] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[4] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[2] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[5] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[6] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[4] ; cf1[1] ; clk ; clk ; None ; None ; 1.181 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[5] ; fmca ; clk ; clk ; None ; None ; 1.170 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[8] ; av1 ; clk ; clk ; None ; None ; 1.171 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[2] ; av1 ; clk ; clk ; None ; None ; 1.161 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[6] ; fmca ; clk ; clk ; None ; None ; 1.056 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[0] ; fmca ; clk ; clk ; None ; None ; 1.025 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[7] ; fmca ; clk ; clk ; None ; None ; 0.997 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[0] ; av1 ; clk ; clk ; None ; None ; 0.951 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[1] ; fmca ; clk ; clk ; None ; None ; 0.921 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs0[0] ; cs0[7] ; clk ; clk ; None ; None ; 0.890 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[0] ; csh1[7] ; clk ; clk ; None ; None ; 0.890 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[10] ; av1 ; clk ; clk ; None ; None ; 0.887 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cf1[3] ; fmca ; clk ; clk ; None ; None ; 0.878 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[6] ; sh1 ; clk ; clk ; None ; None ; 0.863 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[6] ; ah1 ; clk ; clk ; None ; None ; 0.863 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs0[0] ; cs0[6] ; clk ; clk ; None ; None ; 0.855 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs0[1] ; cs0[7] ; clk ; clk ; None ; None ; 0.855 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[1] ; csh1[7] ; clk ; clk ; None ; None ; 0.855 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[0] ; csh1[6] ; clk ; clk ; None ; None ; 0.855 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[2] ; sh1 ; clk ; clk ; None ; None ; 0.822 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs0[1] ; cs0[6] ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs0[2] ; cs0[7] ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs0[0] ; cs0[5] ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[2] ; csh1[7] ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[1] ; csh1[6] ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[0] ; csh1[5] ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[2] ; ah1 ; clk ; clk ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cv1[1] ; av1 ; clk ; clk ; None ; None ; 0.811 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[3] ; sh1 ; clk ; clk ; None ; None ; 0.787 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[3] ; ah1 ; clk ; clk ; None ; None ; 0.786 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; csh1[2] ; csh1[6] ; clk ; clk ; None ; None ; 0.785 ns ;
- ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
- +-----------------------------------------+-----------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clock Setup: 's' ;
- +-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
- +-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
- ; N/A ; 492.37 MHz ( period = 2.031 ns ) ; cs1[2] ; cs1[7] ; s ; s ; None ; None ; 1.847 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[6] ; s ; s ; None ; None ; 1.812 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[5] ; s ; s ; None ; None ; 1.777 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[4] ; s ; s ; None ; None ; 1.742 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[3] ; s ; s ; None ; None ; 1.707 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[2] ; s ; s ; None ; None ; 1.672 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[1] ; s ; s ; None ; None ; 1.637 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; cs1[0] ; s ; s ; None ; None ; 1.574 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[7] ; s ; s ; None ; None ; 1.437 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[7] ; s ; s ; None ; None ; 1.409 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[6] ; s ; s ; None ; None ; 1.402 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[6] ; s ; s ; None ; None ; 1.374 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[5] ; s ; s ; None ; None ; 1.367 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[5] ; s ; s ; None ; None ; 1.339 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[7] ; s ; s ; None ; None ; 1.339 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[4] ; s ; s ; None ; None ; 1.332 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[7] ; s ; s ; None ; None ; 1.310 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[6] ; s ; s ; None ; None ; 1.304 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[4] ; s ; s ; None ; None ; 1.304 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[3] ; s ; s ; None ; None ; 1.297 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[6] ; s ; s ; None ; None ; 1.275 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[5] ; s ; s ; None ; None ; 1.269 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[3] ; s ; s ; None ; None ; 1.269 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[2] ; s ; s ; None ; None ; 1.262 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[5] ; s ; s ; None ; None ; 1.240 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[2] ; s ; s ; None ; None ; 1.234 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[4] ; s ; s ; None ; None ; 1.234 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[1] ; s ; s ; None ; None ; 1.227 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[7] ; s ; s ; None ; None ; 1.206 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[4] ; s ; s ; None ; None ; 1.205 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[1] ; s ; s ; None ; None ; 1.199 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[3] ; s ; s ; None ; None ; 1.199 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[6] ; s ; s ; None ; None ; 1.171 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[3] ; s ; s ; None ; None ; 1.170 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[2] ; s ; s ; None ; None ; 1.164 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; cs1[0] ; s ; s ; None ; None ; 1.164 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[5] ; s ; s ; None ; None ; 1.136 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; cs1[0] ; s ; s ; None ; None ; 1.136 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[2] ; s ; s ; None ; None ; 1.135 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[1] ; s ; s ; None ; None ; 1.129 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[7] ; s ; s ; None ; None ; 1.125 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[4] ; s ; s ; None ; None ; 1.101 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[1] ; s ; s ; None ; None ; 1.100 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[6] ; s ; s ; None ; None ; 1.090 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; cs1[0] ; s ; s ; None ; None ; 1.078 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[3] ; s ; s ; None ; None ; 1.066 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[5] ; s ; s ; None ; None ; 1.055 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; cs1[0] ; s ; s ; None ; None ; 1.037 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[2] ; s ; s ; None ; None ; 1.031 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[4] ; s ; s ; None ; None ; 1.020 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[1] ; s ; s ; None ; None ; 0.996 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[3] ; s ; s ; None ; None ; 0.985 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[2] ; s ; s ; None ; None ; 0.950 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; cs1[0] ; s ; s ; None ; None ; 0.947 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[1] ; s ; s ; None ; None ; 0.915 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[7] ; s ; s ; None ; None ; 0.890 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[6] ; s ; s ; None ; None ; 0.855 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; cs1[0] ; s ; s ; None ; None ; 0.845 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[5] ; s ; s ; None ; None ; 0.820 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[4] ; s ; s ; None ; None ; 0.785 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[3] ; s ; s ; None ; None ; 0.750 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[2] ; s ; s ; None ; None ; 0.715 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[1] ; s ; s ; None ; None ; 0.680 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[4] ; sv1 ; s ; s ; None ; None ; 1.065 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; cs1[0] ; s ; s ; None ; None ; 0.609 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[2] ; sv1 ; s ; s ; None ; None ; 1.051 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[7] ; sv1 ; s ; s ; None ; None ; 0.885 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[6] ; sv1 ; s ; s ; None ; None ; 0.864 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[3] ; sv1 ; s ; s ; None ; None ; 0.807 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[5] ; sv1 ; s ; s ; None ; None ; 0.681 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[0] ; sv1 ; s ; s ; None ; None ; 0.627 ns ;
- ; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cs1[1] ; sv1 ; s ; s ; None ; None ; 0.607 ns ;
- +-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
- +--------------------------------------------------------------+
- ; tsu ;
- +-------+--------------+------------+------+--------+----------+
- ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
- +-------+--------------+------------+------+--------+----------+
- ; N/A ; None ; 3.730 ns ; s ; fmca ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[1] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[2] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[6] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[4] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[3] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[7] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[0] ; clk ;
- ; N/A ; None ; 3.287 ns ; s ; cs0[5] ; clk ;
- +-------+--------------+------------+------+--------+----------+
- +--------------------------------------------------------------+
- ; tco ;
- +-------+--------------+------------+------+------+------------+
- ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
- +-------+--------------+------------+------+------+------------+
- ; N/A ; None ; 8.813 ns ; sv1 ; fmc1 ; s ;
- ; N/A ; None ; 7.824 ns ; oe1 ; oe ; s ;
- ; N/A ; None ; 6.550 ns ; sv11 ; fmc1 ; clk ;
- ; N/A ; None ; 6.508 ns ; sv1 ; sv ; s ;
- ; N/A ; None ; 6.283 ns ; av1 ; av ; clk ;
- ; N/A ; None ; 5.749 ns ; ah1 ; ah ; clk ;
- ; N/A ; None ; 5.636 ns ; sh1 ; sh ; clk ;
- ; N/A ; None ; 5.589 ns ; fmcb ; fmc ; clk ;
- +-------+--------------+------------+------+------+------------+
- +--------------------------------------------------------------------+
- ; th ;
- +---------------+-------------+-----------+------+--------+----------+
- ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
- +---------------+-------------+-----------+------+--------+----------+
- ; N/A ; None ; -3.048 ns ; s ; cs0[1] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[2] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[6] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[4] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[3] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[7] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[0] ; clk ;
- ; N/A ; None ; -3.048 ns ; s ; cs0[5] ; clk ;
- ; N/A ; None ; -3.491 ns ; s ; fmca ; clk ;
- +---------------+-------------+-----------+------+--------+----------+
- +--------------------------+
- ; Timing Analyzer Messages ;
- +--------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Classic Timing Analyzer
- Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
- Info: Processing started: Thu Mar 05 01:08:09 2009
- Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fj -c fj --timing_analysis_only
- Warning: Found pins functioning as undefined clocks and/or memory enables
- Info: Assuming node "clk" is an undefined clock
- Info: Assuming node "s" is an undefined clock
- Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
- Info: Detected ripple clock "sv1" as buffer
- Info: Clock "clk" has Internal fmax of 351.62 MHz between source register "cf1[0]" and destination register "fmcb" (period= 2.844 ns)
- Info: + Longest register to register delay is 1.238 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y9_N1; Fanout = 4; REG Node = 'cf1[0]'
- Info: 2: + IC(0.253 ns) + CELL(0.346 ns) = 0.599 ns; Loc. = LCCOMB_X15_Y9_N20; Fanout = 2; COMB Node = 'process2~29'
- Info: 3: + IC(0.256 ns) + CELL(0.228 ns) = 1.083 ns; Loc. = LCCOMB_X15_Y9_N28; Fanout = 1; COMB Node = 'process2~0'
- Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.238 ns; Loc. = LCFF_X15_Y9_N29; Fanout = 9; REG Node = 'fmcb'
- Info: Total cell delay = 0.729 ns ( 58.89 % )
- Info: Total interconnect delay = 0.509 ns ( 41.11 % )
- Info: - Smallest clock skew is 0.000 ns
- Info: + Shortest clock path from clock "clk" to destination register is 2.459 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 42; COMB Node = 'clk~clkctrl'
- Info: 3: + IC(0.644 ns) + CELL(0.618 ns) = 2.459 ns; Loc. = LCFF_X15_Y9_N29; Fanout = 9; REG Node = 'fmcb'
- Info: Total cell delay = 1.472 ns ( 59.86 % )
- Info: Total interconnect delay = 0.987 ns ( 40.14 % )
- Info: - Longest clock path from clock "clk" to source register is 2.459 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 42; COMB Node = 'clk~clkctrl'
- Info: 3: + IC(0.644 ns) + CELL(0.618 ns) = 2.459 ns; Loc. = LCFF_X15_Y9_N1; Fanout = 4; REG Node = 'cf1[0]'
- Info: Total cell delay = 1.472 ns ( 59.86 % )
- Info: Total interconnect delay = 0.987 ns ( 40.14 % )
- Info: + Micro clock to output delay of source is 0.094 ns
- Info: + Micro setup delay of destination is 0.090 ns
- Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
- Info: Clock "s" has Internal fmax of 492.37 MHz between source register "cs1[2]" and destination register "cs1[7]" (period= 2.031 ns)
- Info: + Longest register to register delay is 1.847 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y9_N5; Fanout = 4; REG Node = 'cs1[2]'
- Info: 2: + IC(0.550 ns) + CELL(0.346 ns) = 0.896 ns; Loc. = LCCOMB_X13_Y9_N20; Fanout = 2; COMB Node = 'LessThan6~82'
- Info: 3: + IC(0.210 ns) + CELL(0.309 ns) = 1.415 ns; Loc. = LCCOMB_X13_Y9_N0; Fanout = 2; COMB Node = 'Add3~121'
- Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 1.450 ns; Loc. = LCCOMB_X13_Y9_N2; Fanout = 2; COMB Node = 'Add3~125'
- Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 1.485 ns; Loc. = LCCOMB_X13_Y9_N4; Fanout = 2; COMB Node = 'Add3~129'
- Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 1.520 ns; Loc. = LCCOMB_X13_Y9_N6; Fanout = 2; COMB Node = 'Add3~133'
- Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 1.555 ns; Loc. = LCCOMB_X13_Y9_N8; Fanout = 2; COMB Node = 'Add3~137'
- Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 1.590 ns; Loc. = LCCOMB_X13_Y9_N10; Fanout = 2; COMB Node = 'Add3~141'
- Info: 9: + IC(0.000 ns) + CELL(0.035 ns) = 1.625 ns; Loc. = LCCOMB_X13_Y9_N12; Fanout = 1; COMB Node = 'Add3~145'
- Info: 10: + IC(0.000 ns) + CELL(0.125 ns) = 1.750 ns; Loc. = LCCOMB_X13_Y9_N14; Fanout = 1; COMB Node = 'Add3~148'
- Info: 11: + IC(0.000 ns) + CELL(0.097 ns) = 1.847 ns; Loc. = LCFF_X13_Y9_N15; Fanout = 4; REG Node = 'cs1[7]'
- Info: Total cell delay = 1.087 ns ( 58.85 % )
- Info: Total interconnect delay = 0.760 ns ( 41.15 % )
- Info: - Smallest clock skew is 0.000 ns
- Info: + Shortest clock path from clock "s" to destination register is 2.466 ns
- Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 11; CLK Node = 's'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 's~clkctrl'
- Info: 3: + IC(0.641 ns) + CELL(0.618 ns) = 2.466 ns; Loc. = LCFF_X13_Y9_N15; Fanout = 4; REG Node = 'cs1[7]'
- Info: Total cell delay = 1.482 ns ( 60.10 % )
- Info: Total interconnect delay = 0.984 ns ( 39.90 % )
- Info: - Longest clock path from clock "s" to source register is 2.466 ns
- Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 11; CLK Node = 's'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 's~clkctrl'
- Info: 3: + IC(0.641 ns) + CELL(0.618 ns) = 2.466 ns; Loc. = LCFF_X13_Y9_N5; Fanout = 4; REG Node = 'cs1[2]'
- Info: Total cell delay = 1.482 ns ( 60.10 % )
- Info: Total interconnect delay = 0.984 ns ( 39.90 % )
- Info: + Micro clock to output delay of source is 0.094 ns
- Info: + Micro setup delay of destination is 0.090 ns
- Info: tsu for register "fmca" (data pin = "s", clock pin = "clk") is 3.730 ns
- Info: + Longest pin to register delay is 6.099 ns
- Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 11; CLK Node = 's'
- Info: 2: + IC(4.714 ns) + CELL(0.366 ns) = 5.944 ns; Loc. = LCCOMB_X15_Y9_N24; Fanout = 1; COMB Node = 'process0~0'
- Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 6.099 ns; Loc. = LCFF_X15_Y9_N25; Fanout = 1; REG Node = 'fmca'
- Info: Total cell delay = 1.385 ns ( 22.71 % )
- Info: Total interconnect delay = 4.714 ns ( 77.29 % )
- Info: + Micro setup delay of destination is 0.090 ns
- Info: - Shortest clock path from clock "clk" to destination register is 2.459 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 42; COMB Node = 'clk~clkctrl'
- Info: 3: + IC(0.644 ns) + CELL(0.618 ns) = 2.459 ns; Loc. = LCFF_X15_Y9_N25; Fanout = 1; REG Node = 'fmca'
- Info: Total cell delay = 1.472 ns ( 59.86 % )
- Info: Total interconnect delay = 0.987 ns ( 40.14 % )
- Info: tco from clock "s" to destination pin "fmc1" through register "sv1" is 8.813 ns
- Info: + Longest clock path from clock "s" to source register is 2.919 ns
- Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 11; CLK Node = 's'
- Info: 2: + IC(1.437 ns) + CELL(0.618 ns) = 2.919 ns; Loc. = LCFF_X13_Y9_N23; Fanout = 4; REG Node = 'sv1'
- Info: Total cell delay = 1.482 ns ( 50.77 % )
- Info: Total interconnect delay = 1.437 ns ( 49.23 % )
- Info: + Micro clock to output delay of source is 0.094 ns
- Info: + Longest register to pin delay is 5.800 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y9_N23; Fanout = 4; REG Node = 'sv1'
- Info: 2: + IC(1.790 ns) + CELL(0.366 ns) = 2.156 ns; Loc. = LCCOMB_X21_Y14_N10; Fanout = 13; COMB Node = 'fmcc~0'
- Info: 3: + IC(1.646 ns) + CELL(1.998 ns) = 5.800 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'fmc1'
- Info: Total cell delay = 2.364 ns ( 40.76 % )
- Info: Total interconnect delay = 3.436 ns ( 59.24 % )
- Info: th for register "cs0[1]" (data pin = "s", clock pin = "clk") is -3.048 ns
- Info: + Longest clock path from clock "clk" to destination register is 2.485 ns
- Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
- Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 42; COMB Node = 'clk~clkctrl'
- Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X11_Y9_N19; Fanout = 3; REG Node = 'cs0[1]'
- Info: Total cell delay = 1.472 ns ( 59.24 % )
- Info: Total interconnect delay = 1.013 ns ( 40.76 % )
- Info: + Micro hold delay of destination is 0.149 ns
- Info: - Shortest pin to register delay is 5.682 ns
- Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 11; CLK Node = 's'
- Info: 2: + IC(4.421 ns) + CELL(0.397 ns) = 5.682 ns; Loc. = LCFF_X11_Y9_N19; Fanout = 3; REG Node = 'cs0[1]'
- Info: Total cell delay = 1.261 ns ( 22.19 % )
- Info: Total interconnect delay = 4.421 ns ( 77.81 % )
- Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Allocated 145 megabytes of memory during processing
- Info: Processing ended: Thu Mar 05 01:08:10 2009
- Info: Elapsed time: 00:00:01
