fj.qws
上传用户:whhc027
上传日期:2022-08-10
资源大小:410k
文件大小:0k
源码类别:

VHDL/FPGA/Verilog

开发平台:

VHDL

  1. [ProjectWorkspace]
  2. ptn_Child1=Frames
  3. [ProjectWorkspace.Frames]
  4. ptn_Child1=ChildFrames
  5. [ProjectWorkspace.Frames.ChildFrames]
  6. ptn_Child1=Document-0
  7. [ProjectWorkspace.Frames.ChildFrames.Document-0]
  8. ptn_Child1=ViewFrame-0
  9. [ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
  10. DocPathName=Block1.bdf
  11. DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
  12. IsChildFrameDetached=False
  13. IsActiveChildFrame=True
  14. ptn_Child1=StateMap