VHDL/FPGA/Verilog

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VHDL

prev_cmp__8259A.qmsg：源码内容

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(188) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(188): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 188 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(189) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(189): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 189 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(190) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(190): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 190 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(191) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(191): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 191 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(192) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(192): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 192 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(193) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(193): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 193 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(194) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(194): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 194 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(195) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(195): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 195 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(199) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(199): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 199 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(200) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(200): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 200 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(201) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(201): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 201 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(202) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(202): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 202 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(203) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(203): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 203 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(204) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(204): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 204 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(205) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(205): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 205 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(206) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(206): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 206 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(210) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(210): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 210 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(211) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(211): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 211 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(212) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(212): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 212 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(213) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(213): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 213 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(214) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(214): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 214 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(215) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(215): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 215 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(216) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(216): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 216 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "isr pr.v(217) " "Warning (10235): Verilog HDL Always Construct warning at pr.v(217): variable "isr" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 217 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable "%1!s!" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "position pr.v(31) " "Warning (10240): Verilog HDL Always Construct warning at pr.v(31): inferring latch(es) for variable "position", which holds its previous value in one or more paths through the always construct" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable "%1!s!", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "hp_nmr pr.v(31) " "Warning (10240): Verilog HDL Always Construct warning at pr.v(31): inferring latch(es) for variable "hp_nmr", which holds its previous value in one or more paths through the always construct" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable "%1!s!", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "hp_isr pr.v(31) " "Warning (10240): Verilog HDL Always Construct warning at pr.v(31): inferring latch(es) for variable "hp_isr", which holds its previous value in one or more paths through the always construct" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable "%1!s!", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "hp_isr[0] pr.v(31) " "Info (10041): Inferred latch for "hp_isr[0]" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "hp_isr[1] pr.v(31) " "Info (10041): Inferred latch for "hp_isr[1]" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "hp_isr[2] pr.v(31) " "Info (10041): Inferred latch for "hp_isr[2]" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "hp_nmr[0] pr.v(31) " "Info (10041): Inferred latch for "hp_nmr[0]" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "hp_nmr[1] pr.v(31) " "Info (10041): Inferred latch for "hp_nmr[1]" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "hp_nmr[2] pr.v(31) " "Info (10041): Inferred latch for "hp_nmr[2]" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.111 pr.v(31) " "Info (10041): Inferred latch for "position.111" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.110 pr.v(31) " "Info (10041): Inferred latch for "position.110" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.101 pr.v(31) " "Info (10041): Inferred latch for "position.101" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.100 pr.v(31) " "Info (10041): Inferred latch for "position.100" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.011 pr.v(31) " "Info (10041): Inferred latch for "position.011" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.010 pr.v(31) " "Info (10041): Inferred latch for "position.010" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.001 pr.v(31) " "Info (10041): Inferred latch for "position.001" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "position.000 pr.v(31) " "Info (10041): Inferred latch for "position.000" at pr.v(31)" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 10041 "Inferred latch for "%1!s!" at %2!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.000_2995 " "Warning: Latch position.000_2995 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[0] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[0]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hp_nmr[2] " "Warning: Latch hp_nmr[2] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[0] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[0]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hp_isr[2] " "Warning: Latch hp_isr[2] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA isr[0] " "Warning: Ports D and ENA on the latch are fed by the same signal isr[0]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hp_nmr[1] " "Warning: Latch hp_nmr[1] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[6] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[6]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hp_isr[1] " "Warning: Latch hp_isr[1] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA isr[6] " "Warning: Ports D and ENA on the latch are fed by the same signal isr[6]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hp_nmr[0] " "Warning: Latch hp_nmr[0] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[5] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[5]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hp_isr[0] " "Warning: Latch hp_isr[0] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA isr[5] " "Warning: Ports D and ENA on the latch are fed by the same signal isr[5]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.001_2865 " "Warning: Latch position.001_2865 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[1] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[1]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.010_2735 " "Warning: Latch position.010_2735 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[2] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[2]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.011_2605 " "Warning: Latch position.011_2605 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[3] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[3]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.100_2475 " "Warning: Latch position.100_2475 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[4] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[4]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.101_2345 " "Warning: Latch position.101_2345 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[4] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[4]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.110_2215 " "Warning: Latch position.110_2215 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[6] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[6]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "position.111_2085 " "Warning: Latch position.111_2085 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA nmr[7] " "Warning: Ports D and ENA on the latch are fed by the same signal nmr[7]" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "_8259A " "Warning: Ignored assignments for entity "_8259A" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity _8259A -section_id "Root Region" " "Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity _8259A -section_id "Root Region" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity _8259A -section_id "Root Region" " "Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity _8259A -section_id "Root Region" is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} } { } 0 0 "Ignored assignments for entity "%1!s!" -- entity does not exist in design" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "279 " "Info: Implemented 279 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "36 " "Info: Implemented 36 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "20 " "Info: Implemented 20 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "223 " "Info: Implemented 223 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 164 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 164 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 10:20:03 2010 " "Info: Processing ended: Sun Apr 25 10:20:03 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 10:20:06 2010 " "Info: Processing started: Sun Apr 25 10:20:06 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off _8259A -c _8259A " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off _8259A -c _8259A" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "_8259A EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design "_8259A"" { } { } 0 0 "Selected device %2!s! for design "%1!s!"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "279 Top " "Info: Previous placement does not exist for 279 of 279 atoms in partition Top" { } { } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0} } { } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "56 56 " "Warning: No exact pin location assignment(s) for 56 pins of 56 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[0] " "Info: Pin isr_set[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[1] " "Info: Pin isr_set[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[2] " "Info: Pin isr_set[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[3] " "Info: Pin isr_set[3] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[3] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[3] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[4] " "Info: Pin isr_set[4] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[4] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[5] " "Info: Pin isr_set[5] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[5] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[5] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[6] " "Info: Pin isr_set[6] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[6] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[6] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_set[7] " "Info: Pin isr_set[7] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_set[7] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 8 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[7] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_set[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[0] " "Info: Pin isr_clr[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[1] " "Info: Pin isr_clr[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[2] " "Info: Pin isr_clr[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[3] " "Info: Pin isr_clr[3] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[3] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[3] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[4] " "Info: Pin isr_clr[4] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[4] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[5] " "Info: Pin isr_clr[5] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[5] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[5] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[6] " "Info: Pin isr_clr[6] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[6] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[6] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr_clr[7] " "Info: Pin isr_clr[7] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr_clr[7] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 9 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[7] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr_clr[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "intr " "Info: Pin intr not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { intr } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 10 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { intr } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { intr } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "code[0] " "Info: Pin code[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { code[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "code[1] " "Info: Pin code[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { code[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "code[2] " "Info: Pin code[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { code[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sm " "Info: Pin sm not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { sm } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 2 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sm } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sm } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[0] " "Info: Pin eoi[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[1] " "Info: Pin eoi[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[2] " "Info: Pin eoi[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[3] " "Info: Pin eoi[3] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[3] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[3] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[4] " "Info: Pin eoi[4] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[4] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[5] " "Info: Pin eoi[5] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[5] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[5] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[6] " "Info: Pin eoi[6] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[6] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[6] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "eoi[7] " "Info: Pin eoi[7] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { eoi[7] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 7 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[7] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoi[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[4] " "Info: Pin isr[4] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[4] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[3] " "Info: Pin isr[3] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[3] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[3] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[2] " "Info: Pin isr[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[1] " "Info: Pin isr[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[0] " "Info: Pin isr[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[7] " "Info: Pin isr[7] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[7] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[7] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[6] " "Info: Pin isr[6] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[6] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[6] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "isr[5] " "Info: Pin isr[5] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { isr[5] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[5] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[5] " "Info: Pin mask[5] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[5] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[5] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[5] " "Info: Pin request[5] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[5] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[5] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[7] " "Info: Pin mask[7] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[7] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[7] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[6] " "Info: Pin mask[6] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[6] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[6] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[6] " "Info: Pin request[6] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[6] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[6] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[7] " "Info: Pin request[7] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[7] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[7] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[2] " "Info: Pin mask[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[2] " "Info: Pin request[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[3] " "Info: Pin mask[3] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[3] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[3] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[4] " "Info: Pin mask[4] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[4] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[4] " "Info: Pin request[4] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[4] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[4] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[3] " "Info: Pin request[3] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[3] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[3] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[0] " "Info: Pin mask[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[0] " "Info: Pin request[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sp[0] " "Info: Pin sp[0] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { sp[0] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 6 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "mask[1] " "Info: Pin mask[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { mask[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "request[1] " "Info: Pin request[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { request[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sp[1] " "Info: Pin sp[1] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { sp[1] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 6 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sp[2] " "Info: Pin sp[2] not assigned to an exact location on the device" { } { { "c:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/program files/altera/72/quartus/bin/pin_planner.ppl" { sp[2] } } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 6 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp[2] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "hp_nmr[0]~2581 " "Info: Automatically promoted node hp_nmr[0]~2581 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hp_nmr[0]~2581 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hp_nmr[0]~2581 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Equal0~30 " "Info: Automatically promoted node Equal0~30 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 28 -1 0 } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Equal0~30 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Equal0~30 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0} } { } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "56 unused 3.30 36 20 0 " "Info: Number of I/O pins in group: 56 (unused VREF, 3.30 VCCIO, 36 input, 20 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 0 64 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 64 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 57 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 57 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 56 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 58 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 65 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 65 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 58 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 58 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 58 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 56 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 56 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X0_Y12 X10_Y23 " "Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X0_Y12 to location X10_Y23" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "20 " "Warning: Found 20 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[0] 0 " "Info: Pin "isr_set[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[1] 0 " "Info: Pin "isr_set[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[2] 0 " "Info: Pin "isr_set[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[3] 0 " "Info: Pin "isr_set[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[4] 0 " "Info: Pin "isr_set[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[5] 0 " "Info: Pin "isr_set[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[6] 0 " "Info: Pin "isr_set[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_set[7] 0 " "Info: Pin "isr_set[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[0] 0 " "Info: Pin "isr_clr[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[1] 0 " "Info: Pin "isr_clr[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[2] 0 " "Info: Pin "isr_clr[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[3] 0 " "Info: Pin "isr_clr[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[4] 0 " "Info: Pin "isr_clr[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[5] 0 " "Info: Pin "isr_clr[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[6] 0 " "Info: Pin "isr_clr[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "isr_clr[7] 0 " "Info: Pin "isr_clr[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "intr 0 " "Info: Pin "intr" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "code[0] 0 " "Info: Pin "code[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "code[1] 0 " "Info: Pin "code[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "code[2] 0 " "Info: Pin "code[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin "%1!s!" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/_8259A.fit.smsg " "Info: Generated suppressed messages file F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/_8259A.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "230 " "Info: Allocated 230 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 10:20:30 2010 " "Info: Processing ended: Sun Apr 25 10:20:30 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 10:20:38 2010 " "Info: Processing started: Sun Apr 25 10:20:38 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off _8259A -c _8259A " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off _8259A -c _8259A" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Allocated 221 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 10:20:54 2010 " "Info: Processing ended: Sun Apr 25 10:20:54 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 25 10:20:58 2010 " "Info: Processing started: Sun Apr 25 10:20:58 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off _8259A -c _8259A --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off _8259A -c _8259A --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "hp_isr[1] " "Warning: Node "hp_isr[1]" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hp_nmr[1] " "Warning: Node "hp_nmr[1]" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hp_isr[0] " "Warning: Node "hp_isr[0]" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hp_nmr[0] " "Warning: Node "hp_nmr[0]" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hp_nmr[2] " "Warning: Node "hp_nmr[2]" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hp_isr[2] " "Warning: Node "hp_isr[2]" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.000_2995 " "Warning: Node "position.000_2995" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.001_2865 " "Warning: Node "position.001_2865" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.010_2735 " "Warning: Node "position.010_2735" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.011_2605 " "Warning: Node "position.011_2605" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.100_2475 " "Warning: Node "position.100_2475" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.101_2345 " "Warning: Node "position.101_2345" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.110_2215 " "Warning: Node "position.110_2215" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "position.111_2085 " "Warning: Node "position.111_2085" is a latch" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "Node "%1!s!" is a latch" 0 0 "" 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[5] " "Info: Assuming node "isr[5]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[1] " "Info: Assuming node "isr[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[3] " "Info: Assuming node "isr[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[4] " "Info: Assuming node "isr[4]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[2] " "Info: Assuming node "isr[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[7] " "Info: Assuming node "isr[7]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[0] " "Info: Assuming node "isr[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "isr[6] " "Info: Assuming node "isr[6]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[0] " "Info: Assuming node "mask[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[0] " "Info: Assuming node "request[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[6] " "Info: Assuming node "mask[6]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[7] " "Info: Assuming node "request[7]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[7] " "Info: Assuming node "mask[7]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[6] " "Info: Assuming node "request[6]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[1] " "Info: Assuming node "mask[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[1] " "Info: Assuming node "request[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[4] " "Info: Assuming node "mask[4]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[4] " "Info: Assuming node "request[4]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[3] " "Info: Assuming node "request[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[3] " "Info: Assuming node "mask[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[2] " "Info: Assuming node "mask[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[2] " "Info: Assuming node "request[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "mask[5] " "Info: Assuming node "mask[5]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "request[5] " "Info: Assuming node "request[5]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "Assuming node "%1!s!" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "nmr[1] " "Info: Detected gated clock "nmr[1]" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "nmr[1]" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "hp_nmr[2]~2580 " "Info: Detected gated clock "hp_nmr[2]~2580" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "hp_nmr[2]~2580" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "nmr[0] " "Info: Detected gated clock "nmr[0]" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "nmr[0]" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "hp_nmr[2]~2579 " "Info: Detected gated clock "hp_nmr[2]~2579" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "hp_nmr[2]~2579" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "position.111~184 " "Info: Detected gated clock "position.111~184" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 15 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "position.111~184" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "nmr[5] " "Info: Detected gated clock "nmr[5]" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "nmr[5]" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~25 " "Info: Detected gated clock "Equal0~25" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 28 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~25" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~28 " "Info: Detected gated clock "Equal0~28" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 28 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~28" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~30 " "Info: Detected gated clock "Equal0~30" as buffer" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 28 -1 0 } } { "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~30" } } } } } 0 0 "Detected gated clock "%1!s!" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "hp_nmr[1] mask[7] mask[6] 10.810 ns register " "Info: tsu for register "hp_nmr[1]" (data pin = "mask[7]", clock pin = "mask[6]") is 10.810 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.109 ns + Longest pin register " "Info: + Longest pin to register delay is 15.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns mask[7] 1 CLK PIN_T2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_T2; Fanout = 6; CLK Node = 'mask[7]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[7] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.520 ns) + CELL(0.275 ns) 6.647 ns position.110~95 2 COMB LCCOMB_X4_Y17_N16 7 " "Info: 2: + IC(5.520 ns) + CELL(0.275 ns) = 6.647 ns; Loc. = LCCOMB_X4_Y17_N16; Fanout = 7; COMB Node = 'position.110~95'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.795 ns" { mask[7] position.110~95 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.275 ns) 7.699 ns hp_nmr[1]~2599 3 COMB LCCOMB_X6_Y17_N4 1 " "Info: 3: + IC(0.777 ns) + CELL(0.275 ns) = 7.699 ns; Loc. = LCCOMB_X6_Y17_N4; Fanout = 1; COMB Node = 'hp_nmr[1]~2599'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { position.110~95 hp_nmr[1]~2599 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.019 ns) + CELL(0.419 ns) 11.137 ns Mux9~228 4 COMB LCCOMB_X25_Y35_N30 1 " "Info: 4: + IC(3.019 ns) + CELL(0.419 ns) = 11.137 ns; Loc. = LCCOMB_X25_Y35_N30; Fanout = 1; COMB Node = 'Mux9~228'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.438 ns" { hp_nmr[1]~2599 Mux9~228 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.420 ns) 11.810 ns Mux9~229 5 COMB LCCOMB_X25_Y35_N8 1 " "Info: 5: + IC(0.253 ns) + CELL(0.420 ns) = 11.810 ns; Loc. = LCCOMB_X25_Y35_N8; Fanout = 1; COMB Node = 'Mux9~229'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { Mux9~228 Mux9~229 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.206 ns) + CELL(0.420 ns) 14.436 ns Mux9~232 6 COMB LCCOMB_X7_Y27_N28 1 " "Info: 6: + IC(2.206 ns) + CELL(0.420 ns) = 14.436 ns; Loc. = LCCOMB_X7_Y27_N28; Fanout = 1; COMB Node = 'Mux9~232'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.626 ns" { Mux9~229 Mux9~232 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.419 ns) 15.109 ns hp_nmr[1] 7 REG LCCOMB_X7_Y27_N10 1 " "Info: 7: + IC(0.254 ns) + CELL(0.419 ns) = 15.109 ns; Loc. = LCCOMB_X7_Y27_N10; Fanout = 1; REG Node = 'hp_nmr[1]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { Mux9~232 hp_nmr[1] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.080 ns ( 20.39 % ) " "Info: Total cell delay = 3.080 ns ( 20.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.029 ns ( 79.61 % ) " "Info: Total interconnect delay = 12.029 ns ( 79.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.109 ns" { mask[7] position.110~95 hp_nmr[1]~2599 Mux9~228 Mux9~229 Mux9~232 hp_nmr[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "15.109 ns" { mask[7] {} mask[7]~combout {} position.110~95 {} hp_nmr[1]~2599 {} Mux9~228 {} Mux9~229 {} Mux9~232 {} hp_nmr[1] {} } { 0.000ns 0.000ns 5.520ns 0.777ns 3.019ns 0.253ns 2.206ns 0.254ns } { 0.000ns 0.852ns 0.275ns 0.275ns 0.419ns 0.420ns 0.420ns 0.419ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.677 ns + " "Info: + Micro setup delay of destination is 0.677 ns" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mask[6] destination 4.976 ns - Shortest register " "Info: - Shortest clock path from clock "mask[6]" to destination register is 4.976 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns mask[6] 1 CLK PIN_R6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_R6; Fanout = 4; CLK Node = 'mask[6]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[6] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.150 ns) 2.011 ns hp_nmr[2]~2579 2 COMB LCCOMB_X1_Y17_N14 19 " "Info: 2: + IC(1.009 ns) + CELL(0.150 ns) = 2.011 ns; Loc. = LCCOMB_X1_Y17_N14; Fanout = 19; COMB Node = 'hp_nmr[2]~2579'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.159 ns" { mask[6] hp_nmr[2]~2579 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.275 ns) 2.548 ns hp_nmr[0]~2581 3 COMB LCCOMB_X1_Y17_N4 1 " "Info: 3: + IC(0.262 ns) + CELL(0.275 ns) = 2.548 ns; Loc. = LCCOMB_X1_Y17_N4; Fanout = 1; COMB Node = 'hp_nmr[0]~2581'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.537 ns" { hp_nmr[2]~2579 hp_nmr[0]~2581 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.000 ns) 3.368 ns hp_nmr[0]~2581clkctrl 4 COMB CLKCTRL_G2 11 " "Info: 4: + IC(0.820 ns) + CELL(0.000 ns) = 3.368 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'hp_nmr[0]~2581clkctrl'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.820 ns" { hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.333 ns) + CELL(0.275 ns) 4.976 ns hp_nmr[1] 5 REG LCCOMB_X7_Y27_N10 1 " "Info: 5: + IC(1.333 ns) + CELL(0.275 ns) = 4.976 ns; Loc. = LCCOMB_X7_Y27_N10; Fanout = 1; REG Node = 'hp_nmr[1]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.608 ns" { hp_nmr[0]~2581clkctrl hp_nmr[1] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.552 ns ( 31.19 % ) " "Info: Total cell delay = 1.552 ns ( 31.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.424 ns ( 68.81 % ) " "Info: Total interconnect delay = 3.424 ns ( 68.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { mask[6] hp_nmr[2]~2579 hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl hp_nmr[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.976 ns" { mask[6] {} mask[6]~combout {} hp_nmr[2]~2579 {} hp_nmr[0]~2581 {} hp_nmr[0]~2581clkctrl {} hp_nmr[1] {} } { 0.000ns 0.000ns 1.009ns 0.262ns 0.820ns 1.333ns } { 0.000ns 0.852ns 0.150ns 0.275ns 0.000ns 0.275ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock "%1!s!" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.109 ns" { mask[7] position.110~95 hp_nmr[1]~2599 Mux9~228 Mux9~229 Mux9~232 hp_nmr[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "15.109 ns" { mask[7] {} mask[7]~combout {} position.110~95 {} hp_nmr[1]~2599 {} Mux9~228 {} Mux9~229 {} Mux9~232 {} hp_nmr[1] {} } { 0.000ns 0.000ns 5.520ns 0.777ns 3.019ns 0.253ns 2.206ns 0.254ns } { 0.000ns 0.852ns 0.275ns 0.275ns 0.419ns 0.420ns 0.420ns 0.419ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.976 ns" { mask[6] hp_nmr[2]~2579 hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl hp_nmr[1] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.976 ns" { mask[6] {} mask[6]~combout {} hp_nmr[2]~2579 {} hp_nmr[0]~2581 {} hp_nmr[0]~2581clkctrl {} hp_nmr[1] {} } { 0.000ns 0.000ns 1.009ns 0.262ns 0.820ns 1.333ns } { 0.000ns 0.852ns 0.150ns 0.275ns 0.000ns 0.275ns } "" } } } 0 0 "tsu for %5!s! "%1!s!" (data pin = "%2!s!", clock pin = "%3!s!") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "request[1] code[0] position.000_2995 18.007 ns register " "Info: tco from clock "request[1]" to destination pin "code[0]" through register "position.000_2995" is 18.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "request[1] source 6.133 ns + Longest register " "Info: + Longest clock path from clock "request[1]" to source register is 6.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns request[1] 1 CLK PIN_P3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P3; Fanout = 8; CLK Node = 'request[1]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[1] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.962 ns) + CELL(0.271 ns) 2.075 ns nmr[1] 2 COMB LCCOMB_X2_Y17_N16 11 " "Info: 2: + IC(0.962 ns) + CELL(0.271 ns) = 2.075 ns; Loc. = LCCOMB_X2_Y17_N16; Fanout = 11; COMB Node = 'nmr[1]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { request[1] nmr[1] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.150 ns) 2.911 ns position.111~184 3 COMB LCCOMB_X1_Y16_N0 8 " "Info: 3: + IC(0.686 ns) + CELL(0.150 ns) = 2.911 ns; Loc. = LCCOMB_X1_Y16_N0; Fanout = 8; COMB Node = 'position.111~184'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.836 ns" { nmr[1] position.111~184 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.420 ns) 3.777 ns hp_nmr[0]~2581 4 COMB LCCOMB_X1_Y17_N4 1 " "Info: 4: + IC(0.446 ns) + CELL(0.420 ns) = 3.777 ns; Loc. = LCCOMB_X1_Y17_N4; Fanout = 1; COMB Node = 'hp_nmr[0]~2581'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.866 ns" { position.111~184 hp_nmr[0]~2581 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.000 ns) 4.597 ns hp_nmr[0]~2581clkctrl 5 COMB CLKCTRL_G2 11 " "Info: 5: + IC(0.820 ns) + CELL(0.000 ns) = 4.597 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'hp_nmr[0]~2581clkctrl'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.820 ns" { hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.386 ns) + CELL(0.150 ns) 6.133 ns position.000_2995 6 REG LCCOMB_X5_Y17_N14 2 " "Info: 6: + IC(1.386 ns) + CELL(0.150 ns) = 6.133 ns; Loc. = LCCOMB_X5_Y17_N14; Fanout = 2; REG Node = 'position.000_2995'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { hp_nmr[0]~2581clkctrl position.000_2995 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.833 ns ( 29.89 % ) " "Info: Total cell delay = 1.833 ns ( 29.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 70.11 % ) " "Info: Total interconnect delay = 4.300 ns ( 70.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.133 ns" { request[1] nmr[1] position.111~184 hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl position.000_2995 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.133 ns" { request[1] {} request[1]~combout {} nmr[1] {} position.111~184 {} hp_nmr[0]~2581 {} hp_nmr[0]~2581clkctrl {} position.000_2995 {} } { 0.000ns 0.000ns 0.962ns 0.686ns 0.446ns 0.820ns 1.386ns } { 0.000ns 0.842ns 0.271ns 0.150ns 0.420ns 0.000ns 0.150ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock "%1!s!" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.874 ns + Longest register pin " "Info: + Longest register to pin delay is 11.874 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns position.000_2995 1 REG LCCOMB_X5_Y17_N14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X5_Y17_N14; Fanout = 2; REG Node = 'position.000_2995'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { position.000_2995 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.288 ns) + CELL(0.275 ns) 3.563 ns code~145 2 COMB LCCOMB_X28_Y35_N16 3 " "Info: 2: + IC(3.288 ns) + CELL(0.275 ns) = 3.563 ns; Loc. = LCCOMB_X28_Y35_N16; Fanout = 3; COMB Node = 'code~145'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.563 ns" { position.000_2995 code~145 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.347 ns) + CELL(0.275 ns) 7.185 ns code~146 3 COMB LCCOMB_X7_Y17_N12 1 " "Info: 3: + IC(3.347 ns) + CELL(0.275 ns) = 7.185 ns; Loc. = LCCOMB_X7_Y17_N12; Fanout = 1; COMB Node = 'code~146'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.622 ns" { code~145 code~146 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.921 ns) + CELL(2.768 ns) 11.874 ns code[0] 4 PIN PIN_E8 0 " "Info: 4: + IC(1.921 ns) + CELL(2.768 ns) = 11.874 ns; Loc. = PIN_E8; Fanout = 0; PIN Node = 'code[0]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.689 ns" { code~146 code[0] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.318 ns ( 27.94 % ) " "Info: Total cell delay = 3.318 ns ( 27.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.556 ns ( 72.06 % ) " "Info: Total interconnect delay = 8.556 ns ( 72.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.874 ns" { position.000_2995 code~145 code~146 code[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "11.874 ns" { position.000_2995 {} code~145 {} code~146 {} code[0] {} } { 0.000ns 3.288ns 3.347ns 1.921ns } { 0.000ns 0.275ns 0.275ns 2.768ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.133 ns" { request[1] nmr[1] position.111~184 hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl position.000_2995 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.133 ns" { request[1] {} request[1]~combout {} nmr[1] {} position.111~184 {} hp_nmr[0]~2581 {} hp_nmr[0]~2581clkctrl {} position.000_2995 {} } { 0.000ns 0.000ns 0.962ns 0.686ns 0.446ns 0.820ns 1.386ns } { 0.000ns 0.842ns 0.271ns 0.150ns 0.420ns 0.000ns 0.150ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.874 ns" { position.000_2995 code~145 code~146 code[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "11.874 ns" { position.000_2995 {} code~145 {} code~146 {} code[0] {} } { 0.000ns 3.288ns 3.347ns 1.921ns } { 0.000ns 0.275ns 0.275ns 2.768ns } "" } } } 0 0 "tco from clock "%1!s!" to destination pin "%2!s!" through %5!s! "%3!s!" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "isr[7] code[0] 15.111 ns Longest " "Info: Longest tpd from source pin "isr[7]" to destination pin "code[0]" is 15.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns isr[7] 1 CLK PIN_B11 14 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_B11; Fanout = 14; CLK Node = 'isr[7]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { isr[7] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.168 ns) + CELL(0.371 ns) 6.389 ns Equal0~26 2 COMB LCCOMB_X28_Y35_N2 2 " "Info: 2: + IC(5.168 ns) + CELL(0.371 ns) = 6.389 ns; Loc. = LCCOMB_X28_Y35_N2; Fanout = 2; COMB Node = 'Equal0~26'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.539 ns" { isr[7] Equal0~26 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.150 ns) 6.800 ns code~145 3 COMB LCCOMB_X28_Y35_N16 3 " "Info: 3: + IC(0.261 ns) + CELL(0.150 ns) = 6.800 ns; Loc. = LCCOMB_X28_Y35_N16; Fanout = 3; COMB Node = 'code~145'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.411 ns" { Equal0~26 code~145 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.347 ns) + CELL(0.275 ns) 10.422 ns code~146 4 COMB LCCOMB_X7_Y17_N12 1 " "Info: 4: + IC(3.347 ns) + CELL(0.275 ns) = 10.422 ns; Loc. = LCCOMB_X7_Y17_N12; Fanout = 1; COMB Node = 'code~146'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.622 ns" { code~145 code~146 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.921 ns) + CELL(2.768 ns) 15.111 ns code[0] 5 PIN PIN_E8 0 " "Info: 5: + IC(1.921 ns) + CELL(2.768 ns) = 15.111 ns; Loc. = PIN_E8; Fanout = 0; PIN Node = 'code[0]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.689 ns" { code~146 code[0] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.414 ns ( 29.21 % ) " "Info: Total cell delay = 4.414 ns ( 29.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.697 ns ( 70.79 % ) " "Info: Total interconnect delay = 10.697 ns ( 70.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.111 ns" { isr[7] Equal0~26 code~145 code~146 code[0] } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "15.111 ns" { isr[7] {} isr[7]~combout {} Equal0~26 {} code~145 {} code~146 {} code[0] {} } { 0.000ns 0.000ns 5.168ns 0.261ns 3.347ns 1.921ns } { 0.000ns 0.850ns 0.371ns 0.150ns 0.275ns 2.768ns } "" } } } 0 0 "%4!s! tpd from source pin "%1!s!" to destination pin "%2!s!" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "position.000_2995 mask[0] request[1] 1.958 ns register " "Info: th for register "position.000_2995" (data pin = "mask[0]", clock pin = "request[1]") is 1.958 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "request[1] destination 6.133 ns + Longest register " "Info: + Longest clock path from clock "request[1]" to destination register is 6.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns request[1] 1 CLK PIN_P3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P3; Fanout = 8; CLK Node = 'request[1]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { request[1] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.962 ns) + CELL(0.271 ns) 2.075 ns nmr[1] 2 COMB LCCOMB_X2_Y17_N16 11 " "Info: 2: + IC(0.962 ns) + CELL(0.271 ns) = 2.075 ns; Loc. = LCCOMB_X2_Y17_N16; Fanout = 11; COMB Node = 'nmr[1]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { request[1] nmr[1] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.150 ns) 2.911 ns position.111~184 3 COMB LCCOMB_X1_Y16_N0 8 " "Info: 3: + IC(0.686 ns) + CELL(0.150 ns) = 2.911 ns; Loc. = LCCOMB_X1_Y16_N0; Fanout = 8; COMB Node = 'position.111~184'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.836 ns" { nmr[1] position.111~184 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.420 ns) 3.777 ns hp_nmr[0]~2581 4 COMB LCCOMB_X1_Y17_N4 1 " "Info: 4: + IC(0.446 ns) + CELL(0.420 ns) = 3.777 ns; Loc. = LCCOMB_X1_Y17_N4; Fanout = 1; COMB Node = 'hp_nmr[0]~2581'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.866 ns" { position.111~184 hp_nmr[0]~2581 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.000 ns) 4.597 ns hp_nmr[0]~2581clkctrl 5 COMB CLKCTRL_G2 11 " "Info: 5: + IC(0.820 ns) + CELL(0.000 ns) = 4.597 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'hp_nmr[0]~2581clkctrl'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.820 ns" { hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.386 ns) + CELL(0.150 ns) 6.133 ns position.000_2995 6 REG LCCOMB_X5_Y17_N14 2 " "Info: 6: + IC(1.386 ns) + CELL(0.150 ns) = 6.133 ns; Loc. = LCCOMB_X5_Y17_N14; Fanout = 2; REG Node = 'position.000_2995'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { hp_nmr[0]~2581clkctrl position.000_2995 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.833 ns ( 29.89 % ) " "Info: Total cell delay = 1.833 ns ( 29.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 70.11 % ) " "Info: Total interconnect delay = 4.300 ns ( 70.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.133 ns" { request[1] nmr[1] position.111~184 hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl position.000_2995 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.133 ns" { request[1] {} request[1]~combout {} nmr[1] {} position.111~184 {} hp_nmr[0]~2581 {} hp_nmr[0]~2581clkctrl {} position.000_2995 {} } { 0.000ns 0.000ns 0.962ns 0.686ns 0.446ns 0.820ns 1.386ns } { 0.000ns 0.842ns 0.271ns 0.150ns 0.420ns 0.000ns 0.150ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock "%1!s!" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.175 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns mask[0] 1 CLK PIN_R7 11 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_R7; Fanout = 11; CLK Node = 'mask[0]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mask[0] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.219 ns) + CELL(0.149 ns) 2.220 ns nmr[0] 2 COMB LCCOMB_X4_Y17_N20 15 " "Info: 2: + IC(1.219 ns) + CELL(0.149 ns) = 2.220 ns; Loc. = LCCOMB_X4_Y17_N20; Fanout = 15; COMB Node = 'nmr[0]'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.368 ns" { mask[0] nmr[0] } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.275 ns) 2.983 ns Mux0~147 3 COMB LCCOMB_X5_Y17_N4 1 " "Info: 3: + IC(0.488 ns) + CELL(0.275 ns) = 2.983 ns; Loc. = LCCOMB_X5_Y17_N4; Fanout = 1; COMB Node = 'Mux0~147'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.763 ns" { nmr[0] Mux0~147 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.271 ns) 3.507 ns Mux0~150 4 COMB LCCOMB_X5_Y17_N26 1 " "Info: 4: + IC(0.253 ns) + CELL(0.271 ns) = 3.507 ns; Loc. = LCCOMB_X5_Y17_N26; Fanout = 1; COMB Node = 'Mux0~150'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.524 ns" { Mux0~147 Mux0~150 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.419 ns) 4.175 ns position.000_2995 5 REG LCCOMB_X5_Y17_N14 2 " "Info: 5: + IC(0.249 ns) + CELL(0.419 ns) = 4.175 ns; Loc. = LCCOMB_X5_Y17_N14; Fanout = 2; REG Node = 'position.000_2995'" { } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.668 ns" { Mux0~150 position.000_2995 } "NODE_NAME" } } { "pr.v" "" { Text "F:/[DOCUMENTS]/InterfaceAndCommunication/_8259A/pr.v" 31 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.966 ns ( 47.09 % ) " "Info: Total cell delay = 1.966 ns ( 47.09 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.209 ns ( 52.91 % ) " "Info: Total interconnect delay = 2.209 ns ( 52.91 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.175 ns" { mask[0] nmr[0] Mux0~147 Mux0~150 position.000_2995 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.175 ns" { mask[0] {} mask[0]~combout {} nmr[0] {} Mux0~147 {} Mux0~150 {} position.000_2995 {} } { 0.000ns 0.000ns 1.219ns 0.488ns 0.253ns 0.249ns } { 0.000ns 0.852ns 0.149ns 0.275ns 0.271ns 0.419ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.133 ns" { request[1] nmr[1] position.111~184 hp_nmr[0]~2581 hp_nmr[0]~2581clkctrl position.000_2995 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.133 ns" { request[1] {} request[1]~combout {} nmr[1] {} position.111~184 {} hp_nmr[0]~2581 {} hp_nmr[0]~2581clkctrl {} position.000_2995 {} } { 0.000ns 0.000ns 0.962ns 0.686ns 0.446ns 0.820ns 1.386ns } { 0.000ns 0.842ns 0.271ns 0.150ns 0.420ns 0.000ns 0.150ns } "" } } { "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.175 ns" { mask[0] nmr[0] Mux0~147 Mux0~150 position.000_2995 } "NODE_NAME" } } { "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.175 ns" { mask[0] {} mask[0]~combout {} nmr[0] {} Mux0~147 {} Mux0~150 {} position.000_2995 {} } { 0.000ns 0.000ns 1.219ns 0.488ns 0.253ns 0.249ns } { 0.000ns 0.852ns 0.149ns 0.275ns 0.271ns 0.419ns } "" } } } 0 0 "th for %5!s! "%1!s!" (data pin = "%2!s!", clock pin = "%3!s!") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 17 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 25 10:20:59 2010 " "Info: Processing ended: Sun Apr 25 10:20:59 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 186 s " "Info: Quartus II Full Compilation was successful. 0 errors, 186 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}