English
deb_i2c.map.rpt
资源名称：I2C.rar [点击查看]
上传用户：lcztgy
上传日期：2007-03-17
资源大小：70k
文件大小：56k
源码类别：
并行计算
开发平台：
VHDL
- Analysis & Synthesis report for deb_i2c
- Tue Jan 30 16:34:44 2007
- Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Analysis & Synthesis Source Files Read
- 5. Analysis & Synthesis Resource Usage Summary
- 6. Analysis & Synthesis Resource Utilization by Entity
- 7. State Machine - |deb_i2c|i2c_top:inst|cs
- 8. State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state
- 9. State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state
- 10. State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state
- 11. State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state
- 12. State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state
- 13. General Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: i2c_top:inst
- 16. Parameter Settings for User Entity Instance: i2c_top:inst|i2c_wr:i2c_wr_inst
- 17. Analysis & Synthesis Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2006 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +---------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +------------------------------------+--------------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Tue Jan 30 16:34:44 2007 ;
- ; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1.18 SJ Full Version ;
- ; Revision Name ; deb_i2c ;
- ; Top-level Entity Name ; deb_i2c ;
- ; Family ; Cyclone II ;
- ; Total logic elements ; 279 ;
- ; Total registers ; 153 ;
- ; Total pins ; 6 ;
- ; Total virtual pins ; 0 ;
- ; Total memory bits ; 0 ;
- ; Embedded Multiplier 9-bit elements ; 0 ;
- ; Total PLLs ; 0 ;
- +------------------------------------+--------------------------------------------------+
- +--------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +--------------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +--------------------------------------------------------------------+--------------------+--------------------+
- ; Device ; EP2C8Q208C8 ; ;
- ; Top-level entity name ; deb_i2c ; deb_i2c ;
- ; Family name ; Cyclone II ; Stratix ;
- ; Use smart compilation ; Off ; Off ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL93 ; VHDL93 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; DSP Block Balancing ; Auto ; Auto ;
- ; Maximum DSP Block Usage ; Unlimited ; Unlimited ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
- ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto Open-Drain Pins ; On ; On ;
- ; Remove Duplicate Logic ; On ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
- ; Perform gate-level register retiming ; Off ; Off ;
- ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto Shift Register Replacement ; On ; On ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
- ; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
- ; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
- ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; HDL message level ; Level2 ; Level2 ;
- +--------------------------------------------------------------------+--------------------+--------------------+
- +--------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +----------------------------------+-----------------+------------------------------------+--------------------------------------------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
- +----------------------------------+-----------------+------------------------------------+--------------------------------------------+
- ; i2c_top.v ; yes ; User Verilog HDL File ; D:/altera_6/works/ep2c8/I2C/i2c_top.v ;
- ; i2c_wr.v ; yes ; User Verilog HDL File ; D:/altera_6/works/ep2c8/I2C/i2c_wr.v ;
- ; deb_i2c.bdf ; yes ; User Block Diagram/Schematic File ; D:/altera_6/works/ep2c8/I2C/deb_i2c.bdf ;
- ; hc164_driver.v ; yes ; Other ; D:/altera_6/works/ep2c8/I2C/hc164_driver.v ;
- +----------------------------------+-----------------+------------------------------------+--------------------------------------------+
- +-----------------------------------------------------------+
- ; Analysis & Synthesis Resource Usage Summary ;
- +---------------------------------------------+-------------+
- ; Resource ; Usage ;
- +---------------------------------------------+-------------+
- ; Estimated Total logic elements ; 279 ;
- ; Total combinational functions ; 279 ;
- ; Logic element usage by number of LUT inputs ; ;
- ; -- 4 input functions ; 159 ;
- ; -- 3 input functions ; 35 ;
- ; -- <=2 input functions ; 85 ;
- ; -- Combinational cells for routing ; 0 ;
- ; Logic elements by mode ; ;
- ; -- normal mode ; 228 ;
- ; -- arithmetic mode ; 51 ;
- ; Total registers ; 153 ;
- ; I/O pins ; 6 ;
- ; Maximum fan-out node ; pld_CLEAR_n ;
- ; Maximum fan-out ; 130 ;
- ; Total fan-out ; 1407 ;
- ; Average fan-out ; 3.21 ;
- +---------------------------------------------+-------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Utilization by Entity ;
- +----------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
- +----------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------+
- ; |deb_i2c ; 279 (0) ; 153 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; |deb_i2c ;
- ; |i2c_top:inst| ; 279 (69) ; 153 (64) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |deb_i2c|i2c_top:inst ;
- ; |hc164_driver:hc164_driver_inst| ; 54 (54) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |deb_i2c|i2c_top:inst|hc164_driver:hc164_driver_inst ;
- ; |i2c_wr:i2c_wr_inst| ; 156 (156) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst ;
- +----------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +---------------------------------------------------------------------------------------------+
- ; State Machine - |deb_i2c|i2c_top:inst|cs ;
- +------------+---------+-----------+------------+----------+-----------+------------+---------+
- ; Name ; cs.SHOW ; cs.RD_ACK ; cs.RD_BYTE ; cs.DELAY ; cs.WR_ACK ; cs.WR_BYTE ; cs.IDLE ;
- +------------+---------+-----------+------------+----------+-----------+------------+---------+
- ; cs.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; cs.RD_ACK ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; cs.RD_BYTE ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
- ; cs.DELAY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
- ; cs.WR_ACK ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
- ; cs.WR_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
- ; cs.SHOW ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- +------------+---------+-----------+------------+----------+-----------+------------+---------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state ;
- +------------------------+-----------------+-----------------+----------------------+----------------------+-----------------------+-----------------------+-----------------------+-----------------------+------------------------+------------------+-----------------+
- ; Name ; main_state.Ackn ; main_state.Stop ; main_state.Data_read ; main_state.Ctrl_read ; main_state.Read_start ; main_state.Data_write ; main_state.Addr_write ; main_state.Ctrl_write ; main_state.Write_start ; main_state.Ready ; main_state.Idle ;
- +------------------------+-----------------+-----------------+----------------------+----------------------+-----------------------+-----------------------+-----------------------+-----------------------+------------------------+------------------+-----------------+
- ; main_state.Idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; main_state.Data_read ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; main_state.Ctrl_read ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; main_state.Stop ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; main_state.Read_start ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; main_state.Data_write ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; main_state.Addr_write ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
- ; main_state.Ctrl_write ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
- ; main_state.Write_start ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
- ; main_state.Ready ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
- ; main_state.Ackn ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- +------------------------+-----------------+-----------------+----------------------+----------------------+-----------------------+-----------------------+-----------------------+-----------------------+------------------------+------------------+-----------------+
- +-------------------------------------------------------------------------------------------+
- ; State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state ;
- +-----------------------+---------------------+---------------------+-----------------------+
- ; Name ; head_state.head_end ; head_state.head_bit ; head_state.head_begin ;
- +-----------------------+---------------------+---------------------+-----------------------+
- ; head_state.head_end ; 0 ; 0 ; 0 ;
- ; head_state.head_bit ; 1 ; 1 ; 0 ;
- ; head_state.head_begin ; 1 ; 0 ; 1 ;
- +-----------------------+---------------------+---------------------+-----------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state ;
- +--------------------------+-------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+
- ; Name ; sh8out_state.sh8out_end ; sh8out_state.sh8out_bit0 ; sh8out_state.sh8out_bit1 ; sh8out_state.sh8out_bit2 ; sh8out_state.sh8out_bit3 ; sh8out_state.sh8out_bit4 ; sh8out_state.sh8out_bit5 ; sh8out_state.sh8out_bit6 ; sh8out_state.sh8out_bit7 ;
- +--------------------------+-------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+
- ; sh8out_state.sh8out_end ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit1 ; 1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit2 ; 1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit3 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit4 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit5 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ;
- ; sh8out_state.sh8out_bit7 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- ; sh8out_state.sh8out_bit6 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ;
- +--------------------------+-------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+--------------------------+
- +-------------------------------------------------------------------------------------------+
- ; State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state ;
- +-----------------------+---------------------+---------------------+-----------------------+
- ; Name ; stop_state.stop_end ; stop_state.stop_bit ; stop_state.stop_begin ;
- +-----------------------+---------------------+---------------------+-----------------------+
- ; stop_state.stop_end ; 0 ; 0 ; 0 ;
- ; stop_state.stop_bit ; 1 ; 1 ; 0 ;
- ; stop_state.stop_begin ; 1 ; 0 ; 1 ;
- +-----------------------+---------------------+---------------------+-----------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; State Machine - |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state ;
- +-------------------------+-----------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-------------------------+
- ; Name ; sh8in_state.sh8in_end ; sh8in_state.sh8in_bit0 ; sh8in_state.sh8in_bit1 ; sh8in_state.sh8in_bit2 ; sh8in_state.sh8in_bit3 ; sh8in_state.sh8in_bit4 ; sh8in_state.sh8in_bit5 ; sh8in_state.sh8in_bit6 ; sh8in_state.sh8in_bit7 ; sh8in_state.sh8in_begin ;
- +-------------------------+-----------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-------------------------+
- ; sh8in_state.sh8in_end ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit1 ; 1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit2 ; 1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit3 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit4 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit5 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit6 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ;
- ; sh8in_state.sh8in_bit7 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ;
- ; sh8in_state.sh8in_begin ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
- +-------------------------+-----------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-------------------------+
- +------------------------------------------------------+
- ; General Register Statistics ;
- +----------------------------------------------+-------+
- ; Statistic ; Value ;
- +----------------------------------------------+-------+
- ; Total registers ; 153 ;
- ; Number of registers using Synchronous Clear ; 18 ;
- ; Number of registers using Synchronous Load ; 3 ;
- ; Number of registers using Asynchronous Clear ; 110 ;
- ; Number of registers using Asynchronous Load ; 0 ;
- ; Number of registers using Clock Enable ; 60 ;
- ; Number of registers using Preset ; 0 ;
- +----------------------------------------------+-------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Multiplexer Restructuring Statistics (Restructuring Performed) ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
- ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
- ; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7] ;
- ; 10:1 ; 3 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[3] ;
- ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |deb_i2c|i2c_top:inst|hc164_driver:hc164_driver_inst|Selector1 ;
- ; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; No ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~20 ;
- ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state~14 ;
- ; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|Selector48 ;
- ; 11:1 ; 2 bits ; 14 LEs ; 6 LEs ; 8 LEs ; No ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state~54 ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
- +-----------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: i2c_top:inst ;
- +----------------+---------+--------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+---------+--------------------------------+
- ; IDLE ; 0000001 ; Binary ;
- ; WR_BYTE ; 0000010 ; Binary ;
- ; WR_ACK ; 0000100 ; Binary ;
- ; DELAY ; 0001000 ; Binary ;
- ; RD_BYTE ; 0010000 ; Binary ;
- ; RD_ACK ; 0100000 ; Binary ;
- ; SHOW ; 1000000 ; Binary ;
- +----------------+---------+--------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: i2c_top:inst|i2c_wr:i2c_wr_inst ;
- +----------------+-------------+-----------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------------+-----------------------------------------------+
- ; Idle ; 00000000001 ; Binary ;
- ; Ready ; 00000000010 ; Binary ;
- ; Write_start ; 00000000100 ; Binary ;
- ; Ctrl_write ; 00000001000 ; Binary ;
- ; Addr_write ; 00000010000 ; Binary ;
- ; Data_write ; 00000100000 ; Binary ;
- ; Read_start ; 00001000000 ; Binary ;
- ; Ctrl_read ; 00010000000 ; Binary ;
- ; Data_read ; 00100000000 ; Binary ;
- ; Stop ; 01000000000 ; Binary ;
- ; Ackn ; 10000000000 ; Binary ;
- ; sh8out_bit7 ; 000000001 ; Binary ;
- ; sh8out_bit6 ; 000000010 ; Binary ;
- ; sh8out_bit5 ; 000000100 ; Binary ;
- ; sh8out_bit4 ; 000001000 ; Binary ;
- ; sh8out_bit3 ; 000010000 ; Binary ;
- ; sh8out_bit2 ; 000100000 ; Binary ;
- ; sh8out_bit1 ; 001000000 ; Binary ;
- ; sh8out_bit0 ; 010000000 ; Binary ;
- ; sh8out_end ; 100000000 ; Binary ;
- ; sh8in_begin ; 0000000001 ; Binary ;
- ; sh8in_bit7 ; 0000000010 ; Binary ;
- ; sh8in_bit6 ; 0000000100 ; Binary ;
- ; sh8in_bit5 ; 0000001000 ; Binary ;
- ; sh8in_bit4 ; 0000010000 ; Binary ;
- ; sh8in_bit3 ; 0000100000 ; Binary ;
- ; sh8in_bit2 ; 0001000000 ; Binary ;
- ; sh8in_bit1 ; 0010000000 ; Binary ;
- ; sh8in_bit0 ; 0100000000 ; Binary ;
- ; sh8in_end ; 1000000000 ; Binary ;
- ; head_begin ; 001 ; Binary ;
- ; head_bit ; 010 ; Binary ;
- ; head_end ; 100 ; Binary ;
- ; stop_begin ; 001 ; Binary ;
- ; stop_bit ; 010 ; Binary ;
- ; stop_end ; 100 ; Binary ;
- ; YES ; 1 ; Integer ;
- ; NO ; 0 ; Integer ;
- +----------------+-------------+-----------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Analysis & Synthesis
- Info: Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
- Info: Processing started: Tue Jan 30 16:34:37 2007
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off deb_i2c -c deb_i2c
- Info: Found 1 design units, including 1 entities, in source file i2c_top.v
- Info: Found entity 1: i2c_top
- Info: Found 1 design units, including 1 entities, in source file i2c_wr.v
- Info: Found entity 1: i2c_wr
- Warning: Can't analyze file -- file D:/altera_6/works/ep2c8/I2C/seg_display.v is missing
- Info: Found 1 design units, including 1 entities, in source file deb_i2c.bdf
- Info: Found entity 1: deb_i2c
- Info: Elaborating entity "deb_i2c" for the top level hierarchy
- Info: Elaborating entity "i2c_top" for hierarchy "i2c_top:inst"
- Info: Elaborating entity "i2c_wr" for hierarchy "i2c_top:inst|i2c_wr:i2c_wr_inst"
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(110): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(111): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(112): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(113): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(127): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(128): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(129): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(130): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(151): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(152): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(153): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(154): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(438): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(439): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(440): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(457): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(458): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(168): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(169): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(354): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(355): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(363): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(364): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(421): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(422): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(210): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(220): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(221): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(222): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(232): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(233): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(244): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(245): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(472): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(473): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(474): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(488): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(489): truncated value with size 32 to match size of target (1)
- Warning (10230): Verilog HDL assignment warning at i2c_wr.v(490): truncated value with size 32 to match size of target (1)
- Warning: Using design file hc164_driver.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
- Info: Found entity 1: hc164_driver
- Info: Elaborating entity "hc164_driver" for hierarchy "i2c_top:inst|hc164_driver:hc164_driver_inst"
- Info: Duplicate registers merged to single register
- Info: Duplicate register "i2c_top:inst|data_w[0]" merged to single register "i2c_top:inst|addr[0]"
- Info: Duplicate register "i2c_top:inst|data_w[1]" merged to single register "i2c_top:inst|addr[1]"
- Info: Duplicate register "i2c_top:inst|data_w[2]" merged to single register "i2c_top:inst|addr[2]"
- Info: Duplicate register "i2c_top:inst|data_w[3]" merged to single register "i2c_top:inst|addr[3]"
- Info: Duplicate register "i2c_top:inst|data_w[4]" merged to single register "i2c_top:inst|addr[4]"
- Info: Duplicate register "i2c_top:inst|data_w[5]" merged to single register "i2c_top:inst|addr[5]"
- Info: Duplicate register "i2c_top:inst|data_w[6]" merged to single register "i2c_top:inst|addr[6]"
- Info: Duplicate register "i2c_top:inst|data_w[7]" merged to single register "i2c_top:inst|addr[7]"
- Info: State machine "|deb_i2c|i2c_top:inst|cs" contains 7 states
- Info: State machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state" contains 11 states
- Info: State machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state" contains 3 states
- Info: State machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state" contains 9 states
- Info: State machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state" contains 3 states
- Info: State machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state" contains 10 states
- Info: Selected Auto state machine encoding method for state machine "|deb_i2c|i2c_top:inst|cs"
- Info: Encoding result for state machine "|deb_i2c|i2c_top:inst|cs"
- Info: Completed encoding using 7 state bits
- Info: Encoded state bit "i2c_top:inst|cs.SHOW"
- Info: Encoded state bit "i2c_top:inst|cs.RD_ACK"
- Info: Encoded state bit "i2c_top:inst|cs.RD_BYTE"
- Info: Encoded state bit "i2c_top:inst|cs.DELAY"
- Info: Encoded state bit "i2c_top:inst|cs.WR_ACK"
- Info: Encoded state bit "i2c_top:inst|cs.WR_BYTE"
- Info: Encoded state bit "i2c_top:inst|cs.IDLE"
- Info: State "|deb_i2c|i2c_top:inst|cs.IDLE" uses code string "0000000"
- Info: State "|deb_i2c|i2c_top:inst|cs.RD_ACK" uses code string "0100001"
- Info: State "|deb_i2c|i2c_top:inst|cs.RD_BYTE" uses code string "0010001"
- Info: State "|deb_i2c|i2c_top:inst|cs.DELAY" uses code string "0001001"
- Info: State "|deb_i2c|i2c_top:inst|cs.WR_ACK" uses code string "0000101"
- Info: State "|deb_i2c|i2c_top:inst|cs.WR_BYTE" uses code string "0000011"
- Info: State "|deb_i2c|i2c_top:inst|cs.SHOW" uses code string "1000001"
- Info: Selected Auto state machine encoding method for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state"
- Info: Encoding result for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state"
- Info: Completed encoding using 11 state bits
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ackn"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Stop"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_read"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_read"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Read_start"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_write"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Addr_write"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_write"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Write_start"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ready"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Idle"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Idle" uses code string "00000000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_read" uses code string "00100000001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_read" uses code string "00010000001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Stop" uses code string "01000000001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Read_start" uses code string "00001000001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_write" uses code string "00000100001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Addr_write" uses code string "00000010001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_write" uses code string "00000001001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Write_start" uses code string "00000000101"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ready" uses code string "00000000011"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ackn" uses code string "10000000001"
- Info: Selected Auto state machine encoding method for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state"
- Info: Encoding result for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state"
- Info: Completed encoding using 3 state bits
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_end"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_begin"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_end" uses code string "000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit" uses code string "110"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_begin" uses code string "101"
- Info: Selected Auto state machine encoding method for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state"
- Info: Encoding result for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state"
- Info: Completed encoding using 9 state bits
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_end"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit1"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit2"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit3"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit4"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit5"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit7"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_end" uses code string "000000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0" uses code string "110000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit1" uses code string "101000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit2" uses code string "100100000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit3" uses code string "100010000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit4" uses code string "100001000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit5" uses code string "100000100"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit7" uses code string "100000001"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6" uses code string "100000010"
- Info: Selected Auto state machine encoding method for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state"
- Info: Encoding result for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state"
- Info: Completed encoding using 3 state bits
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_end"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_begin"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_end" uses code string "000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit" uses code string "110"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_begin" uses code string "101"
- Info: Selected Auto state machine encoding method for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state"
- Info: Encoding result for state machine "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state"
- Info: Completed encoding using 10 state bits
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_end"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit0"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit1"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit2"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit3"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit4"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit5"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit6"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit7"
- Info: Encoded state bit "i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_begin"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_end" uses code string "0000000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit0" uses code string "1100000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit1" uses code string "1010000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit2" uses code string "1001000000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit3" uses code string "1000100000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit4" uses code string "1000010000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit5" uses code string "1000001000"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit6" uses code string "1000000100"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_bit7" uses code string "1000000010"
- Info: State "|deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state.sh8in_begin" uses code string "1000000001"
- Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus I2C_clk~0 that it feeds
- Warning: Reduced register "i2c_top:inst|i2c_wr:i2c_wr_inst|head_buf[0]" with stuck data_in port to stuck value GND
- Warning: TRI or OPNDRN buffers permanently enabled
- Warning: Node "I2C_clk~1"
- Info: Implemented 304 device resources after synthesis - the final resource count might be different
- Info: Implemented 2 input pins
- Info: Implemented 2 output pins
- Info: Implemented 2 bidirectional pins
- Info: Implemented 298 logic cells
- Info: Quartus II Analysis & Synthesis was successful. 0 errors, 45 warnings
- Info: Processing ended: Tue Jan 30 16:34:44 2007
- Info: Elapsed time: 00:00:08
