English
deb_i2c.fit.rpt
资源名称：I2C.rar [点击查看]
上传用户：lcztgy
上传日期：2007-03-17
资源大小：70k
文件大小：121k
源码类别：
并行计算
开发平台：
VHDL
- Fitter report for deb_i2c
- Tue Jan 30 16:34:54 2007
- Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Pin-Out File
- 5. Fitter Resource Usage Summary
- 6. Input Pins
- 7. Output Pins
- 8. Bidir Pins
- 9. I/O Bank Usage
- 10. All Package Pins
- 11. Output Pin Default Load For Reported TCO
- 12. Fitter Resource Utilization by Entity
- 13. Delay Chain Summary
- 14. Pad To Core Delay Chain Fanout
- 15. Control Signals
- 16. Global & Other Fast Signals
- 17. Non-Global High Fan-Out Signals
- 18. Interconnect Usage Summary
- 19. LAB Logic Elements
- 20. LAB-wide Signals
- 21. LAB Signals Sourced
- 22. LAB Signals Sourced Out
- 23. LAB Distinct Inputs
- 24. Fitter Device Options
- 25. Advanced Data - General
- 26. Advanced Data - Placement Preparation
- 27. Advanced Data - Placement
- 28. Advanced Data - Routing
- 29. Fitter Messages
- 30. Fitter Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2006 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +---------------------------------------------------------------------------------------+
- ; Fitter Summary ;
- +------------------------------------+--------------------------------------------------+
- ; Fitter Status ; Successful - Tue Jan 30 16:34:54 2007 ;
- ; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1.18 SJ Full Version ;
- ; Revision Name ; deb_i2c ;
- ; Top-level Entity Name ; deb_i2c ;
- ; Family ; Cyclone II ;
- ; Device ; EP2C8Q208C8 ;
- ; Timing Models ; Final ;
- ; Total logic elements ; 287 / 8,256 ( 3 % ) ;
- ; Total registers ; 153 ;
- ; Total pins ; 6 / 138 ( 4 % ) ;
- ; Total virtual pins ; 0 ;
- ; Total memory bits ; 0 / 165,888 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
- ; Total PLLs ; 0 / 2 ( 0 % ) ;
- +------------------------------------+--------------------------------------------------+
- +------------------------------------------------------------------------------------------------------------------+
- ; Fitter Settings ;
- +------------------------------------------------+--------------------------------+--------------------------------+
- ; Option ; Setting ; Default Value ;
- +------------------------------------------------+--------------------------------+--------------------------------+
- ; Device ; EP2C8Q208C8 ; ;
- ; Use smart compilation ; Off ; Off ;
- ; Router Timing Optimization Level ; Normal ; Normal ;
- ; Placement Effort Multiplier ; 1.0 ; 1.0 ;
- ; Router Effort Multiplier ; 1.0 ; 1.0 ;
- ; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
- ; Optimize Fast-Corner Timing ; Off ; Off ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; Optimize Timing ; Normal compilation ; Normal compilation ;
- ; Optimize IOC Register Placement for Timing ; On ; On ;
- ; Limit to One Fitting Attempt ; Off ; Off ;
- ; Final Placement Optimizations ; Automatically ; Automatically ;
- ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
- ; Fitter Initial Placement Seed ; 1 ; 1 ;
- ; PCI I/O ; Off ; Off ;
- ; Weak Pull-Up Resistor ; Off ; Off ;
- ; Enable Bus-Hold Circuitry ; Off ; Off ;
- ; Auto Global Memory Control Signals ; Off ; Off ;
- ; Auto Packed Registers -- Stratix II/Cyclone II ; Auto ; Auto ;
- ; Auto Delay Chains ; On ; On ;
- ; Auto Merge PLLs ; On ; On ;
- ; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
- ; Fitter Effort ; Auto Fit ; Auto Fit ;
- ; Physical Synthesis Effort Level ; Normal ; Normal ;
- ; Auto Global Clock ; On ; On ;
- ; Auto Global Register Control Signals ; On ; On ;
- ; Always Enable Input Buffers ; Off ; Off ;
- +------------------------------------------------+--------------------------------+--------------------------------+
- +--------------+
- ; Pin-Out File ;
- +--------------+
- The pin-out file can be found in D:/altera_6/works/ep2c8/I2C/deb_i2c.pin.
- +-------------------------------------------------------------------+
- ; Fitter Resource Usage Summary ;
- +---------------------------------------------+---------------------+
- ; Resource ; Usage ;
- +---------------------------------------------+---------------------+
- ; Total logic elements ; 287 / 8,256 ( 3 % ) ;
- ; -- Combinational with no register ; 134 ;
- ; -- Register only ; 8 ;
- ; -- Combinational with a register ; 145 ;
- ; ; ;
- ; Logic element usage by number of LUT inputs ; ;
- ; -- 4 input functions ; 159 ;
- ; -- 3 input functions ; 35 ;
- ; -- <=2 input functions ; 85 ;
- ; -- Register only ; 8 ;
- ; ; ;
- ; Logic elements by mode ; ;
- ; -- normal mode ; 228 ;
- ; -- arithmetic mode ; 51 ;
- ; ; ;
- ; Total registers ; 153 / 8,256 ( 2 % ) ;
- ; Total LABs ; 20 / 516 ( 4 % ) ;
- ; User inserted logic elements ; 0 ;
- ; Virtual pins ; 0 ;
- ; I/O pins ; 6 / 138 ( 4 % ) ;
- ; -- Clock pins ; 1 / 4 ( 25 % ) ;
- ; Global signals ; 2 ;
- ; M4Ks ; 0 / 36 ( 0 % ) ;
- ; Total memory bits ; 0 / 165,888 ( 0 % ) ;
- ; Total RAM block bits ; 0 / 165,888 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
- ; PLLs ; 0 / 2 ( 0 % ) ;
- ; Global clocks ; 2 / 8 ( 25 % ) ;
- ; Maximum fan-out node ; pld_CLEAR_n ;
- ; Maximum fan-out ; 130 ;
- ; Highest non-global fan-out signal ; pld_CLEAR_n ;
- ; Highest non-global fan-out ; 130 ;
- ; Total fan-out ; 1413 ;
- ; Average fan-out ; 3.16 ;
- +---------------------------------------------+---------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Input Pins ;
- +-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
- +-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
- ; clk1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
- ; pld_CLEAR_n ; 3 ; 1 ; 0 ; 18 ; 2 ; 130 ; 0 ; no ; no ; no ; no ; no ; Off ; LVTTL ; Off ; User ;
- +-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Output Pins ;
- +-------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
- +-------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
- ; HC_CP ; 164 ; 2 ; 30 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ; 0 pF ;
- ; HC_SI ; 165 ; 2 ; 30 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ; 0 pF ;
- +-------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Bidir Pins ;
- +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
- +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
- ; I2C_clk ; 197 ; 2 ; 5 ; 19 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ; 0 pF ;
- ; I2C_sda ; 195 ; 2 ; 9 ; 19 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 24mA ; Off ; User ; 0 pF ;
- +---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
- +-----------------------------------------------------------+
- ; I/O Bank Usage ;
- +----------+-----------------+---------------+--------------+
- ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
- +----------+-----------------+---------------+--------------+
- ; 1 ; 4 / 32 ( 13 % ) ; 3.3V ; -- ;
- ; 2 ; 4 / 35 ( 11 % ) ; 3.3V ; -- ;
- ; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
- ; 4 ; 0 / 36 ( 0 % ) ; 3.3V ; -- ;
- +----------+-----------------+---------------+--------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; All Package Pins ;
- +----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
- +----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- ; 1 ; 0 ; 1 ; +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; 2 ; 1 ; 1 ; +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; 3 ; 2 ; 1 ; pld_CLEAR_n ; input ; LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
- ; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
- ; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
- ; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
- ; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
- ; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
- ; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
- ; 23 ; 27 ; 1 ; clk1 ; input ; LVTTL ; ; Row I/O ; Y ; no ; Off ;
- ; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
- ; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 77 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 80 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 81 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 108 ; 106 ; 3 ; *~LVDS54p/nCEO~ / GND* ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
- ; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
- ; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
- ; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
- ; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 142 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 143 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 144 ; 142 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 145 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 146 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 147 ; 150 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 149 ; 151 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 150 ; 152 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
- ; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 164 ; 159 ; 2 ; HC_CP ; output ; LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; 165 ; 160 ; 2 ; HC_SI ; output ; LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 195 ; 187 ; 2 ; I2C_sda ; bidir ; LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 197 ; 191 ; 2 ; I2C_clk ; bidir ; LVTTL ; ; Column I/O ; Y ; no ; Off ;
- ; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- ; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
- +----------+------------+----------+-------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- +-------------------------------------------------------------------------------+
- ; Output Pin Default Load For Reported TCO ;
- +----------------------------------+-------+------------------------------------+
- ; I/O Standard ; Load ; Termination Resistance ;
- +----------------------------------+-------+------------------------------------+
- ; LVTTL ; 0 pF ; Not Available ;
- ; LVCMOS ; 0 pF ; Not Available ;
- ; 2.5 V ; 0 pF ; Not Available ;
- ; 1.8 V ; 0 pF ; Not Available ;
- ; 1.5 V ; 0 pF ; Not Available ;
- ; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
- ; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
- ; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
- ; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
- ; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
- ; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
- ; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
- ; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
- ; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
- ; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
- ; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
- ; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
- ; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
- ; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
- ; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
- ; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
- ; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
- ; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
- ; LVDS ; 0 pF ; 100 Ohm (Differential) ;
- ; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
- ; RSDS ; 0 pF ; 100 Ohm (Differential) ;
- ; Simple RSDS ; 0 pF ; Not Available ;
- ; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
- +----------------------------------+-------+------------------------------------+
- Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Resource Utilization by Entity ;
- +----------------------------------------+-------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------+
- ; Compilation Hierarchy Node ; Logic Cells ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ;
- +----------------------------------------+-------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------+
- ; |deb_i2c ; 287 (0) ; 279 (0) ; 153 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 134 (0) ; 8 (0) ; 145 (0) ; |deb_i2c ;
- ; |i2c_top:inst| ; 287 (85) ; 279 (69) ; 153 (64) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 134 (21) ; 8 (8) ; 145 (48) ; |deb_i2c|i2c_top:inst ;
- ; |hc164_driver:hc164_driver_inst| ; 54 (54) ; 54 (54) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 0 (0) ; 33 (33) ; |deb_i2c|i2c_top:inst|hc164_driver:hc164_driver_inst ;
- ; |i2c_wr:i2c_wr_inst| ; 156 (156) ; 156 (156) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 92 (92) ; 0 (0) ; 64 (64) ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst ;
- +----------------------------------------+-------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +--------------------------------------------------------------------------------------+
- ; Delay Chain Summary ;
- +-------------+----------+---------------+---------------+-----------------------+-----+
- ; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
- +-------------+----------+---------------+---------------+-----------------------+-----+
- ; clk1 ; Input ; 0 ; 0 ; -- ; -- ;
- ; pld_CLEAR_n ; Input ; 6 ; 6 ; -- ; -- ;
- ; HC_CP ; Output ; -- ; -- ; -- ; -- ;
- ; HC_SI ; Output ; -- ; -- ; -- ; -- ;
- ; I2C_sda ; Bidir ; 6 ; 6 ; -- ; -- ;
- ; I2C_clk ; Bidir ; 0 ; 0 ; -- ; -- ;
- +-------------+----------+---------------+---------------+-----------------------+-----+
- +-------------------------------------------------------------------------------------------------+
- ; Pad To Core Delay Chain Fanout ;
- +-------------------------------------------------------------------+-------------------+---------+
- ; Source Pin / Fanout ; Pad To Core Index ; Setting ;
- +-------------------------------------------------------------------+-------------------+---------+
- ; clk1 ; ; ;
- ; pld_CLEAR_n ; ; ;
- ; - i2c_top:inst|data_rep[14] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[13] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[12] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[11] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[10] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[9] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[8] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[7] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[6] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[5] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[4] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[3] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[2] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[1] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[0] ; 0 ; 6 ;
- ; - i2c_top:inst|data_rep[15] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|hc_cp ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|seg_led_num[0] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|seg_led_num[1] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|ack ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[1] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[2] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[4] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[3] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[15] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[5] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div ; 0 ; 6 ;
- ; - i2c_top:inst|show_ok ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[0] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[1] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[2] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[3] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[4] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[5] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[6] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[7] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[8] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[9] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[10] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[11] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[12] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[13] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[14] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[0] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[4] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[1] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[5] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[2] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[6] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[3] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[7] ; 0 ; 6 ;
- ; - i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[0] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Stop ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|ff ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ready ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ackn ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|scl ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_read ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~668 ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[10] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[7] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[9] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[8] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[6] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[5] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[4] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[3] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[1] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[2] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[0] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_cnt[11] ; 0 ; 6 ;
- ; - i2c_top:inst|cs.RD_ACK ; 0 ; 6 ;
- ; - i2c_top:inst|cs.WR_ACK ; 0 ; 6 ;
- ; - i2c_top:inst|cs.WR_BYTE ; 0 ; 6 ;
- ; - i2c_top:inst|cs.RD_BYTE ; 0 ; 6 ;
- ; - i2c_top:inst|cs.SHOW ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_write ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Read_start ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Write_start ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_read ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Addr_write ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_write ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_end ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Idle ; 0 ; 6 ;
- ; - i2c_top:inst|rd ; 0 ; 6 ;
- ; - i2c_top:inst|wr ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[1] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|link_write ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|link_stop ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|head_buf[1] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|link_head ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|link_sda ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~382 ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[8] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[0] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[1] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[11] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[3] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[5] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[2] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[4] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[6] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[7] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[9] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[10] ; 0 ; 6 ;
- ; - i2c_top:inst|clk_div_cnt[12] ; 0 ; 6 ;
- ; - i2c_top:inst|cs.IDLE ; 0 ; 6 ;
- ; - i2c_top:inst|cs.DELAY ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~388 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|rf ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|wf ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_bit ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state~767 ; 0 ; 6 ;
- ; - i2c_top:inst|wr_flag ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|stop_buf[0] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~546 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|stop_state.stop_begin ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|head_state~257 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit1 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit2 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit3 ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit4 ; 0 ; 6 ;
- ; - i2c_top:inst|addr[10] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit5 ; 0 ; 6 ;
- ; - i2c_top:inst|addr[9] ; 0 ; 6 ;
- ; - i2c_top:inst|addr[8] ; 0 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[0] ; 0 ; 6 ;
- ; I2C_sda ; ; ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[4]~669 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~670 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[5]~671 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[1]~672 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[6]~673 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[2]~674 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[7]~675 ; 1 ; 6 ;
- ; - i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[3]~676 ; 1 ; 6 ;
- ; I2C_clk ; ; ;
- +-------------------------------------------------------------------+-------------------+---------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Control Signals ;
- +---------------------------------------------------------+-------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
- ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
- +---------------------------------------------------------+-------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
- ; clk1 ; PIN_23 ; 38 ; Clock ; yes ; Global clock ; GCLK2 ; -- ;
- ; i2c_top:inst|Equal3~66 ; LCCOMB_X24_Y9_N20 ; 15 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|clk_div ; LCFF_X15_Y8_N1 ; 115 ; Clock ; yes ; Global clock ; GCLK3 ; -- ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[15] ; LCFF_X17_Y8_N31 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|Selector48~163 ; LCCOMB_X22_Y8_N16 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|ff ; LCFF_X22_Y8_N31 ; 51 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|head_state~257 ; LCCOMB_X23_Y8_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|link_sda ; LCFF_X22_Y9_N27 ; 3 ; Output enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_read ; LCFF_X19_Y8_N11 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~382 ; LCCOMB_X21_Y8_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~388 ; LCCOMB_X21_Y8_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~546 ; LCCOMB_X21_Y9_N0 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~547 ; LCCOMB_X19_Y9_N26 ; 7 ; Sync. load ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state~767 ; LCCOMB_X19_Y9_N20 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
- ; i2c_top:inst|show_ok ; LCFF_X18_Y8_N1 ; 19 ; Clock enable ; no ; -- ; -- ; -- ;
- ; pld_CLEAR_n ; PIN_3 ; 130 ; Async. clear, Clock enable ; no ; -- ; -- ; -- ;
- +---------------------------------------------------------+-------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
- +-----------------------------------------------------------------------------------------------------------------------+
- ; Global & Other Fast Signals ;
- +----------------------+----------------+---------+----------------------+------------------+---------------------------+
- ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
- +----------------------+----------------+---------+----------------------+------------------+---------------------------+
- ; clk1 ; PIN_23 ; 38 ; Global clock ; GCLK2 ; -- ;
- ; i2c_top:inst|clk_div ; LCFF_X15_Y8_N1 ; 115 ; Global clock ; GCLK3 ; -- ;
- +----------------------+----------------+---------+----------------------+------------------+---------------------------+
- +----------------------------------------------------------------------+
- ; Non-Global High Fan-Out Signals ;
- +------------------------------------------------------------+---------+
- ; Name ; Fan-Out ;
- +------------------------------------------------------------+---------+
- ; pld_CLEAR_n ; 130 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|ff ; 51 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|scl ; 35 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_read ; 24 ;
- ; i2c_top:inst|show_ok ; 19 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Addr_write ; 18 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Stop ; 18 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|Selector39~382 ; 17 ;
- ; i2c_top:inst|Equal3~66 ; 15 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ready ; 12 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~542 ; 11 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Idle ; 10 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_write ; 10 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Read_start ; 10 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|clk_cnt[15] ; 10 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Write_start ; 9 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ackn ; 9 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|seg_led_num[0] ; 9 ;
- ; I2C_sda~0 ; 8 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~382 ; 8 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|data_r[0]~668 ; 8 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|ack ; 8 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|seg_led_num[1] ; 8 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~547 ; 7 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit6 ; 7 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~546 ; 7 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]~543 ; 7 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|wf ; 7 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Data_write ; 7 ;
- ; i2c_top:inst|Equal0~108 ; 7 ;
- ; i2c_top:inst|Equal0~107 ; 7 ;
- ; i2c_top:inst|Equal0~106 ; 7 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[1] ; 7 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|Selector0~15 ; 7 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|Selector1~23 ; 7 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|Selector2~15 ; 7 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|Selector3~15 ; 7 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|Selector73~611 ; 6 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|Selector82~176 ; 6 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit7 ; 6 ;
- ; i2c_top:inst|wr ; 6 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_end ; 6 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ctrl_read ; 6 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|head_state.head_bit ; 6 ;
- ; i2c_top:inst|hc164_driver:hc164_driver_inst|tx_cnt[2] ; 6 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit5 ; 5 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit4 ; 5 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit3 ; 5 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit2 ; 5 ;
- ; i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit1 ; 5 ;
- +------------------------------------------------------------+---------+
- +-----------------------------------------------------+
- ; Interconnect Usage Summary ;
- +----------------------------+------------------------+
- ; Interconnect Resource Type ; Usage ;
- +----------------------------+------------------------+
- ; Block interconnects ; 306 / 26,052 ( 1 % ) ;
- ; C16 interconnects ; 4 / 1,156 ( < 1 % ) ;
- ; C4 interconnects ; 130 / 17,952 ( < 1 % ) ;
- ; Direct links ; 81 / 26,052 ( < 1 % ) ;
- ; Global clocks ; 2 / 8 ( 25 % ) ;
- ; Local interconnects ; 208 / 8,256 ( 3 % ) ;
- ; R24 interconnects ; 6 / 1,020 ( < 1 % ) ;
- ; R4 interconnects ; 166 / 22,440 ( < 1 % ) ;
- +----------------------------+------------------------+
- +----------------------------------------------------------------------------+
- ; LAB Logic Elements ;
- +---------------------------------------------+------------------------------+
- ; Number of Logic Elements (Average = 14.35) ; Number of LABs (Total = 20) ;
- +---------------------------------------------+------------------------------+
- ; 1 ; 2 ;
- ; 2 ; 0 ;
- ; 3 ; 0 ;
- ; 4 ; 0 ;
- ; 5 ; 0 ;
- ; 6 ; 0 ;
- ; 7 ; 0 ;
- ; 8 ; 0 ;
- ; 9 ; 0 ;
- ; 10 ; 0 ;
- ; 11 ; 0 ;
- ; 12 ; 0 ;
- ; 13 ; 1 ;
- ; 14 ; 0 ;
- ; 15 ; 0 ;
- ; 16 ; 17 ;
- +---------------------------------------------+------------------------------+
- +-------------------------------------------------------------------+
- ; LAB-wide Signals ;
- +------------------------------------+------------------------------+
- ; LAB-wide Signals (Average = 2.15) ; Number of LABs (Total = 20) ;
- +------------------------------------+------------------------------+
- ; 1 Async. clear ; 13 ;
- ; 1 Clock ; 16 ;
- ; 1 Clock enable ; 11 ;
- ; 2 Clocks ; 3 ;
- +------------------------------------+------------------------------+
- +-----------------------------------------------------------------------------+
- ; LAB Signals Sourced ;
- +----------------------------------------------+------------------------------+
- ; Number of Signals Sourced (Average = 21.80) ; Number of LABs (Total = 20) ;
- +----------------------------------------------+------------------------------+
- ; 0 ; 0 ;
- ; 1 ; 1 ;
- ; 2 ; 1 ;
- ; 3 ; 0 ;
- ; 4 ; 0 ;
- ; 5 ; 0 ;
- ; 6 ; 0 ;
- ; 7 ; 0 ;
- ; 8 ; 0 ;
- ; 9 ; 0 ;
- ; 10 ; 0 ;
- ; 11 ; 0 ;
- ; 12 ; 0 ;
- ; 13 ; 0 ;
- ; 14 ; 0 ;
- ; 15 ; 1 ;
- ; 16 ; 0 ;
- ; 17 ; 0 ;
- ; 18 ; 0 ;
- ; 19 ; 3 ;
- ; 20 ; 1 ;
- ; 21 ; 1 ;
- ; 22 ; 1 ;
- ; 23 ; 0 ;
- ; 24 ; 4 ;
- ; 25 ; 1 ;
- ; 26 ; 1 ;
- ; 27 ; 0 ;
- ; 28 ; 1 ;
- ; 29 ; 1 ;
- ; 30 ; 0 ;
- ; 31 ; 2 ;
- ; 32 ; 1 ;
- +----------------------------------------------+------------------------------+
- +--------------------------------------------------------------------------------+
- ; LAB Signals Sourced Out ;
- +-------------------------------------------------+------------------------------+
- ; Number of Signals Sourced Out (Average = 7.65) ; Number of LABs (Total = 20) ;
- +-------------------------------------------------+------------------------------+
- ; 0 ; 0 ;
- ; 1 ; 2 ;
- ; 2 ; 1 ;
- ; 3 ; 1 ;
- ; 4 ; 0 ;
- ; 5 ; 3 ;
- ; 6 ; 1 ;
- ; 7 ; 2 ;
- ; 8 ; 1 ;
- ; 9 ; 2 ;
- ; 10 ; 4 ;
- ; 11 ; 0 ;
- ; 12 ; 0 ;
- ; 13 ; 0 ;
- ; 14 ; 1 ;
- ; 15 ; 1 ;
- ; 16 ; 1 ;
- +-------------------------------------------------+------------------------------+
- +-----------------------------------------------------------------------------+
- ; LAB Distinct Inputs ;
- +----------------------------------------------+------------------------------+
- ; Number of Distinct Inputs (Average = 14.00) ; Number of LABs (Total = 20) ;
- +----------------------------------------------+------------------------------+
- ; 0 ; 0 ;
- ; 1 ; 0 ;
- ; 2 ; 1 ;
- ; 3 ; 1 ;
- ; 4 ; 1 ;
- ; 5 ; 0 ;
- ; 6 ; 1 ;
- ; 7 ; 0 ;
- ; 8 ; 2 ;
- ; 9 ; 1 ;
- ; 10 ; 0 ;
- ; 11 ; 1 ;
- ; 12 ; 1 ;
- ; 13 ; 2 ;
- ; 14 ; 0 ;
- ; 15 ; 0 ;
- ; 16 ; 2 ;
- ; 17 ; 0 ;
- ; 18 ; 0 ;
- ; 19 ; 1 ;
- ; 20 ; 2 ;
- ; 21 ; 2 ;
- ; 22 ; 0 ;
- ; 23 ; 0 ;
- ; 24 ; 0 ;
- ; 25 ; 0 ;
- ; 26 ; 0 ;
- ; 27 ; 0 ;
- ; 28 ; 1 ;
- ; 29 ; 0 ;
- ; 30 ; 1 ;
- +----------------------------------------------+------------------------------+
- +-------------------------------------------------------------------------+
- ; Fitter Device Options ;
- +----------------------------------------------+--------------------------+
- ; Option ; Setting ;
- +----------------------------------------------+--------------------------+
- ; Enable user-supplied start-up clock (CLKUSR) ; Off ;
- ; Enable device-wide reset (DEV_CLRn) ; Off ;
- ; Enable device-wide output enable (DEV_OE) ; Off ;
- ; Enable INIT_DONE output ; Off ;
- ; Configuration scheme ; Active Serial ;
- ; Error detection CRC ; Off ;
- ; Reserve nCEO pin after configuration ; As output driving ground ;
- ; Reserve all unused pins ; As input tri-stated ;
- ; Base pin-out file on sameframe device ; Off ;
- +----------------------------------------------+--------------------------+
- +----------------------------+
- ; Advanced Data - General ;
- +--------------------+-------+
- ; Name ; Value ;
- +--------------------+-------+
- ; Status Code ; 0 ;
- ; Desired User Slack ; 0 ;
- ; Fit Attempts ; 1 ;
- +--------------------+-------+
- +-------------------------------------------------------------------------------------+
- ; Advanced Data - Placement Preparation ;
- +------------------------------------------------------------------+------------------+
- ; Name ; Value ;
- +------------------------------------------------------------------+------------------+
- ; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
- ; Mid Wire Use - Fit Attempt 1 ; 1 ;
- ; Mid Slack - Fit Attempt 1 ; -8354 ;
- ; Internal Atom Count - Fit Attempt 1 ; 433 ;
- ; LE/ALM Count - Fit Attempt 1 ; 288 ;
- ; LAB Count - Fit Attempt 1 ; 21 ;
- ; Outputs per Lab - Fit Attempt 1 ; 7.286 ;
- ; Inputs per LAB - Fit Attempt 1 ; 12.286 ;
- ; Global Inputs per LAB - Fit Attempt 1 ; 1.048 ;
- ; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:20;1:1 ;
- ; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2;1:5;2:11;3:3 ;
- ; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2;1:5;2:11;3:3 ;
- ; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:21 ;
- ; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2;1:15;2:4 ;
- ; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2;1:10;2:9 ;
- ; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:6;1:12;2:3 ;
- ; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2;1:5;2:14 ;
- ; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2;1:16;2:3 ;
- ; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:13;1:8 ;
- ; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:18;1:3 ;
- ; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:21 ;
- ; LEs in Chains - Fit Attempt 1 ; 56 ;
- ; LEs in Long Chains - Fit Attempt 1 ; 0 ;
- ; LABs with Chains - Fit Attempt 1 ; 5 ;
- ; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
- ; Time - Fit Attempt 1 ; 0 ;
- ; Time in tsm_tan.dll - Fit Attempt 1 ; 0.047 ;
- +------------------------------------------------------------------+------------------+
- +----------------------------------------------+
- ; Advanced Data - Placement ;
- +-------------------------------------+--------+
- ; Name ; Value ;
- +-------------------------------------+--------+
- ; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
- ; Early Wire Use - Fit Attempt 1 ; 1 ;
- ; Early Slack - Fit Attempt 1 ; -10466 ;
- ; Auto Fit Point 3 - Fit Attempt 1 ; ff ;
- ; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
- ; Mid Wire Use - Fit Attempt 1 ; 1 ;
- ; Mid Slack - Fit Attempt 1 ; -7102 ;
- ; Late Wire Use - Fit Attempt 1 ; 1 ;
- ; Late Slack - Fit Attempt 1 ; -7102 ;
- ; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
- ; Time - Fit Attempt 1 ; 0 ;
- ; Time in tsm_tan.dll - Fit Attempt 1 ; 0.062 ;
- +-------------------------------------+--------+
- +---------------------------------------------+
- ; Advanced Data - Routing ;
- +-------------------------------------+-------+
- ; Name ; Value ;
- +-------------------------------------+-------+
- ; Early Slack - Fit Attempt 1 ; -5156 ;
- ; Early Wire Use - Fit Attempt 1 ; 1 ;
- ; Peak Regional Wire - Fit Attempt 1 ; 2 ;
- ; Mid Slack - Fit Attempt 1 ; -6179 ;
- ; Late Slack - Fit Attempt 1 ; -6179 ;
- ; Late Wire Use - Fit Attempt 1 ; 1 ;
- ; Time - Fit Attempt 1 ; 1 ;
- ; Time in tsm_tan.dll - Fit Attempt 1 ; 0.266 ;
- +-------------------------------------+-------+
- +-----------------+
- ; Fitter Messages ;
- +-----------------+
- Info: *******************************************************************
- Info: Running Quartus II Fitter
- Info: Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
- Info: Processing started: Tue Jan 30 16:34:47 2007
- Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off deb_i2c -c deb_i2c
- Info: Selected device EP2C8Q208C8 for design "deb_i2c"
- Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
- Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
- Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info: Device EP2C5Q208C8 is compatible
- Info: Device EP2C5Q208I8 is compatible
- Info: Device EP2C8Q208I8 is compatible
- Info: Automatically promoted node clk1 (placed in PIN 23 (CLK0, LVDSCLK0p, Input))
- Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
- Info: Automatically promoted node i2c_top:inst|clk_div
- Info: Automatically promoted destinations to use location or clock signal Global Clock
- Info: Following destination nodes may be non-global or may not use global or regional clocks
- Info: Destination node i2c_top:inst|clk_div~43
- Info: Starting register packing
- Info: Finished register packing: elapsed time is 00:00:00
- Extra Info: No registers were packed into other blocks
- Warning: Ignored locations or region assignments to the following nodes
- Warning: Node "Buzzer" is assigned to location or region, but does not exist in design
- Warning: Node "DS_a" is assigned to location or region, but does not exist in design
- Warning: Node "DS_b" is assigned to location or region, but does not exist in design
- Warning: Node "DS_c" is assigned to location or region, but does not exist in design
- Warning: Node "DS_d" is assigned to location or region, but does not exist in design
- Warning: Node "DS_e" is assigned to location or region, but does not exist in design
- Warning: Node "DS_f" is assigned to location or region, but does not exist in design
- Warning: Node "DS_g" is assigned to location or region, but does not exist in design
- Warning: Node "FA[0]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[10]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[11]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[12]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[13]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[14]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[15]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[16]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[17]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[18]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[19]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[1]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[20]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[21]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[22]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[2]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[3]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[4]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[5]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[6]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[7]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[8]" is assigned to location or region, but does not exist in design
- Warning: Node "FA[9]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[0]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[1]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[2]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[3]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[4]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[5]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[6]" is assigned to location or region, but does not exist in design
- Warning: Node "FD[7]" is assigned to location or region, but does not exist in design
- Warning: Node "Flash_CSn" is assigned to location or region, but does not exist in design
- Warning: Node "Flash_OEn" is assigned to location or region, but does not exist in design
- Warning: Node "Flash_WEn" is assigned to location or region, but does not exist in design
- Warning: Node "IrDA_RX" is assigned to location or region, but does not exist in design
- Warning: Node "IrDA_Rx" is assigned to location or region, but does not exist in design
- Warning: Node "IrDA_TX" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[0]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[1]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[2]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[3]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[4]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[5]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[6]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_D[7]" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_EN" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_RS" is assigned to location or region, but does not exist in design
- Warning: Node "LCM_RW" is assigned to location or region, but does not exist in design
- Warning: Node "LED[0]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[1]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[2]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[3]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[4]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[5]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[6]" is assigned to location or region, but does not exist in design
- Warning: Node "LED[7]" is assigned to location or region, but does not exist in design
- Warning: Node "PS2_CLK" is assigned to location or region, but does not exist in design
- Warning: Node "PS2_TATA" is assigned to location or region, but does not exist in design
- Warning: Node "UART_R" is assigned to location or region, but does not exist in design
- Warning: Node "UART_T" is assigned to location or region, but does not exist in design
- Warning: Node "Uart_R" is assigned to location or region, but does not exist in design
- Warning: Node "Uart_T" is assigned to location or region, but does not exist in design
- Warning: Node "VGA_B" is assigned to location or region, but does not exist in design
- Warning: Node "VGA_G" is assigned to location or region, but does not exist in design
- Warning: Node "VGA_HS" is assigned to location or region, but does not exist in design
- Warning: Node "VGA_R" is assigned to location or region, but does not exist in design
- Warning: Node "VGA_VS" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO10" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO11" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO12" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO13" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO14" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO15" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO16" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO17" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO18" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO19" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO20" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO21" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO22" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO23" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO24" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO6" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO7" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO8" is assigned to location or region, but does not exist in design
- Warning: Node "VS1_IO9" is assigned to location or region, but does not exist in design
- Warning: Node "clk2" is assigned to location or region, but does not exist in design
- Warning: Node "clk3" is assigned to location or region, but does not exist in design
- Warning: Node "clk4" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[0]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[10]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[11]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[12]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[1]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[2]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[3]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[4]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[5]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[6]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[7]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[8]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_A[9]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_BA[0]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_BA[1]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_CASn" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_CKE" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_CLK" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_CSn" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_DQM[0]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_DQM[1]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_DQM[2]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_DQM[3]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[0]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[10]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[11]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[12]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[13]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[14]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[15]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[16]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[17]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[18]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[19]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[1]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[20]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[21]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[22]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[23]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[24]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[25]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[26]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[27]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[28]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[29]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[2]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[30]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[31]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[3]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[4]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[5]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[6]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[7]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[8]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_D[9]" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_RASn" is assigned to location or region, but does not exist in design
- Warning: Node "sdram_WEn" is assigned to location or region, but does not exist in design
- Warning: Node "user_PB[0]" is assigned to location or region, but does not exist in design
- Warning: Node "user_PB[1]" is assigned to location or region, but does not exist in design
- Warning: Node "user_PB[2]" is assigned to location or region, but does not exist in design
- Warning: Node "user_PB[3]" is assigned to location or region, but does not exist in design
- Info: Fitter placement preparation operations beginning
- Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
- Info: Fitter placement operations beginning
- Info: Fitter placement was successful
- Info: Fitter placement operations ending: elapsed time is 00:00:00
- Info: Estimated most critical path is register to register delay of 7.374 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y8; Fanout = 9; REG Node = 'i2c_top:inst|i2c_wr:i2c_wr_inst|main_state.Ackn'
- Info: 2: + IC(1.350 ns) + CELL(0.624 ns) = 1.974 ns; Loc. = LAB_X23_Y9; Fanout = 2; COMB Node = 'i2c_top:inst|i2c_wr:i2c_wr_inst|WideOr25~40'
- Info: 3: + IC(1.698 ns) + CELL(0.202 ns) = 3.874 ns; Loc. = LAB_X19_Y8; Fanout = 3; COMB Node = 'i2c_top:inst|i2c_wr:i2c_wr_inst|Selector73~609'
- Info: 4: + IC(1.694 ns) + CELL(0.206 ns) = 5.774 ns; Loc. = LAB_X21_Y9; Fanout = 6; COMB Node = 'i2c_top:inst|i2c_wr:i2c_wr_inst|Selector73~611'
- Info: 5: + IC(1.286 ns) + CELL(0.206 ns) = 7.266 ns; Loc. = LAB_X19_Y9; Fanout = 1; COMB Node = 'i2c_top:inst|i2c_wr:i2c_wr_inst|Selector73~610'
- Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 7.374 ns; Loc. = LAB_X19_Y9; Fanout = 4; REG Node = 'i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state.sh8out_bit0'
- Info: Total cell delay = 1.346 ns ( 18.25 % )
- Info: Total interconnect delay = 6.028 ns ( 81.75 % )
- Info: Fitter routing operations beginning
- Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
- Info: The peak interconnect region extends from location x11_y0 to location x22_y9
- Info: Fitter routing operations ending: elapsed time is 00:00:01
- Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info: Optimizations that may affect the design's routability were skipped
- Info: Optimizations that may affect the design's timing were skipped
- Info: Started post-fitting delay annotation
- Warning: Found 4 output pins without output pin load capacitance assignment
- Info: Pin "HC_CP" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "HC_SI" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "I2C_sda" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Pin "I2C_clk" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
- Info: Delay annotation completed successfully
- Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
- Info: Pin I2C_clk has a permanently enabled output enable
- Info: Following groups of pins have the same output enable
- Info: Following pins have the same output enable: i2c_top:inst|i2c_wr:i2c_wr_inst|link_sda
- Info: Type bidirectional pin I2C_sda uses the LVTTL I/O standard
- Info: Quartus II Fitter was successful. 0 errors, 161 warnings
- Info: Processing ended: Tue Jan 30 16:34:54 2007
- Info: Elapsed time: 00:00:08
- +----------------------------+
- ; Fitter Suppressed Messages ;
- +----------------------------+
- The suppressed messages can be found in D:/altera_6/works/ep2c8/I2C/deb_i2c.fit.smsg.
