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i2c_top.v
资源名称：I2C.rar　[点击查看]
上传用户：lcztgy
上传日期：2007-03-17
资源大小：70k
文件大小：9k
源码类别：

并行计算

开发平台：

VHDL

i2c_top.v：源码内容
  1. ////////////////////////////////////////////////////////////////////////////////
  2. //                __     ___ _               ___ ____                         //
  3. //                    / (_) |__   ___  ___|_ _/ ___|                        //
  4. //                   / /| | '_  / _ / __|| | |                            //
  5. //                   V / | | |_) |  __/__ | | |___                         //
  6. //                   _/  |_|_.__/ ___||___/_______|                        //
  7. //                                                                            //
  8. ////////////////////////////////////////////////////////////////////////////////
  9. //     Copyright (C) 2003-2006 VibesIC, Inc.   All rights reserved.           //
  10. //----------------------------------------------------------------------------//
  11. // This source code is provided by VibesIC,and be verified on VibesIC FPGA    //
  12. // development kit. The source code may be used and distributed without       //
  13. // restriction provided that this copyright statement is not removed from the //
  14. // file and that any derivative work contains the original copyright notice   //
  15. // and the associated disclaimer.                                             //
  16. //----------------------------------------------------------------------------//
  17. // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED     //
  18. // WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF       //
  19. // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE//
  20. // AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,     //
  21. // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,//
  22. // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,OR PROFITS; //
  23. // OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,   //
  24. // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR    //
  25. // OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF     //
  26. // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                 //
  27. //----------------------------------------------------------------------------//
  28. // 本设计由威百仕( VibesIC )提供，并在其产品中验证通过，您可以在此基础上修改，//
  29. // 复制并分发,但请您保留版权声明部分。我们并不承诺本设计可以用做商业产品，同时//
  30. // 我们不保证设计的通用性。为了方便更新以及修改请保留设计的版本信息，并对自行 //
  31. // 修改部分添加足够的注释。对设计如有其他建议,请到网站进行讨论。              //
  32. //                                                                            //
  33. ////////////////////////////////////////////////////////////////////////////////
  34. //  Company:       www.richic.com                                             //
  35. //  Company bbs:   www.edacn.net                                              //
  36. //  Engineer:      alex_yang                                                  //
  37. //                                                                            //
  38. //  Target Device: XC3S400-PQ208                                              //
  39. //  Tool versions: Simulation:    ModelSim SE 6.2a                            //
  40. //                 Synthesis:     XST(ise8.1...sp3)                           //
  41. //                 Place&Routing: ISE8.1...sp3                                //
  42. //                 Others tools:  UltraEdit-32 12.10a                         //
  43. //  Create Date:   2006-12-21 14:19                                           //
  44. //  Description:                                                              //
  45. //                                                                            //
  46. //  LOG:                                                                      //
  47. //       1. Revision 1.0 (Initial version)  2006-12-21 14:19  alex_yang       //
  48. //                                                                            //
  49. //       2. Revision 1.1  2006-12-26 9:11   alex_yang                         //
  50. //          Modify for VX-SP306                                               //
  51. ////////////////////////////////////////////////////////////////////////////////
  52. `timescale 1ns/1ns
  54. module i2c_top(clk, rst_n, sda, scl, hc_cp, hc_si);
  55.   input  clk;
  56.   input  rst_n;
  57.   inout  sda;
  58.   output scl;
  59.   output hc_cp;
  60.   output hc_si;
  62.   reg  wr;  //write eeprom command
  63.   reg  rd;  //read eeprom command
  64.   reg  [10:0] addr;   //write or read address.
  65.   reg  [7:0]  data_w; //write data to eeprom
  66.   wire ack;           //i2c write or read complete
  67.   wire [7:0] data_r;  //read data from eeprom
  68.  
  69.   reg [15:0] data_rep; //存储显示在七段数码管上的数据
  70.   reg show_ok;   //正确显示后的标志
  71.   reg wr_flag;   //记录是否已经发送过write,read command
  72.   
  73.   reg [6:0]  cs,ns;
  74.   parameter  IDLE    = 7'b0000001,
  75.              WR_BYTE = 7'b0000010,
  76.              WR_ACK  = 7'b0000100,
  77.              DELAY   = 7'B0001000,
  78.              RD_BYTE = 7'b0010000,
  79.              RD_ACK  = 7'b0100000,
  80.              SHOW    = 7'b1000000;
  81.              
  83.   //-------------产生时钟clk分频-----------------------------------------------
  84.   reg [11:0] clk_cnt; 
  85.   reg [12:0] clk_div_cnt;
  86.   reg clk_div;
  87.   always @ (posedge clk or negedge rst_n)
  88.     if (!rst_n) 
  89.       clk_cnt <= 12'd0;
  90.     else if (clk_cnt == 12'd1250)  //get 20khz SCL clock  
  91.       clk_cnt <= 12'd0;
  92.     else 
  93.       clk_cnt <= clk_cnt + 1'b1;
  94.       
  95.   always @ (posedge clk or negedge rst_n)
  96.     if (!rst_n)
  97.       clk_div <= 1'b0;
  98.     else if (clk_cnt == 12'd1250)
  99.       clk_div <= ~clk_div;       //20khz
  100.       
  101.   always @ (posedge clk_div or negedge rst_n)
  102.     if (!rst_n)
  103.       clk_div_cnt <= 13'd0;
  104.     else
  105.       clk_div_cnt <= clk_div_cnt + 1'b1;
  106.       
  107.   //---------State machine------------------
  108.   always @ (posedge clk_div or negedge rst_n)
  109.     if (!rst_n)
  110.       cs <= IDLE;
  111.     else 
  112.       cs <= ns;
  113.       
  114.   always @ ( * )
  115.     case (cs)
  116.       IDLE:
  117.         if (clk_div_cnt == 13'd1000)
  118.           ns = WR_BYTE;
  119.         else
  120.           ns = IDLE;
  121.       WR_BYTE:
  122.         if (ack)
  123.           ns = WR_ACK;
  124.         else
  125.           ns = WR_BYTE;
  126.       WR_ACK:
  127.         if (!ack)
  128.             ns = DELAY;
  129.         else
  130.           ns = WR_ACK;
  131.       DELAY://eeprom写数据需要时间(请参考SPEC),故：等待数据写完后再进行读操作
  132.         if (clk_div_cnt == 13'd1300)
  133.           ns = RD_BYTE;
  134.         else
  135.           ns = DELAY;
  136.       RD_BYTE:
  137.         if (ack)
  138.           ns = RD_ACK;
  139.         else
  140.           ns = RD_BYTE;
  141.       RD_ACK:
  142.         if (!ack)
  143.           ns = SHOW;
  144.         else
  145.           ns = RD_ACK;
  146.       SHOW:
  147.         if (show_ok)
  148.           ns = IDLE;
  149.         else
  150.           ns = SHOW;
  151.       default:
  152.         ns = IDLE;
  153.     endcase
  154.     
  155.   always @ (posedge clk_div or negedge rst_n)
  156.     if (!rst_n)
  157.       begin
  158.         wr <= 1'b0;
  159.         rd <= 1'b0;
  160.         addr <= 11'd0;
  161.         data_w <= 8'd0;
  162. //        data_w <= 8'h58;
  163.         show_ok <= 1'b0;
  164.         wr_flag <= 1'b0;
  165.       end
  166.     else if (data_w == 8'd255) //计数到255就重新开始
  167.       begin
  168.         addr <= 11'd0;
  169.         data_w <= 8'd0;
  170. //        data_w <= 8'h58;
  171.       end
  172.     else
  173.       case (cs)
  174.         IDLE:
  175.           begin
  176.             wr <= 1'b0;
  177.             rd <= 1'b0;
  178.             show_ok <= 1'b0;
  179.             wr_flag <= 1'b0;
  180.           end
  181.         WR_BYTE:
  182.           if (wr_flag == 1'b0)
  183.             begin
  184.               wr <= 1'b1;
  185.               wr_flag <= 1'b1;
  186.             end
  187.           else
  188.             wr <= 1'b0;
  189.         WR_ACK:
  190.           wr_flag <= 1'b0;
  191.         DELAY:
  192.           begin
  193.             wr <= 1'b0;
  194.             rd <= 1'b0;
  195.             show_ok <= 1'b0;
  196.             wr_flag <= 1'b0;
  197.           end
  198.         RD_BYTE:
  199.           if (wr_flag == 1'b0)
  200.             begin
  201.               rd <= 1'b1;
  202.               wr_flag <= 1'b1;
  203.             end
  204.           else
  205.             rd <= 1'b0;
  206.         RD_ACK:
  207.           begin
  208.             wr_flag <= 1'b0;
  209.             show_ok <= 1'b1; 
  210.           end
  211.         SHOW:
  212.           begin
  213.             show_ok <= 1'b0;
  214.             addr <= addr + 1'b1;
  215.             data_w <= data_w + 1'b1;
  216.           end
  217.         default:
  218.           begin
  219.             wr <= 1'b0;
  220.             rd <= 1'b0;
  221.             show_ok <= 1'b0;
  222.             wr_flag <= 1'b0;
  223.           end
  224.       endcase
  225.       
  226.   always @ (posedge clk_div or negedge rst_n)
  227.     if (!rst_n)
  228.       data_rep <=16'h0000;
  229.     else if (show_ok)
  230.       data_rep <= {data_w,data_r}; //将写入eeprom和从eeprom中读出的数据进行对比输出
  231.     
  232.   // ---------------------------------------------------------------------------
  233.   // 例化EEPROM: 24C02的驱动程序
  234.   // ---------------------------------------------------------------------------
  235.   i2c_wr i2c_wr_inst(
  236.       .clk          (clk_div),
  237.       .rst_n        (rst_n),
  238.       .wr           (wr),
  239.     .rd           (rd),
  240.     .addr         (addr),
  241.     .data_w       (data_w),
  242.     .data_r       (data_r),
  243.     .ack          (ack),
  244.       .scl          (scl),
  245.       .sda          (sda)
  246.     );
  248.   // ---------------------------------------------------------------------------
  249.   // 例化hc164的驱动程序
  250.   // ---------------------------------------------------------------------------
  252.   hc164_driver hc164_driver_inst(
  253.       .clk         ( clk ),
  254.       .rst_n       ( rst_n ),
  255.       .led         ( {4{ ack }} ),
  256.       .dot         ( 4'b0000 ),
  257.       .seg_value   ( data_rep ),
  258.       .hc_cp       ( hc_cp ), 
  259.       .hc_si       ( hc_si )  
  260.       );
  261.       
  262.       
  263. endmodule