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DAC960.h
资源名称：block.rar　[点击查看]
上传用户：ajay2009
上传日期：2009-05-22
资源大小：495k
文件大小：149k
源码类别：

驱动编程

开发平台：

Unix_Linux

DAC960.h：源码内容
  2. /*
  3.   Define the DAC960 Driver Command Types.
  4. */
  6. typedef enum
  7. {
  8.   DAC960_ReadCommand = 1,
  9.   DAC960_WriteCommand = 2,
  10.   DAC960_ReadRetryCommand = 3,
  11.   DAC960_WriteRetryCommand = 4,
  12.   DAC960_MonitoringCommand = 5,
  13.   DAC960_ImmediateCommand = 6,
  14.   DAC960_QueuedCommand = 7
  15. }
  16. DAC960_CommandType_T;
  19. /*
  20.   Define the DAC960 Driver Command structure.
  21. */
  23. typedef struct DAC960_Command
  24. {
  25.   int CommandIdentifier;
  26.   DAC960_CommandType_T CommandType;
  27.   struct DAC960_Controller *Controller;
  28.   struct DAC960_Command *Next;
  29.   struct completion *Completion;
  30.   unsigned int LogicalDriveNumber;
  31.   unsigned int BlockNumber;
  32.   unsigned int BlockCount;
  33.   unsigned int SegmentCount;
  34.   int DmaDirection;
  35.   struct scatterlist *cmd_sglist;
  36.   struct request *Request;
  37.   union {
  38.     struct {
  39.       DAC960_V1_CommandMailbox_T CommandMailbox;
  40.       DAC960_V1_KernelCommand_T *KernelCommand;
  41.       DAC960_V1_CommandStatus_T CommandStatus;
  42.       DAC960_V1_ScatterGatherSegment_T *ScatterGatherList;
  43.       dma_addr_t ScatterGatherListDMA;
  44.       struct scatterlist ScatterList[DAC960_V1_ScatterGatherLimit];
  45.       unsigned int EndMarker[0];
  46.     } V1;
  47.     struct {
  48.       DAC960_V2_CommandMailbox_T CommandMailbox;
  49.       DAC960_V2_KernelCommand_T *KernelCommand;
  50.       DAC960_V2_CommandStatus_T CommandStatus;
  51.       unsigned char RequestSenseLength;
  52.       int DataTransferResidue;
  53.       DAC960_V2_ScatterGatherSegment_T *ScatterGatherList;
  54.       dma_addr_t ScatterGatherListDMA;
  55.       DAC960_SCSI_RequestSense_T *RequestSense;
  56.       dma_addr_t RequestSenseDMA;
  57.       struct scatterlist ScatterList[DAC960_V2_ScatterGatherLimit];
  58.       unsigned int EndMarker[0];
  59.     } V2;
  60.   } FW;
  61. }
  62. DAC960_Command_T;
  65. /*
  66.   Define the DAC960 Driver Controller structure.
  67. */
  69. typedef struct DAC960_Controller
  70. {
  71.   void __iomem *BaseAddress;
  72.   void __iomem *MemoryMappedAddress;
  73.   DAC960_FirmwareType_T FirmwareType;
  74.   DAC960_HardwareType_T HardwareType;
  75.   DAC960_IO_Address_T IO_Address;
  76.   DAC960_PCI_Address_T PCI_Address;
  77.   struct pci_dev *PCIDevice;
  78.   unsigned char ControllerNumber;
  79.   unsigned char ControllerName[4];
  80.   unsigned char ModelName[20];
  81.   unsigned char FullModelName[28];
  82.   unsigned char FirmwareVersion[12];
  83.   unsigned char Bus;
  84.   unsigned char Device;
  85.   unsigned char Function;
  86.   unsigned char IRQ_Channel;
  87.   unsigned char Channels;
  88.   unsigned char Targets;
  89.   unsigned char MemorySize;
  90.   unsigned char LogicalDriveCount;
  91.   unsigned short CommandAllocationGroupSize;
  92.   unsigned short ControllerQueueDepth;
  93.   unsigned short DriverQueueDepth;
  94.   unsigned short MaxBlocksPerCommand;
  95.   unsigned short ControllerScatterGatherLimit;
  96.   unsigned short DriverScatterGatherLimit;
  97.   u64 BounceBufferLimit;
  98.   unsigned int CombinedStatusBufferLength;
  99.   unsigned int InitialStatusLength;
  100.   unsigned int CurrentStatusLength;
  101.   unsigned int ProgressBufferLength;
  102.   unsigned int UserStatusLength;
  103.   struct dma_loaf DmaPages;
  104.   unsigned long MonitoringTimerCount;
  105.   unsigned long PrimaryMonitoringTime;
  106.   unsigned long SecondaryMonitoringTime;
  107.   unsigned long ShutdownMonitoringTimer;
  108.   unsigned long LastProgressReportTime;
  109.   unsigned long LastCurrentStatusTime;
  110.   boolean ControllerInitialized;
  111.   boolean MonitoringCommandDeferred;
  112.   boolean EphemeralProgressMessage;
  113.   boolean DriveSpinUpMessageDisplayed;
  114.   boolean MonitoringAlertMode;
  115.   boolean SuppressEnclosureMessages;
  116.   struct timer_list MonitoringTimer;
  117.   struct gendisk *disks[DAC960_MaxLogicalDrives];
  118.   struct pci_pool *ScatterGatherPool;
  119.   DAC960_Command_T *FreeCommands;
  120.   unsigned char *CombinedStatusBuffer;
  121.   unsigned char *CurrentStatusBuffer;
  122.   struct request_queue *RequestQueue[DAC960_MaxLogicalDrives];
  123.   int req_q_index;
  124.   spinlock_t queue_lock;
  125.   wait_queue_head_t CommandWaitQueue;
  126.   wait_queue_head_t HealthStatusWaitQueue;
  127.   DAC960_Command_T InitialCommand;
  128.   DAC960_Command_T *Commands[DAC960_MaxDriverQueueDepth];
  129.   struct proc_dir_entry *ControllerProcEntry;
  130.   boolean LogicalDriveInitiallyAccessible[DAC960_MaxLogicalDrives];
  131.   void (*QueueCommand)(DAC960_Command_T *Command);
  132.   boolean (*ReadControllerConfiguration)(struct DAC960_Controller *);
  133.   boolean (*ReadDeviceConfiguration)(struct DAC960_Controller *);
  134.   boolean (*ReportDeviceConfiguration)(struct DAC960_Controller *);
  135.   void (*QueueReadWriteCommand)(DAC960_Command_T *Command);
  136.   union {
  137.     struct {
  138.       unsigned char GeometryTranslationHeads;
  139.       unsigned char GeometryTranslationSectors;
  140.       unsigned char PendingRebuildFlag;
  141.       unsigned short StripeSize;
  142.       unsigned short SegmentSize;
  143.       unsigned short NewEventLogSequenceNumber;
  144.       unsigned short OldEventLogSequenceNumber;
  145.       unsigned short DeviceStateChannel;
  146.       unsigned short DeviceStateTargetID;
  147.       boolean DualModeMemoryMailboxInterface;
  148.       boolean BackgroundInitializationStatusSupported;
  149.       boolean SAFTE_EnclosureManagementEnabled;
  150.       boolean NeedLogicalDriveInformation;
  151.       boolean NeedErrorTableInformation;
  152.       boolean NeedDeviceStateInformation;
  153.       boolean NeedDeviceInquiryInformation;
  154.       boolean NeedDeviceSerialNumberInformation;
  155.       boolean NeedRebuildProgress;
  156.       boolean NeedConsistencyCheckProgress;
  157.       boolean NeedBackgroundInitializationStatus;
  158.       boolean StartDeviceStateScan;
  159.       boolean RebuildProgressFirst;
  160.       boolean RebuildFlagPending;
  161.       boolean RebuildStatusPending;
  163.       dma_addr_t FirstCommandMailboxDMA;
  164.       DAC960_V1_CommandMailbox_T *FirstCommandMailbox;
  165.       DAC960_V1_CommandMailbox_T *LastCommandMailbox;
  166.       DAC960_V1_CommandMailbox_T *NextCommandMailbox;
  167.       DAC960_V1_CommandMailbox_T *PreviousCommandMailbox1;
  168.       DAC960_V1_CommandMailbox_T *PreviousCommandMailbox2;
  170.       dma_addr_t FirstStatusMailboxDMA;
  171.       DAC960_V1_StatusMailbox_T *FirstStatusMailbox;
  172.       DAC960_V1_StatusMailbox_T *LastStatusMailbox;
  173.       DAC960_V1_StatusMailbox_T *NextStatusMailbox;
  175.       DAC960_V1_DCDB_T *MonitoringDCDB;
  176.       dma_addr_t MonitoringDCDB_DMA;
  178.       DAC960_V1_Enquiry_T Enquiry;
  179.       DAC960_V1_Enquiry_T *NewEnquiry;
  180.       dma_addr_t NewEnquiryDMA;
  182.       DAC960_V1_ErrorTable_T ErrorTable;
  183.       DAC960_V1_ErrorTable_T *NewErrorTable;
  184.       dma_addr_t NewErrorTableDMA;
  186.       DAC960_V1_EventLogEntry_T *EventLogEntry;
  187.       dma_addr_t EventLogEntryDMA;
  189.       DAC960_V1_RebuildProgress_T *RebuildProgress;
  190.       dma_addr_t RebuildProgressDMA;
  191.       DAC960_V1_CommandStatus_T LastRebuildStatus;
  192.       DAC960_V1_CommandStatus_T PendingRebuildStatus;
  194.       DAC960_V1_LogicalDriveInformationArray_T LogicalDriveInformation;
  195.       DAC960_V1_LogicalDriveInformationArray_T *NewLogicalDriveInformation;
  196.       dma_addr_t NewLogicalDriveInformationDMA;
  198.       DAC960_V1_BackgroundInitializationStatus_T
  199.          *BackgroundInitializationStatus;
  200.       dma_addr_t BackgroundInitializationStatusDMA;
  201.       DAC960_V1_BackgroundInitializationStatus_T
  202.          LastBackgroundInitializationStatus;
  204.       DAC960_V1_DeviceState_T
  205. DeviceState[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  206.       DAC960_V1_DeviceState_T *NewDeviceState;
  207.       dma_addr_t NewDeviceStateDMA;
  209.       DAC960_SCSI_Inquiry_T
  210. InquiryStandardData[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  211.       DAC960_SCSI_Inquiry_T *NewInquiryStandardData;
  212.       dma_addr_t NewInquiryStandardDataDMA;
  214.       DAC960_SCSI_Inquiry_UnitSerialNumber_T
  215. InquiryUnitSerialNumber[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  216.       DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber;
  217.       dma_addr_t NewInquiryUnitSerialNumberDMA;
  219.       int DeviceResetCount[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  220.       boolean DirectCommandActive[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  221.     } V1;
  222.     struct {
  223.       unsigned int StatusChangeCounter;
  224.       unsigned int NextEventSequenceNumber;
  225.       unsigned int PhysicalDeviceIndex;
  226.       boolean NeedLogicalDeviceInformation;
  227.       boolean NeedPhysicalDeviceInformation;
  228.       boolean NeedDeviceSerialNumberInformation;
  229.       boolean StartLogicalDeviceInformationScan;
  230.       boolean StartPhysicalDeviceInformationScan;
  231.       struct pci_pool *RequestSensePool;
  233.       dma_addr_t FirstCommandMailboxDMA;
  234.       DAC960_V2_CommandMailbox_T *FirstCommandMailbox;
  235.       DAC960_V2_CommandMailbox_T *LastCommandMailbox;
  236.       DAC960_V2_CommandMailbox_T *NextCommandMailbox;
  237.       DAC960_V2_CommandMailbox_T *PreviousCommandMailbox1;
  238.       DAC960_V2_CommandMailbox_T *PreviousCommandMailbox2;
  240.       dma_addr_t FirstStatusMailboxDMA;
  241.       DAC960_V2_StatusMailbox_T *FirstStatusMailbox;
  242.       DAC960_V2_StatusMailbox_T *LastStatusMailbox;
  243.       DAC960_V2_StatusMailbox_T *NextStatusMailbox;
  245.       dma_addr_t HealthStatusBufferDMA;
  246.       DAC960_V2_HealthStatusBuffer_T *HealthStatusBuffer;
  248.       DAC960_V2_ControllerInfo_T ControllerInformation;
  249.       DAC960_V2_ControllerInfo_T *NewControllerInformation;
  250.       dma_addr_t NewControllerInformationDMA;
  252.       DAC960_V2_LogicalDeviceInfo_T
  253. *LogicalDeviceInformation[DAC960_MaxLogicalDrives];
  254.       DAC960_V2_LogicalDeviceInfo_T *NewLogicalDeviceInformation;
  255.       dma_addr_t  NewLogicalDeviceInformationDMA;
  257.       DAC960_V2_PhysicalDeviceInfo_T
  258. *PhysicalDeviceInformation[DAC960_V2_MaxPhysicalDevices];
  259.       DAC960_V2_PhysicalDeviceInfo_T *NewPhysicalDeviceInformation;
  260.       dma_addr_t NewPhysicalDeviceInformationDMA;
  262.       DAC960_SCSI_Inquiry_UnitSerialNumber_T *NewInquiryUnitSerialNumber;
  263.       dma_addr_t NewInquiryUnitSerialNumberDMA;
  264.       DAC960_SCSI_Inquiry_UnitSerialNumber_T
  265. *InquiryUnitSerialNumber[DAC960_V2_MaxPhysicalDevices];
  267.       DAC960_V2_Event_T *Event;
  268.       dma_addr_t EventDMA;
  270.       DAC960_V2_PhysicalToLogicalDevice_T *PhysicalToLogicalDevice;
  271.       dma_addr_t PhysicalToLogicalDeviceDMA;
  273.       DAC960_V2_PhysicalDevice_T
  274. LogicalDriveToVirtualDevice[DAC960_MaxLogicalDrives];
  275.       boolean LogicalDriveFoundDuringScan[DAC960_MaxLogicalDrives];
  276.     } V2;
  277.   } FW;
  278.   unsigned char ProgressBuffer[DAC960_ProgressBufferSize];
  279.   unsigned char UserStatusBuffer[DAC960_UserMessageSize];
  280. }
  281. DAC960_Controller_T;
  284. /*
  285.   Simplify access to Firmware Version Dependent Data Structure Components
  286.   and Functions.
  287. */
  289. #define V1 FW.V1
  290. #define V2 FW.V2
  291. #define DAC960_QueueCommand(Command) 
  292.   (Controller->QueueCommand)(Command)
  293. #define DAC960_ReadControllerConfiguration(Controller) 
  294.   (Controller->ReadControllerConfiguration)(Controller)
  295. #define DAC960_ReadDeviceConfiguration(Controller) 
  296.   (Controller->ReadDeviceConfiguration)(Controller)
  297. #define DAC960_ReportDeviceConfiguration(Controller) 
  298.   (Controller->ReportDeviceConfiguration)(Controller)
  299. #define DAC960_QueueReadWriteCommand(Command) 
  300.   (Controller->QueueReadWriteCommand)(Command)
  302. /*
  303.  * dma_addr_writeql is provided to write dma_addr_t types
  304.  * to a 64-bit pci address space register.  The controller
  305.  * will accept having the register written as two 32-bit
  306.  * values.
  307.  *
  308.  * In HIGHMEM kernels, dma_addr_t is a 64-bit value.
  309.  * without HIGHMEM,  dma_addr_t is a 32-bit value.
  310.  *
  311.  * The compiler should always fix up the assignment
  312.  * to u.wq appropriately, depending upon the size of
  313.  * dma_addr_t.
  314.  */
  315. static inline
  316. void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address)
  317. {
  318. union {
  319. u64 wq;
  320. uint wl[2];
  321. } u;
  323. u.wq = addr;
  325. writel(u.wl[0], write_address);
  326. writel(u.wl[1], write_address + 4);
  327. }
  329. /*
  330.   Define the DAC960 GEM Series Controller Interface Register Offsets.
  331.  */
  333. #define DAC960_GEM_RegisterWindowSize 0x600
  335. typedef enum
  336. {
  337.   DAC960_GEM_InboundDoorBellRegisterReadSetOffset   =   0x214,
  338.   DAC960_GEM_InboundDoorBellRegisterClearOffset     =   0x218,
  339.   DAC960_GEM_OutboundDoorBellRegisterReadSetOffset  =   0x224,
  340.   DAC960_GEM_OutboundDoorBellRegisterClearOffset    =   0x228,
  341.   DAC960_GEM_InterruptStatusRegisterOffset          =   0x208,
  342.   DAC960_GEM_InterruptMaskRegisterReadSetOffset     =   0x22C,
  343.   DAC960_GEM_InterruptMaskRegisterClearOffset       =   0x230,
  344.   DAC960_GEM_CommandMailboxBusAddressOffset         =   0x510,
  345.   DAC960_GEM_CommandStatusOffset                    =   0x518,
  346.   DAC960_GEM_ErrorStatusRegisterReadSetOffset       =   0x224,
  347.   DAC960_GEM_ErrorStatusRegisterClearOffset         =   0x228,
  348. }
  349. DAC960_GEM_RegisterOffsets_T;
  351. /*
  352.   Define the structure of the DAC960 GEM Series Inbound Door Bell
  353.  */
  355. typedef union DAC960_GEM_InboundDoorBellRegister
  356. {
  357.   unsigned int All;
  358.   struct {
  359.     unsigned int :24;
  360.     boolean HardwareMailboxNewCommand:1;
  361.     boolean AcknowledgeHardwareMailboxStatus:1;
  362.     boolean GenerateInterrupt:1;
  363.     boolean ControllerReset:1;
  364.     boolean MemoryMailboxNewCommand:1;
  365.     unsigned int :3;
  366.   } Write;
  367.   struct {
  368.     unsigned int :24;
  369.     boolean HardwareMailboxFull:1;
  370.     boolean InitializationInProgress:1;
  371.     unsigned int :6;
  372.   } Read;
  373. }
  374. DAC960_GEM_InboundDoorBellRegister_T;
  376. /*
  377.   Define the structure of the DAC960 GEM Series Outbound Door Bell Register.
  378.  */
  379. typedef union DAC960_GEM_OutboundDoorBellRegister
  380. {
  381.   unsigned int All;
  382.   struct {
  383.     unsigned int :24;
  384.     boolean AcknowledgeHardwareMailboxInterrupt:1;
  385.     boolean AcknowledgeMemoryMailboxInterrupt:1;
  386.     unsigned int :6;
  387.   } Write;
  388.   struct {
  389.     unsigned int :24;
  390.     boolean HardwareMailboxStatusAvailable:1;
  391.     boolean MemoryMailboxStatusAvailable:1;
  392.     unsigned int :6;
  393.   } Read;
  394. }
  395. DAC960_GEM_OutboundDoorBellRegister_T;
  397. /*
  398.   Define the structure of the DAC960 GEM Series Interrupt Mask Register.
  399.  */
  400. typedef union DAC960_GEM_InterruptMaskRegister
  401. {
  402.   unsigned int All;
  403.   struct {
  404.     unsigned int :16;
  405.     unsigned int :8;
  406.     unsigned int HardwareMailboxInterrupt:1;
  407.     unsigned int MemoryMailboxInterrupt:1;
  408.     unsigned int :6;
  409.   } Bits;
  410. }
  411. DAC960_GEM_InterruptMaskRegister_T;
  413. /*
  414.   Define the structure of the DAC960 GEM Series Error Status Register.
  415.  */
  417. typedef union DAC960_GEM_ErrorStatusRegister
  418. {
  419.   unsigned int All;
  420.   struct {
  421.     unsigned int :24;
  422.     unsigned int :5;
  423.     boolean ErrorStatusPending:1;
  424.     unsigned int :2;
  425.   } Bits;
  426. }
  427. DAC960_GEM_ErrorStatusRegister_T;
  429. /*
  430.   Define inline functions to provide an abstraction for reading and writing the
  431.   DAC960 GEM Series Controller Interface Registers.
  432. */
  434. static inline
  435. void DAC960_GEM_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress)
  436. {
  437.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  438.   InboundDoorBellRegister.All = 0;
  439.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  440.   writel(InboundDoorBellRegister.All,
  441.  ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
  442. }
  444. static inline
  445. void DAC960_GEM_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress)
  446. {
  447.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  448.   InboundDoorBellRegister.All = 0;
  449.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  450.   writel(InboundDoorBellRegister.All,
  451.  ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterClearOffset);
  452. }
  454. static inline
  455. void DAC960_GEM_GenerateInterrupt(void __iomem *ControllerBaseAddress)
  456. {
  457.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  458.   InboundDoorBellRegister.All = 0;
  459.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  460.   writel(InboundDoorBellRegister.All,
  461.  ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
  462. }
  464. static inline
  465. void DAC960_GEM_ControllerReset(void __iomem *ControllerBaseAddress)
  466. {
  467.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  468.   InboundDoorBellRegister.All = 0;
  469.   InboundDoorBellRegister.Write.ControllerReset = true;
  470.   writel(InboundDoorBellRegister.All,
  471.  ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
  472. }
  474. static inline
  475. void DAC960_GEM_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
  476. {
  477.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  478.   InboundDoorBellRegister.All = 0;
  479.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  480.   writel(InboundDoorBellRegister.All,
  481.  ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
  482. }
  484. static inline
  485. boolean DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
  486. {
  487.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  488.   InboundDoorBellRegister.All =
  489.     readl(ControllerBaseAddress +
  490.           DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
  491.   return InboundDoorBellRegister.Read.HardwareMailboxFull;
  492. }
  494. static inline
  495. boolean DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress)
  496. {
  497.   DAC960_GEM_InboundDoorBellRegister_T InboundDoorBellRegister;
  498.   InboundDoorBellRegister.All =
  499.     readl(ControllerBaseAddress +
  500.           DAC960_GEM_InboundDoorBellRegisterReadSetOffset);
  501.   return InboundDoorBellRegister.Read.InitializationInProgress;
  502. }
  504. static inline
  505. void DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress)
  506. {
  507.   DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  508.   OutboundDoorBellRegister.All = 0;
  509.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  510.   writel(OutboundDoorBellRegister.All,
  511.  ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset);
  512. }
  514. static inline
  515. void DAC960_GEM_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress)
  516. {
  517.   DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  518.   OutboundDoorBellRegister.All = 0;
  519.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  520.   writel(OutboundDoorBellRegister.All,
  521.  ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset);
  522. }
  524. static inline
  525. void DAC960_GEM_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
  526. {
  527.   DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  528.   OutboundDoorBellRegister.All = 0;
  529.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  530.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  531.   writel(OutboundDoorBellRegister.All,
  532.  ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset);
  533. }
  535. static inline
  536. boolean DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  537. {
  538.   DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  539.   OutboundDoorBellRegister.All =
  540.     readl(ControllerBaseAddress +
  541.           DAC960_GEM_OutboundDoorBellRegisterReadSetOffset);
  542.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  543. }
  545. static inline
  546. boolean DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  547. {
  548.   DAC960_GEM_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  549.   OutboundDoorBellRegister.All =
  550.     readl(ControllerBaseAddress +
  551.           DAC960_GEM_OutboundDoorBellRegisterReadSetOffset);
  552.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  553. }
  555. static inline
  556. void DAC960_GEM_EnableInterrupts(void __iomem *ControllerBaseAddress)
  557. {
  558.   DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
  559.   InterruptMaskRegister.All = 0;
  560.   InterruptMaskRegister.Bits.HardwareMailboxInterrupt = true;
  561.   InterruptMaskRegister.Bits.MemoryMailboxInterrupt = true;
  562.   writel(InterruptMaskRegister.All,
  563.  ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterClearOffset);
  564. }
  566. static inline
  567. void DAC960_GEM_DisableInterrupts(void __iomem *ControllerBaseAddress)
  568. {
  569.   DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
  570.   InterruptMaskRegister.All = 0;
  571.   InterruptMaskRegister.Bits.HardwareMailboxInterrupt = true;
  572.   InterruptMaskRegister.Bits.MemoryMailboxInterrupt = true;
  573.   writel(InterruptMaskRegister.All,
  574.  ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterReadSetOffset);
  575. }
  577. static inline
  578. boolean DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
  579. {
  580.   DAC960_GEM_InterruptMaskRegister_T InterruptMaskRegister;
  581.   InterruptMaskRegister.All =
  582.     readl(ControllerBaseAddress +
  583.           DAC960_GEM_InterruptMaskRegisterReadSetOffset);
  584.   return !(InterruptMaskRegister.Bits.HardwareMailboxInterrupt ||
  585.            InterruptMaskRegister.Bits.MemoryMailboxInterrupt);
  586. }
  588. static inline
  589. void DAC960_GEM_WriteCommandMailbox(DAC960_V2_CommandMailbox_T
  590.      *MemoryCommandMailbox,
  591.    DAC960_V2_CommandMailbox_T
  592.      *CommandMailbox)
  593. {
  594.   memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1],
  595.  sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int));
  596.   wmb();
  597.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  598.   mb();
  599. }
  601. static inline
  602. void DAC960_GEM_WriteHardwareMailbox(void __iomem *ControllerBaseAddress,
  603.     dma_addr_t CommandMailboxDMA)
  604. {
  605. dma_addr_writeql(CommandMailboxDMA,
  606. ControllerBaseAddress +
  607. DAC960_GEM_CommandMailboxBusAddressOffset);
  608. }
  610. static inline DAC960_V2_CommandIdentifier_T
  611. DAC960_GEM_ReadCommandIdentifier(void __iomem *ControllerBaseAddress)
  612. {
  613.   return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset);
  614. }
  616. static inline DAC960_V2_CommandStatus_T
  617. DAC960_GEM_ReadCommandStatus(void __iomem *ControllerBaseAddress)
  618. {
  619.   return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2);
  620. }
  622. static inline boolean
  623. DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress,
  624.   unsigned char *ErrorStatus,
  625.   unsigned char *Parameter0,
  626.   unsigned char *Parameter1)
  627. {
  628.   DAC960_GEM_ErrorStatusRegister_T ErrorStatusRegister;
  629.   ErrorStatusRegister.All =
  630.     readl(ControllerBaseAddress + DAC960_GEM_ErrorStatusRegisterReadSetOffset);
  631.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  632.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  633.   *ErrorStatus = ErrorStatusRegister.All;
  634.   *Parameter0 =
  635.     readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 0);
  636.   *Parameter1 =
  637.     readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 1);
  638.   writel(0x03000000, ControllerBaseAddress +
  639.          DAC960_GEM_ErrorStatusRegisterClearOffset);
  640.   return true;
  641. }
  643. /*
  644.   Define the DAC960 BA Series Controller Interface Register Offsets.
  645. */
  647. #define DAC960_BA_RegisterWindowSize 0x80
  649. typedef enum
  650. {
  651.   DAC960_BA_InboundDoorBellRegisterOffset = 0x60,
  652.   DAC960_BA_OutboundDoorBellRegisterOffset = 0x61,
  653.   DAC960_BA_InterruptStatusRegisterOffset = 0x30,
  654.   DAC960_BA_InterruptMaskRegisterOffset = 0x34,
  655.   DAC960_BA_CommandMailboxBusAddressOffset = 0x50,
  656.   DAC960_BA_CommandStatusOffset = 0x58,
  657.   DAC960_BA_ErrorStatusRegisterOffset = 0x63
  658. }
  659. DAC960_BA_RegisterOffsets_T;
  662. /*
  663.   Define the structure of the DAC960 BA Series Inbound Door Bell Register.
  664. */
  666. typedef union DAC960_BA_InboundDoorBellRegister
  667. {
  668.   unsigned char All;
  669.   struct {
  670.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  671.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  672.     boolean GenerateInterrupt:1; /* Bit 2 */
  673.     boolean ControllerReset:1; /* Bit 3 */
  674.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  675.     unsigned char :3; /* Bits 5-7 */
  676.   } Write;
  677.   struct {
  678.     boolean HardwareMailboxEmpty:1; /* Bit 0 */
  679.     boolean InitializationNotInProgress:1; /* Bit 1 */
  680.     unsigned char :6; /* Bits 2-7 */
  681.   } Read;
  682. }
  683. DAC960_BA_InboundDoorBellRegister_T;
  686. /*
  687.   Define the structure of the DAC960 BA Series Outbound Door Bell Register.
  688. */
  690. typedef union DAC960_BA_OutboundDoorBellRegister
  691. {
  692.   unsigned char All;
  693.   struct {
  694.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  695.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  696.     unsigned char :6; /* Bits 2-7 */
  697.   } Write;
  698.   struct {
  699.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  700.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  701.     unsigned char :6; /* Bits 2-7 */
  702.   } Read;
  703. }
  704. DAC960_BA_OutboundDoorBellRegister_T;
  707. /*
  708.   Define the structure of the DAC960 BA Series Interrupt Mask Register.
  709. */
  711. typedef union DAC960_BA_InterruptMaskRegister
  712. {
  713.   unsigned char All;
  714.   struct {
  715.     unsigned int :2; /* Bits 0-1 */
  716.     boolean DisableInterrupts:1; /* Bit 2 */
  717.     boolean DisableInterruptsI2O:1; /* Bit 3 */
  718.     unsigned int :4; /* Bits 4-7 */
  719.   } Bits;
  720. }
  721. DAC960_BA_InterruptMaskRegister_T;
  724. /*
  725.   Define the structure of the DAC960 BA Series Error Status Register.
  726. */
  728. typedef union DAC960_BA_ErrorStatusRegister
  729. {
  730.   unsigned char All;
  731.   struct {
  732.     unsigned int :2; /* Bits 0-1 */
  733.     boolean ErrorStatusPending:1; /* Bit 2 */
  734.     unsigned int :5; /* Bits 3-7 */
  735.   } Bits;
  736. }
  737. DAC960_BA_ErrorStatusRegister_T;
  740. /*
  741.   Define inline functions to provide an abstraction for reading and writing the
  742.   DAC960 BA Series Controller Interface Registers.
  743. */
  745. static inline
  746. void DAC960_BA_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress)
  747. {
  748.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  749.   InboundDoorBellRegister.All = 0;
  750.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  751.   writeb(InboundDoorBellRegister.All,
  752.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  753. }
  755. static inline
  756. void DAC960_BA_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress)
  757. {
  758.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  759.   InboundDoorBellRegister.All = 0;
  760.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  761.   writeb(InboundDoorBellRegister.All,
  762.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  763. }
  765. static inline
  766. void DAC960_BA_GenerateInterrupt(void __iomem *ControllerBaseAddress)
  767. {
  768.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  769.   InboundDoorBellRegister.All = 0;
  770.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  771.   writeb(InboundDoorBellRegister.All,
  772.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  773. }
  775. static inline
  776. void DAC960_BA_ControllerReset(void __iomem *ControllerBaseAddress)
  777. {
  778.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  779.   InboundDoorBellRegister.All = 0;
  780.   InboundDoorBellRegister.Write.ControllerReset = true;
  781.   writeb(InboundDoorBellRegister.All,
  782.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  783. }
  785. static inline
  786. void DAC960_BA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
  787. {
  788.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  789.   InboundDoorBellRegister.All = 0;
  790.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  791.   writeb(InboundDoorBellRegister.All,
  792.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  793. }
  795. static inline
  796. boolean DAC960_BA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
  797. {
  798.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  799.   InboundDoorBellRegister.All =
  800.     readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  801.   return !InboundDoorBellRegister.Read.HardwareMailboxEmpty;
  802. }
  804. static inline
  805. boolean DAC960_BA_InitializationInProgressP(void __iomem *ControllerBaseAddress)
  806. {
  807.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  808.   InboundDoorBellRegister.All =
  809.     readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  810.   return !InboundDoorBellRegister.Read.InitializationNotInProgress;
  811. }
  813. static inline
  814. void DAC960_BA_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress)
  815. {
  816.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  817.   OutboundDoorBellRegister.All = 0;
  818.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  819.   writeb(OutboundDoorBellRegister.All,
  820.  ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  821. }
  823. static inline
  824. void DAC960_BA_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress)
  825. {
  826.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  827.   OutboundDoorBellRegister.All = 0;
  828.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  829.   writeb(OutboundDoorBellRegister.All,
  830.  ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  831. }
  833. static inline
  834. void DAC960_BA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
  835. {
  836.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  837.   OutboundDoorBellRegister.All = 0;
  838.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  839.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  840.   writeb(OutboundDoorBellRegister.All,
  841.  ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  842. }
  844. static inline
  845. boolean DAC960_BA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  846. {
  847.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  848.   OutboundDoorBellRegister.All =
  849.     readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  850.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  851. }
  853. static inline
  854. boolean DAC960_BA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  855. {
  856.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  857.   OutboundDoorBellRegister.All =
  858.     readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  859.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  860. }
  862. static inline
  863. void DAC960_BA_EnableInterrupts(void __iomem *ControllerBaseAddress)
  864. {
  865.   DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
  866.   InterruptMaskRegister.All = 0xFF;
  867.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  868.   InterruptMaskRegister.Bits.DisableInterruptsI2O = true;
  869.   writeb(InterruptMaskRegister.All,
  870.  ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset);
  871. }
  873. static inline
  874. void DAC960_BA_DisableInterrupts(void __iomem *ControllerBaseAddress)
  875. {
  876.   DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
  877.   InterruptMaskRegister.All = 0xFF;
  878.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  879.   InterruptMaskRegister.Bits.DisableInterruptsI2O = true;
  880.   writeb(InterruptMaskRegister.All,
  881.  ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset);
  882. }
  884. static inline
  885. boolean DAC960_BA_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
  886. {
  887.   DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
  888.   InterruptMaskRegister.All =
  889.     readb(ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset);
  890.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  891. }
  893. static inline
  894. void DAC960_BA_WriteCommandMailbox(DAC960_V2_CommandMailbox_T
  895.      *MemoryCommandMailbox,
  896.    DAC960_V2_CommandMailbox_T
  897.      *CommandMailbox)
  898. {
  899.   memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1],
  900.  sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int));
  901.   wmb();
  902.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  903.   mb();
  904. }
  907. static inline
  908. void DAC960_BA_WriteHardwareMailbox(void __iomem *ControllerBaseAddress,
  909.     dma_addr_t CommandMailboxDMA)
  910. {
  911. dma_addr_writeql(CommandMailboxDMA,
  912. ControllerBaseAddress +
  913. DAC960_BA_CommandMailboxBusAddressOffset);
  914. }
  916. static inline DAC960_V2_CommandIdentifier_T
  917. DAC960_BA_ReadCommandIdentifier(void __iomem *ControllerBaseAddress)
  918. {
  919.   return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset);
  920. }
  922. static inline DAC960_V2_CommandStatus_T
  923. DAC960_BA_ReadCommandStatus(void __iomem *ControllerBaseAddress)
  924. {
  925.   return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset + 2);
  926. }
  928. static inline boolean
  929. DAC960_BA_ReadErrorStatus(void __iomem *ControllerBaseAddress,
  930.   unsigned char *ErrorStatus,
  931.   unsigned char *Parameter0,
  932.   unsigned char *Parameter1)
  933. {
  934.   DAC960_BA_ErrorStatusRegister_T ErrorStatusRegister;
  935.   ErrorStatusRegister.All =
  936.     readb(ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset);
  937.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  938.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  939.   *ErrorStatus = ErrorStatusRegister.All;
  940.   *Parameter0 =
  941.     readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 0);
  942.   *Parameter1 =
  943.     readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 1);
  944.   writeb(0xFF, ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset);
  945.   return true;
  946. }
  949. /*
  950.   Define the DAC960 LP Series Controller Interface Register Offsets.
  951. */
  953. #define DAC960_LP_RegisterWindowSize 0x80
  955. typedef enum
  956. {
  957.   DAC960_LP_InboundDoorBellRegisterOffset = 0x20,
  958.   DAC960_LP_OutboundDoorBellRegisterOffset = 0x2C,
  959.   DAC960_LP_InterruptStatusRegisterOffset = 0x30,
  960.   DAC960_LP_InterruptMaskRegisterOffset = 0x34,
  961.   DAC960_LP_CommandMailboxBusAddressOffset = 0x10,
  962.   DAC960_LP_CommandStatusOffset = 0x18,
  963.   DAC960_LP_ErrorStatusRegisterOffset = 0x2E
  964. }
  965. DAC960_LP_RegisterOffsets_T;
  968. /*
  969.   Define the structure of the DAC960 LP Series Inbound Door Bell Register.
  970. */
  972. typedef union DAC960_LP_InboundDoorBellRegister
  973. {
  974.   unsigned char All;
  975.   struct {
  976.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  977.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  978.     boolean GenerateInterrupt:1; /* Bit 2 */
  979.     boolean ControllerReset:1; /* Bit 3 */
  980.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  981.     unsigned char :3; /* Bits 5-7 */
  982.   } Write;
  983.   struct {
  984.     boolean HardwareMailboxFull:1; /* Bit 0 */
  985.     boolean InitializationInProgress:1; /* Bit 1 */
  986.     unsigned char :6; /* Bits 2-7 */
  987.   } Read;
  988. }
  989. DAC960_LP_InboundDoorBellRegister_T;
  992. /*
  993.   Define the structure of the DAC960 LP Series Outbound Door Bell Register.
  994. */
  996. typedef union DAC960_LP_OutboundDoorBellRegister
  997. {
  998.   unsigned char All;
  999.   struct {
  1000.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  1001.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  1002.     unsigned char :6; /* Bits 2-7 */
  1003.   } Write;
  1004.   struct {
  1005.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  1006.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  1007.     unsigned char :6; /* Bits 2-7 */
  1008.   } Read;
  1009. }
  1010. DAC960_LP_OutboundDoorBellRegister_T;
  1013. /*
  1014.   Define the structure of the DAC960 LP Series Interrupt Mask Register.
  1015. */
  1017. typedef union DAC960_LP_InterruptMaskRegister
  1018. {
  1019.   unsigned char All;
  1020.   struct {
  1021.     unsigned int :2; /* Bits 0-1 */
  1022.     boolean DisableInterrupts:1; /* Bit 2 */
  1023.     unsigned int :5; /* Bits 3-7 */
  1024.   } Bits;
  1025. }
  1026. DAC960_LP_InterruptMaskRegister_T;
  1029. /*
  1030.   Define the structure of the DAC960 LP Series Error Status Register.
  1031. */
  1033. typedef union DAC960_LP_ErrorStatusRegister
  1034. {
  1035.   unsigned char All;
  1036.   struct {
  1037.     unsigned int :2; /* Bits 0-1 */
  1038.     boolean ErrorStatusPending:1; /* Bit 2 */
  1039.     unsigned int :5; /* Bits 3-7 */
  1040.   } Bits;
  1041. }
  1042. DAC960_LP_ErrorStatusRegister_T;
  1045. /*
  1046.   Define inline functions to provide an abstraction for reading and writing the
  1047.   DAC960 LP Series Controller Interface Registers.
  1048. */
  1050. static inline
  1051. void DAC960_LP_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress)
  1052. {
  1053.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1054.   InboundDoorBellRegister.All = 0;
  1055.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  1056.   writeb(InboundDoorBellRegister.All,
  1057.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1058. }
  1060. static inline
  1061. void DAC960_LP_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress)
  1062. {
  1063.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1064.   InboundDoorBellRegister.All = 0;
  1065.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  1066.   writeb(InboundDoorBellRegister.All,
  1067.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1068. }
  1070. static inline
  1071. void DAC960_LP_GenerateInterrupt(void __iomem *ControllerBaseAddress)
  1072. {
  1073.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1074.   InboundDoorBellRegister.All = 0;
  1075.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  1076.   writeb(InboundDoorBellRegister.All,
  1077.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1078. }
  1080. static inline
  1081. void DAC960_LP_ControllerReset(void __iomem *ControllerBaseAddress)
  1082. {
  1083.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1084.   InboundDoorBellRegister.All = 0;
  1085.   InboundDoorBellRegister.Write.ControllerReset = true;
  1086.   writeb(InboundDoorBellRegister.All,
  1087.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1088. }
  1090. static inline
  1091. void DAC960_LP_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
  1092. {
  1093.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1094.   InboundDoorBellRegister.All = 0;
  1095.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  1096.   writeb(InboundDoorBellRegister.All,
  1097.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1098. }
  1100. static inline
  1101. boolean DAC960_LP_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
  1102. {
  1103.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1104.   InboundDoorBellRegister.All =
  1105.     readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1106.   return InboundDoorBellRegister.Read.HardwareMailboxFull;
  1107. }
  1109. static inline
  1110. boolean DAC960_LP_InitializationInProgressP(void __iomem *ControllerBaseAddress)
  1111. {
  1112.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  1113.   InboundDoorBellRegister.All =
  1114.     readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  1115.   return InboundDoorBellRegister.Read.InitializationInProgress;
  1116. }
  1118. static inline
  1119. void DAC960_LP_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress)
  1120. {
  1121.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1122.   OutboundDoorBellRegister.All = 0;
  1123.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1124.   writeb(OutboundDoorBellRegister.All,
  1125.  ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  1126. }
  1128. static inline
  1129. void DAC960_LP_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress)
  1130. {
  1131.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1132.   OutboundDoorBellRegister.All = 0;
  1133.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1134.   writeb(OutboundDoorBellRegister.All,
  1135.  ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  1136. }
  1138. static inline
  1139. void DAC960_LP_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
  1140. {
  1141.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1142.   OutboundDoorBellRegister.All = 0;
  1143.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1144.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1145.   writeb(OutboundDoorBellRegister.All,
  1146.  ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  1147. }
  1149. static inline
  1150. boolean DAC960_LP_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  1151. {
  1152.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1153.   OutboundDoorBellRegister.All =
  1154.     readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  1155.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  1156. }
  1158. static inline
  1159. boolean DAC960_LP_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  1160. {
  1161.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1162.   OutboundDoorBellRegister.All =
  1163.     readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  1164.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  1165. }
  1167. static inline
  1168. void DAC960_LP_EnableInterrupts(void __iomem *ControllerBaseAddress)
  1169. {
  1170.   DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
  1171.   InterruptMaskRegister.All = 0xFF;
  1172.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  1173.   writeb(InterruptMaskRegister.All,
  1174.  ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset);
  1175. }
  1177. static inline
  1178. void DAC960_LP_DisableInterrupts(void __iomem *ControllerBaseAddress)
  1179. {
  1180.   DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
  1181.   InterruptMaskRegister.All = 0xFF;
  1182.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  1183.   writeb(InterruptMaskRegister.All,
  1184.  ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset);
  1185. }
  1187. static inline
  1188. boolean DAC960_LP_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
  1189. {
  1190.   DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
  1191.   InterruptMaskRegister.All =
  1192.     readb(ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset);
  1193.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  1194. }
  1196. static inline
  1197. void DAC960_LP_WriteCommandMailbox(DAC960_V2_CommandMailbox_T
  1198.      *MemoryCommandMailbox,
  1199.    DAC960_V2_CommandMailbox_T
  1200.      *CommandMailbox)
  1201. {
  1202.   memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1],
  1203.  sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int));
  1204.   wmb();
  1205.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  1206.   mb();
  1207. }
  1209. static inline
  1210. void DAC960_LP_WriteHardwareMailbox(void __iomem *ControllerBaseAddress,
  1211.     dma_addr_t CommandMailboxDMA)
  1212. {
  1213. dma_addr_writeql(CommandMailboxDMA,
  1214. ControllerBaseAddress +
  1215. DAC960_LP_CommandMailboxBusAddressOffset);
  1216. }
  1218. static inline DAC960_V2_CommandIdentifier_T
  1219. DAC960_LP_ReadCommandIdentifier(void __iomem *ControllerBaseAddress)
  1220. {
  1221.   return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset);
  1222. }
  1224. static inline DAC960_V2_CommandStatus_T
  1225. DAC960_LP_ReadCommandStatus(void __iomem *ControllerBaseAddress)
  1226. {
  1227.   return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset + 2);
  1228. }
  1230. static inline boolean
  1231. DAC960_LP_ReadErrorStatus(void __iomem *ControllerBaseAddress,
  1232.   unsigned char *ErrorStatus,
  1233.   unsigned char *Parameter0,
  1234.   unsigned char *Parameter1)
  1235. {
  1236.   DAC960_LP_ErrorStatusRegister_T ErrorStatusRegister;
  1237.   ErrorStatusRegister.All =
  1238.     readb(ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset);
  1239.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  1240.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  1241.   *ErrorStatus = ErrorStatusRegister.All;
  1242.   *Parameter0 =
  1243.     readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 0);
  1244.   *Parameter1 =
  1245.     readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 1);
  1246.   writeb(0xFF, ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset);
  1247.   return true;
  1248. }
  1251. /*
  1252.   Define the DAC960 LA Series Controller Interface Register Offsets.
  1253. */
  1255. #define DAC960_LA_RegisterWindowSize 0x80
  1257. typedef enum
  1258. {
  1259.   DAC960_LA_InboundDoorBellRegisterOffset = 0x60,
  1260.   DAC960_LA_OutboundDoorBellRegisterOffset = 0x61,
  1261.   DAC960_LA_InterruptMaskRegisterOffset = 0x34,
  1262.   DAC960_LA_CommandOpcodeRegisterOffset = 0x50,
  1263.   DAC960_LA_CommandIdentifierRegisterOffset = 0x51,
  1264.   DAC960_LA_MailboxRegister2Offset = 0x52,
  1265.   DAC960_LA_MailboxRegister3Offset = 0x53,
  1266.   DAC960_LA_MailboxRegister4Offset = 0x54,
  1267.   DAC960_LA_MailboxRegister5Offset = 0x55,
  1268.   DAC960_LA_MailboxRegister6Offset = 0x56,
  1269.   DAC960_LA_MailboxRegister7Offset = 0x57,
  1270.   DAC960_LA_MailboxRegister8Offset = 0x58,
  1271.   DAC960_LA_MailboxRegister9Offset = 0x59,
  1272.   DAC960_LA_MailboxRegister10Offset = 0x5A,
  1273.   DAC960_LA_MailboxRegister11Offset = 0x5B,
  1274.   DAC960_LA_MailboxRegister12Offset = 0x5C,
  1275.   DAC960_LA_StatusCommandIdentifierRegOffset = 0x5D,
  1276.   DAC960_LA_StatusRegisterOffset = 0x5E,
  1277.   DAC960_LA_ErrorStatusRegisterOffset = 0x63
  1278. }
  1279. DAC960_LA_RegisterOffsets_T;
  1282. /*
  1283.   Define the structure of the DAC960 LA Series Inbound Door Bell Register.
  1284. */
  1286. typedef union DAC960_LA_InboundDoorBellRegister
  1287. {
  1288.   unsigned char All;
  1289.   struct {
  1290.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  1291.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  1292.     boolean GenerateInterrupt:1; /* Bit 2 */
  1293.     boolean ControllerReset:1; /* Bit 3 */
  1294.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  1295.     unsigned char :3; /* Bits 5-7 */
  1296.   } Write;
  1297.   struct {
  1298.     boolean HardwareMailboxEmpty:1; /* Bit 0 */
  1299.     boolean InitializationNotInProgress:1; /* Bit 1 */
  1300.     unsigned char :6; /* Bits 2-7 */
  1301.   } Read;
  1302. }
  1303. DAC960_LA_InboundDoorBellRegister_T;
  1306. /*
  1307.   Define the structure of the DAC960 LA Series Outbound Door Bell Register.
  1308. */
  1310. typedef union DAC960_LA_OutboundDoorBellRegister
  1311. {
  1312.   unsigned char All;
  1313.   struct {
  1314.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  1315.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  1316.     unsigned char :6; /* Bits 2-7 */
  1317.   } Write;
  1318.   struct {
  1319.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  1320.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  1321.     unsigned char :6; /* Bits 2-7 */
  1322.   } Read;
  1323. }
  1324. DAC960_LA_OutboundDoorBellRegister_T;
  1327. /*
  1328.   Define the structure of the DAC960 LA Series Interrupt Mask Register.
  1329. */
  1331. typedef union DAC960_LA_InterruptMaskRegister
  1332. {
  1333.   unsigned char All;
  1334.   struct {
  1335.     unsigned char :2; /* Bits 0-1 */
  1336.     boolean DisableInterrupts:1; /* Bit 2 */
  1337.     unsigned char :5; /* Bits 3-7 */
  1338.   } Bits;
  1339. }
  1340. DAC960_LA_InterruptMaskRegister_T;
  1343. /*
  1344.   Define the structure of the DAC960 LA Series Error Status Register.
  1345. */
  1347. typedef union DAC960_LA_ErrorStatusRegister
  1348. {
  1349.   unsigned char All;
  1350.   struct {
  1351.     unsigned int :2; /* Bits 0-1 */
  1352.     boolean ErrorStatusPending:1; /* Bit 2 */
  1353.     unsigned int :5; /* Bits 3-7 */
  1354.   } Bits;
  1355. }
  1356. DAC960_LA_ErrorStatusRegister_T;
  1359. /*
  1360.   Define inline functions to provide an abstraction for reading and writing the
  1361.   DAC960 LA Series Controller Interface Registers.
  1362. */
  1364. static inline
  1365. void DAC960_LA_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress)
  1366. {
  1367.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1368.   InboundDoorBellRegister.All = 0;
  1369.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  1370.   writeb(InboundDoorBellRegister.All,
  1371.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1372. }
  1374. static inline
  1375. void DAC960_LA_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress)
  1376. {
  1377.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1378.   InboundDoorBellRegister.All = 0;
  1379.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  1380.   writeb(InboundDoorBellRegister.All,
  1381.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1382. }
  1384. static inline
  1385. void DAC960_LA_GenerateInterrupt(void __iomem *ControllerBaseAddress)
  1386. {
  1387.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1388.   InboundDoorBellRegister.All = 0;
  1389.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  1390.   writeb(InboundDoorBellRegister.All,
  1391.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1392. }
  1394. static inline
  1395. void DAC960_LA_ControllerReset(void __iomem *ControllerBaseAddress)
  1396. {
  1397.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1398.   InboundDoorBellRegister.All = 0;
  1399.   InboundDoorBellRegister.Write.ControllerReset = true;
  1400.   writeb(InboundDoorBellRegister.All,
  1401.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1402. }
  1404. static inline
  1405. void DAC960_LA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
  1406. {
  1407.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1408.   InboundDoorBellRegister.All = 0;
  1409.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  1410.   writeb(InboundDoorBellRegister.All,
  1411.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1412. }
  1414. static inline
  1415. boolean DAC960_LA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
  1416. {
  1417.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1418.   InboundDoorBellRegister.All =
  1419.     readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1420.   return !InboundDoorBellRegister.Read.HardwareMailboxEmpty;
  1421. }
  1423. static inline
  1424. boolean DAC960_LA_InitializationInProgressP(void __iomem *ControllerBaseAddress)
  1425. {
  1426.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1427.   InboundDoorBellRegister.All =
  1428.     readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1429.   return !InboundDoorBellRegister.Read.InitializationNotInProgress;
  1430. }
  1432. static inline
  1433. void DAC960_LA_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress)
  1434. {
  1435.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1436.   OutboundDoorBellRegister.All = 0;
  1437.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1438.   writeb(OutboundDoorBellRegister.All,
  1439.  ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1440. }
  1442. static inline
  1443. void DAC960_LA_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress)
  1444. {
  1445.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1446.   OutboundDoorBellRegister.All = 0;
  1447.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1448.   writeb(OutboundDoorBellRegister.All,
  1449.  ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1450. }
  1452. static inline
  1453. void DAC960_LA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
  1454. {
  1455.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1456.   OutboundDoorBellRegister.All = 0;
  1457.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1458.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1459.   writeb(OutboundDoorBellRegister.All,
  1460.  ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1461. }
  1463. static inline
  1464. boolean DAC960_LA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  1465. {
  1466.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1467.   OutboundDoorBellRegister.All =
  1468.     readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1469.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  1470. }
  1472. static inline
  1473. boolean DAC960_LA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  1474. {
  1475.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1476.   OutboundDoorBellRegister.All =
  1477.     readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1478.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  1479. }
  1481. static inline
  1482. void DAC960_LA_EnableInterrupts(void __iomem *ControllerBaseAddress)
  1483. {
  1484.   DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
  1485.   InterruptMaskRegister.All = 0xFF;
  1486.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  1487.   writeb(InterruptMaskRegister.All,
  1488.  ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset);
  1489. }
  1491. static inline
  1492. void DAC960_LA_DisableInterrupts(void __iomem *ControllerBaseAddress)
  1493. {
  1494.   DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
  1495.   InterruptMaskRegister.All = 0xFF;
  1496.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  1497.   writeb(InterruptMaskRegister.All,
  1498.  ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset);
  1499. }
  1501. static inline
  1502. boolean DAC960_LA_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
  1503. {
  1504.   DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
  1505.   InterruptMaskRegister.All =
  1506.     readb(ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset);
  1507.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  1508. }
  1510. static inline
  1511. void DAC960_LA_WriteCommandMailbox(DAC960_V1_CommandMailbox_T
  1512.      *MemoryCommandMailbox,
  1513.    DAC960_V1_CommandMailbox_T
  1514.      *CommandMailbox)
  1515. {
  1516.   MemoryCommandMailbox->Words[1] = CommandMailbox->Words[1];
  1517.   MemoryCommandMailbox->Words[2] = CommandMailbox->Words[2];
  1518.   MemoryCommandMailbox->Words[3] = CommandMailbox->Words[3];
  1519.   wmb();
  1520.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  1521.   mb();
  1522. }
  1524. static inline
  1525. void DAC960_LA_WriteHardwareMailbox(void __iomem *ControllerBaseAddress,
  1526.     DAC960_V1_CommandMailbox_T *CommandMailbox)
  1527. {
  1528.   writel(CommandMailbox->Words[0],
  1529.  ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset);
  1530.   writel(CommandMailbox->Words[1],
  1531.  ControllerBaseAddress + DAC960_LA_MailboxRegister4Offset);
  1532.   writel(CommandMailbox->Words[2],
  1533.  ControllerBaseAddress + DAC960_LA_MailboxRegister8Offset);
  1534.   writeb(CommandMailbox->Bytes[12],
  1535.  ControllerBaseAddress + DAC960_LA_MailboxRegister12Offset);
  1536. }
  1538. static inline DAC960_V1_CommandIdentifier_T
  1539. DAC960_LA_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress)
  1540. {
  1541.   return readb(ControllerBaseAddress
  1542.        + DAC960_LA_StatusCommandIdentifierRegOffset);
  1543. }
  1545. static inline DAC960_V1_CommandStatus_T
  1546. DAC960_LA_ReadStatusRegister(void __iomem *ControllerBaseAddress)
  1547. {
  1548.   return readw(ControllerBaseAddress + DAC960_LA_StatusRegisterOffset);
  1549. }
  1551. static inline boolean
  1552. DAC960_LA_ReadErrorStatus(void __iomem *ControllerBaseAddress,
  1553.   unsigned char *ErrorStatus,
  1554.   unsigned char *Parameter0,
  1555.   unsigned char *Parameter1)
  1556. {
  1557.   DAC960_LA_ErrorStatusRegister_T ErrorStatusRegister;
  1558.   ErrorStatusRegister.All =
  1559.     readb(ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset);
  1560.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  1561.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  1562.   *ErrorStatus = ErrorStatusRegister.All;
  1563.   *Parameter0 =
  1564.     readb(ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset);
  1565.   *Parameter1 =
  1566.     readb(ControllerBaseAddress + DAC960_LA_CommandIdentifierRegisterOffset);
  1567.   writeb(0xFF, ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset);
  1568.   return true;
  1569. }
  1571. /*
  1572.   Define the DAC960 PG Series Controller Interface Register Offsets.
  1573. */
  1575. #define DAC960_PG_RegisterWindowSize 0x2000
  1577. typedef enum
  1578. {
  1579.   DAC960_PG_InboundDoorBellRegisterOffset = 0x0020,
  1580.   DAC960_PG_OutboundDoorBellRegisterOffset = 0x002C,
  1581.   DAC960_PG_InterruptMaskRegisterOffset = 0x0034,
  1582.   DAC960_PG_CommandOpcodeRegisterOffset = 0x1000,
  1583.   DAC960_PG_CommandIdentifierRegisterOffset = 0x1001,
  1584.   DAC960_PG_MailboxRegister2Offset = 0x1002,
  1585.   DAC960_PG_MailboxRegister3Offset = 0x1003,
  1586.   DAC960_PG_MailboxRegister4Offset = 0x1004,
  1587.   DAC960_PG_MailboxRegister5Offset = 0x1005,
  1588.   DAC960_PG_MailboxRegister6Offset = 0x1006,
  1589.   DAC960_PG_MailboxRegister7Offset = 0x1007,
  1590.   DAC960_PG_MailboxRegister8Offset = 0x1008,
  1591.   DAC960_PG_MailboxRegister9Offset = 0x1009,
  1592.   DAC960_PG_MailboxRegister10Offset = 0x100A,
  1593.   DAC960_PG_MailboxRegister11Offset = 0x100B,
  1594.   DAC960_PG_MailboxRegister12Offset = 0x100C,
  1595.   DAC960_PG_StatusCommandIdentifierRegOffset = 0x1018,
  1596.   DAC960_PG_StatusRegisterOffset = 0x101A,
  1597.   DAC960_PG_ErrorStatusRegisterOffset = 0x103F
  1598. }
  1599. DAC960_PG_RegisterOffsets_T;
  1602. /*
  1603.   Define the structure of the DAC960 PG Series Inbound Door Bell Register.
  1604. */
  1606. typedef union DAC960_PG_InboundDoorBellRegister
  1607. {
  1608.   unsigned int All;
  1609.   struct {
  1610.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  1611.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  1612.     boolean GenerateInterrupt:1; /* Bit 2 */
  1613.     boolean ControllerReset:1; /* Bit 3 */
  1614.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  1615.     unsigned int :27; /* Bits 5-31 */
  1616.   } Write;
  1617.   struct {
  1618.     boolean HardwareMailboxFull:1; /* Bit 0 */
  1619.     boolean InitializationInProgress:1; /* Bit 1 */
  1620.     unsigned int :30; /* Bits 2-31 */
  1621.   } Read;
  1622. }
  1623. DAC960_PG_InboundDoorBellRegister_T;
  1626. /*
  1627.   Define the structure of the DAC960 PG Series Outbound Door Bell Register.
  1628. */
  1630. typedef union DAC960_PG_OutboundDoorBellRegister
  1631. {
  1632.   unsigned int All;
  1633.   struct {
  1634.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  1635.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  1636.     unsigned int :30; /* Bits 2-31 */
  1637.   } Write;
  1638.   struct {
  1639.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  1640.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  1641.     unsigned int :30; /* Bits 2-31 */
  1642.   } Read;
  1643. }
  1644. DAC960_PG_OutboundDoorBellRegister_T;
  1647. /*
  1648.   Define the structure of the DAC960 PG Series Interrupt Mask Register.
  1649. */
  1651. typedef union DAC960_PG_InterruptMaskRegister
  1652. {
  1653.   unsigned int All;
  1654.   struct {
  1655.     unsigned int MessageUnitInterruptMask1:2; /* Bits 0-1 */
  1656.     boolean DisableInterrupts:1; /* Bit 2 */
  1657.     unsigned int MessageUnitInterruptMask2:5; /* Bits 3-7 */
  1658.     unsigned int Reserved0:24; /* Bits 8-31 */
  1659.   } Bits;
  1660. }
  1661. DAC960_PG_InterruptMaskRegister_T;
  1664. /*
  1665.   Define the structure of the DAC960 PG Series Error Status Register.
  1666. */
  1668. typedef union DAC960_PG_ErrorStatusRegister
  1669. {
  1670.   unsigned char All;
  1671.   struct {
  1672.     unsigned int :2; /* Bits 0-1 */
  1673.     boolean ErrorStatusPending:1; /* Bit 2 */
  1674.     unsigned int :5; /* Bits 3-7 */
  1675.   } Bits;
  1676. }
  1677. DAC960_PG_ErrorStatusRegister_T;
  1680. /*
  1681.   Define inline functions to provide an abstraction for reading and writing the
  1682.   DAC960 PG Series Controller Interface Registers.
  1683. */
  1685. static inline
  1686. void DAC960_PG_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress)
  1687. {
  1688.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1689.   InboundDoorBellRegister.All = 0;
  1690.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  1691.   writel(InboundDoorBellRegister.All,
  1692.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1693. }
  1695. static inline
  1696. void DAC960_PG_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress)
  1697. {
  1698.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1699.   InboundDoorBellRegister.All = 0;
  1700.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  1701.   writel(InboundDoorBellRegister.All,
  1702.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1703. }
  1705. static inline
  1706. void DAC960_PG_GenerateInterrupt(void __iomem *ControllerBaseAddress)
  1707. {
  1708.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1709.   InboundDoorBellRegister.All = 0;
  1710.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  1711.   writel(InboundDoorBellRegister.All,
  1712.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1713. }
  1715. static inline
  1716. void DAC960_PG_ControllerReset(void __iomem *ControllerBaseAddress)
  1717. {
  1718.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1719.   InboundDoorBellRegister.All = 0;
  1720.   InboundDoorBellRegister.Write.ControllerReset = true;
  1721.   writel(InboundDoorBellRegister.All,
  1722.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1723. }
  1725. static inline
  1726. void DAC960_PG_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress)
  1727. {
  1728.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1729.   InboundDoorBellRegister.All = 0;
  1730.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  1731.   writel(InboundDoorBellRegister.All,
  1732.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1733. }
  1735. static inline
  1736. boolean DAC960_PG_HardwareMailboxFullP(void __iomem *ControllerBaseAddress)
  1737. {
  1738.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1739.   InboundDoorBellRegister.All =
  1740.     readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1741.   return InboundDoorBellRegister.Read.HardwareMailboxFull;
  1742. }
  1744. static inline
  1745. boolean DAC960_PG_InitializationInProgressP(void __iomem *ControllerBaseAddress)
  1746. {
  1747.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1748.   InboundDoorBellRegister.All =
  1749.     readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1750.   return InboundDoorBellRegister.Read.InitializationInProgress;
  1751. }
  1753. static inline
  1754. void DAC960_PG_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress)
  1755. {
  1756.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1757.   OutboundDoorBellRegister.All = 0;
  1758.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1759.   writel(OutboundDoorBellRegister.All,
  1760.  ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1761. }
  1763. static inline
  1764. void DAC960_PG_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress)
  1765. {
  1766.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1767.   OutboundDoorBellRegister.All = 0;
  1768.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1769.   writel(OutboundDoorBellRegister.All,
  1770.  ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1771. }
  1773. static inline
  1774. void DAC960_PG_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
  1775. {
  1776.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1777.   OutboundDoorBellRegister.All = 0;
  1778.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1779.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1780.   writel(OutboundDoorBellRegister.All,
  1781.  ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1782. }
  1784. static inline
  1785. boolean DAC960_PG_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  1786. {
  1787.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1788.   OutboundDoorBellRegister.All =
  1789.     readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1790.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  1791. }
  1793. static inline
  1794. boolean DAC960_PG_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress)
  1795. {
  1796.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1797.   OutboundDoorBellRegister.All =
  1798.     readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1799.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  1800. }
  1802. static inline
  1803. void DAC960_PG_EnableInterrupts(void __iomem *ControllerBaseAddress)
  1804. {
  1805.   DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
  1806.   InterruptMaskRegister.All = 0;
  1807.   InterruptMaskRegister.Bits.MessageUnitInterruptMask1 = 0x3;
  1808.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  1809.   InterruptMaskRegister.Bits.MessageUnitInterruptMask2 = 0x1F;
  1810.   writel(InterruptMaskRegister.All,
  1811.  ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset);
  1812. }
  1814. static inline
  1815. void DAC960_PG_DisableInterrupts(void __iomem *ControllerBaseAddress)
  1816. {
  1817.   DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
  1818.   InterruptMaskRegister.All = 0;
  1819.   InterruptMaskRegister.Bits.MessageUnitInterruptMask1 = 0x3;
  1820.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  1821.   InterruptMaskRegister.Bits.MessageUnitInterruptMask2 = 0x1F;
  1822.   writel(InterruptMaskRegister.All,
  1823.  ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset);
  1824. }
  1826. static inline
  1827. boolean DAC960_PG_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
  1828. {
  1829.   DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
  1830.   InterruptMaskRegister.All =
  1831.     readl(ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset);
  1832.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  1833. }
  1835. static inline
  1836. void DAC960_PG_WriteCommandMailbox(DAC960_V1_CommandMailbox_T
  1837.      *MemoryCommandMailbox,
  1838.    DAC960_V1_CommandMailbox_T
  1839.      *CommandMailbox)
  1840. {
  1841.   MemoryCommandMailbox->Words[1] = CommandMailbox->Words[1];
  1842.   MemoryCommandMailbox->Words[2] = CommandMailbox->Words[2];
  1843.   MemoryCommandMailbox->Words[3] = CommandMailbox->Words[3];
  1844.   wmb();
  1845.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  1846.   mb();
  1847. }
  1849. static inline
  1850. void DAC960_PG_WriteHardwareMailbox(void __iomem *ControllerBaseAddress,
  1851.     DAC960_V1_CommandMailbox_T *CommandMailbox)
  1852. {
  1853.   writel(CommandMailbox->Words[0],
  1854.  ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset);
  1855.   writel(CommandMailbox->Words[1],
  1856.  ControllerBaseAddress + DAC960_PG_MailboxRegister4Offset);
  1857.   writel(CommandMailbox->Words[2],
  1858.  ControllerBaseAddress + DAC960_PG_MailboxRegister8Offset);
  1859.   writeb(CommandMailbox->Bytes[12],
  1860.  ControllerBaseAddress + DAC960_PG_MailboxRegister12Offset);
  1861. }
  1863. static inline DAC960_V1_CommandIdentifier_T
  1864. DAC960_PG_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress)
  1865. {
  1866.   return readb(ControllerBaseAddress
  1867.        + DAC960_PG_StatusCommandIdentifierRegOffset);
  1868. }
  1870. static inline DAC960_V1_CommandStatus_T
  1871. DAC960_PG_ReadStatusRegister(void __iomem *ControllerBaseAddress)
  1872. {
  1873.   return readw(ControllerBaseAddress + DAC960_PG_StatusRegisterOffset);
  1874. }
  1876. static inline boolean
  1877. DAC960_PG_ReadErrorStatus(void __iomem *ControllerBaseAddress,
  1878.   unsigned char *ErrorStatus,
  1879.   unsigned char *Parameter0,
  1880.   unsigned char *Parameter1)
  1881. {
  1882.   DAC960_PG_ErrorStatusRegister_T ErrorStatusRegister;
  1883.   ErrorStatusRegister.All =
  1884.     readb(ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset);
  1885.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  1886.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  1887.   *ErrorStatus = ErrorStatusRegister.All;
  1888.   *Parameter0 =
  1889.     readb(ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset);
  1890.   *Parameter1 =
  1891.     readb(ControllerBaseAddress + DAC960_PG_CommandIdentifierRegisterOffset);
  1892.   writeb(0, ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset);
  1893.   return true;
  1894. }
  1896. /*
  1897.   Define the DAC960 PD Series Controller Interface Register Offsets.
  1898. */
  1900. #define DAC960_PD_RegisterWindowSize 0x80
  1902. typedef enum
  1903. {
  1904.   DAC960_PD_CommandOpcodeRegisterOffset = 0x00,
  1905.   DAC960_PD_CommandIdentifierRegisterOffset = 0x01,
  1906.   DAC960_PD_MailboxRegister2Offset = 0x02,
  1907.   DAC960_PD_MailboxRegister3Offset = 0x03,
  1908.   DAC960_PD_MailboxRegister4Offset = 0x04,
  1909.   DAC960_PD_MailboxRegister5Offset = 0x05,
  1910.   DAC960_PD_MailboxRegister6Offset = 0x06,
  1911.   DAC960_PD_MailboxRegister7Offset = 0x07,
  1912.   DAC960_PD_MailboxRegister8Offset = 0x08,
  1913.   DAC960_PD_MailboxRegister9Offset = 0x09,
  1914.   DAC960_PD_MailboxRegister10Offset = 0x0A,
  1915.   DAC960_PD_MailboxRegister11Offset = 0x0B,
  1916.   DAC960_PD_MailboxRegister12Offset = 0x0C,
  1917.   DAC960_PD_StatusCommandIdentifierRegOffset = 0x0D,
  1918.   DAC960_PD_StatusRegisterOffset = 0x0E,
  1919.   DAC960_PD_ErrorStatusRegisterOffset = 0x3F,
  1920.   DAC960_PD_InboundDoorBellRegisterOffset = 0x40,
  1921.   DAC960_PD_OutboundDoorBellRegisterOffset = 0x41,
  1922.   DAC960_PD_InterruptEnableRegisterOffset = 0x43
  1923. }
  1924. DAC960_PD_RegisterOffsets_T;
  1927. /*
  1928.   Define the structure of the DAC960 PD Series Inbound Door Bell Register.
  1929. */
  1931. typedef union DAC960_PD_InboundDoorBellRegister
  1932. {
  1933.   unsigned char All;
  1934.   struct {
  1935.     boolean NewCommand:1; /* Bit 0 */
  1936.     boolean AcknowledgeStatus:1; /* Bit 1 */
  1937.     boolean GenerateInterrupt:1; /* Bit 2 */
  1938.     boolean ControllerReset:1; /* Bit 3 */
  1939.     unsigned char :4; /* Bits 4-7 */
  1940.   } Write;
  1941.   struct {
  1942.     boolean MailboxFull:1; /* Bit 0 */
  1943.     boolean InitializationInProgress:1; /* Bit 1 */
  1944.     unsigned char :6; /* Bits 2-7 */
  1945.   } Read;
  1946. }
  1947. DAC960_PD_InboundDoorBellRegister_T;
  1950. /*
  1951.   Define the structure of the DAC960 PD Series Outbound Door Bell Register.
  1952. */
  1954. typedef union DAC960_PD_OutboundDoorBellRegister
  1955. {
  1956.   unsigned char All;
  1957.   struct {
  1958.     boolean AcknowledgeInterrupt:1; /* Bit 0 */
  1959.     unsigned char :7; /* Bits 1-7 */
  1960.   } Write;
  1961.   struct {
  1962.     boolean StatusAvailable:1; /* Bit 0 */
  1963.     unsigned char :7; /* Bits 1-7 */
  1964.   } Read;
  1965. }
  1966. DAC960_PD_OutboundDoorBellRegister_T;
  1969. /*
  1970.   Define the structure of the DAC960 PD Series Interrupt Enable Register.
  1971. */
  1973. typedef union DAC960_PD_InterruptEnableRegister
  1974. {
  1975.   unsigned char All;
  1976.   struct {
  1977.     boolean EnableInterrupts:1; /* Bit 0 */
  1978.     unsigned char :7; /* Bits 1-7 */
  1979.   } Bits;
  1980. }
  1981. DAC960_PD_InterruptEnableRegister_T;
  1984. /*
  1985.   Define the structure of the DAC960 PD Series Error Status Register.
  1986. */
  1988. typedef union DAC960_PD_ErrorStatusRegister
  1989. {
  1990.   unsigned char All;
  1991.   struct {
  1992.     unsigned int :2; /* Bits 0-1 */
  1993.     boolean ErrorStatusPending:1; /* Bit 2 */
  1994.     unsigned int :5; /* Bits 3-7 */
  1995.   } Bits;
  1996. }
  1997. DAC960_PD_ErrorStatusRegister_T;
  2000. /*
  2001.   Define inline functions to provide an abstraction for reading and writing the
  2002.   DAC960 PD Series Controller Interface Registers.
  2003. */
  2005. static inline
  2006. void DAC960_PD_NewCommand(void __iomem *ControllerBaseAddress)
  2007. {
  2008.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  2009.   InboundDoorBellRegister.All = 0;
  2010.   InboundDoorBellRegister.Write.NewCommand = true;
  2011.   writeb(InboundDoorBellRegister.All,
  2012.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  2013. }
  2015. static inline
  2016. void DAC960_PD_AcknowledgeStatus(void __iomem *ControllerBaseAddress)
  2017. {
  2018.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  2019.   InboundDoorBellRegister.All = 0;
  2020.   InboundDoorBellRegister.Write.AcknowledgeStatus = true;
  2021.   writeb(InboundDoorBellRegister.All,
  2022.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  2023. }
  2025. static inline
  2026. void DAC960_PD_GenerateInterrupt(void __iomem *ControllerBaseAddress)
  2027. {
  2028.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  2029.   InboundDoorBellRegister.All = 0;
  2030.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  2031.   writeb(InboundDoorBellRegister.All,
  2032.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  2033. }
  2035. static inline
  2036. void DAC960_PD_ControllerReset(void __iomem *ControllerBaseAddress)
  2037. {
  2038.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  2039.   InboundDoorBellRegister.All = 0;
  2040.   InboundDoorBellRegister.Write.ControllerReset = true;
  2041.   writeb(InboundDoorBellRegister.All,
  2042.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  2043. }
  2045. static inline
  2046. boolean DAC960_PD_MailboxFullP(void __iomem *ControllerBaseAddress)
  2047. {
  2048.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  2049.   InboundDoorBellRegister.All =
  2050.     readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  2051.   return InboundDoorBellRegister.Read.MailboxFull;
  2052. }
  2054. static inline
  2055. boolean DAC960_PD_InitializationInProgressP(void __iomem *ControllerBaseAddress)
  2056. {
  2057.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  2058.   InboundDoorBellRegister.All =
  2059.     readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  2060.   return InboundDoorBellRegister.Read.InitializationInProgress;
  2061. }
  2063. static inline
  2064. void DAC960_PD_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress)
  2065. {
  2066.   DAC960_PD_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  2067.   OutboundDoorBellRegister.All = 0;
  2068.   OutboundDoorBellRegister.Write.AcknowledgeInterrupt = true;
  2069.   writeb(OutboundDoorBellRegister.All,
  2070.  ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset);
  2071. }
  2073. static inline
  2074. boolean DAC960_PD_StatusAvailableP(void __iomem *ControllerBaseAddress)
  2075. {
  2076.   DAC960_PD_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  2077.   OutboundDoorBellRegister.All =
  2078.     readb(ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset);
  2079.   return OutboundDoorBellRegister.Read.StatusAvailable;
  2080. }
  2082. static inline
  2083. void DAC960_PD_EnableInterrupts(void __iomem *ControllerBaseAddress)
  2084. {
  2085.   DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
  2086.   InterruptEnableRegister.All = 0;
  2087.   InterruptEnableRegister.Bits.EnableInterrupts = true;
  2088.   writeb(InterruptEnableRegister.All,
  2089.  ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset);
  2090. }
  2092. static inline
  2093. void DAC960_PD_DisableInterrupts(void __iomem *ControllerBaseAddress)
  2094. {
  2095.   DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
  2096.   InterruptEnableRegister.All = 0;
  2097.   InterruptEnableRegister.Bits.EnableInterrupts = false;
  2098.   writeb(InterruptEnableRegister.All,
  2099.  ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset);
  2100. }
  2102. static inline
  2103. boolean DAC960_PD_InterruptsEnabledP(void __iomem *ControllerBaseAddress)
  2104. {
  2105.   DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
  2106.   InterruptEnableRegister.All =
  2107.     readb(ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset);
  2108.   return InterruptEnableRegister.Bits.EnableInterrupts;
  2109. }
  2111. static inline
  2112. void DAC960_PD_WriteCommandMailbox(void __iomem *ControllerBaseAddress,
  2113.    DAC960_V1_CommandMailbox_T *CommandMailbox)
  2114. {
  2115.   writel(CommandMailbox->Words[0],
  2116.  ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset);
  2117.   writel(CommandMailbox->Words[1],
  2118.  ControllerBaseAddress + DAC960_PD_MailboxRegister4Offset);
  2119.   writel(CommandMailbox->Words[2],
  2120.  ControllerBaseAddress + DAC960_PD_MailboxRegister8Offset);
  2121.   writeb(CommandMailbox->Bytes[12],
  2122.  ControllerBaseAddress + DAC960_PD_MailboxRegister12Offset);
  2123. }
  2125. static inline DAC960_V1_CommandIdentifier_T
  2126. DAC960_PD_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress)
  2127. {
  2128.   return readb(ControllerBaseAddress
  2129.        + DAC960_PD_StatusCommandIdentifierRegOffset);
  2130. }
  2132. static inline DAC960_V1_CommandStatus_T
  2133. DAC960_PD_ReadStatusRegister(void __iomem *ControllerBaseAddress)
  2134. {
  2135.   return readw(ControllerBaseAddress + DAC960_PD_StatusRegisterOffset);
  2136. }
  2138. static inline boolean
  2139. DAC960_PD_ReadErrorStatus(void __iomem *ControllerBaseAddress,
  2140.   unsigned char *ErrorStatus,
  2141.   unsigned char *Parameter0,
  2142.   unsigned char *Parameter1)
  2143. {
  2144.   DAC960_PD_ErrorStatusRegister_T ErrorStatusRegister;
  2145.   ErrorStatusRegister.All =
  2146.     readb(ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset);
  2147.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  2148.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  2149.   *ErrorStatus = ErrorStatusRegister.All;
  2150.   *Parameter0 =
  2151.     readb(ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset);
  2152.   *Parameter1 =
  2153.     readb(ControllerBaseAddress + DAC960_PD_CommandIdentifierRegisterOffset);
  2154.   writeb(0, ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset);
  2155.   return true;
  2156. }
  2158. static inline void DAC960_P_To_PD_TranslateEnquiry(void *Enquiry)
  2159. {
  2160.   memcpy(Enquiry + 132, Enquiry + 36, 64);
  2161.   memset(Enquiry + 36, 0, 96);
  2162. }
  2164. static inline void DAC960_P_To_PD_TranslateDeviceState(void *DeviceState)
  2165. {
  2166.   memcpy(DeviceState + 2, DeviceState + 3, 1);
  2167.   memcpy(DeviceState + 4, DeviceState + 5, 2);
  2168.   memcpy(DeviceState + 6, DeviceState + 8, 4);
  2169. }
  2171. static inline
  2172. void DAC960_PD_To_P_TranslateReadWriteCommand(DAC960_V1_CommandMailbox_T
  2173.       *CommandMailbox)
  2174. {
  2175.   int LogicalDriveNumber = CommandMailbox->Type5.LD.LogicalDriveNumber;
  2176.   CommandMailbox->Bytes[3] &= 0x7;
  2177.   CommandMailbox->Bytes[3] |= CommandMailbox->Bytes[7] << 6;
  2178.   CommandMailbox->Bytes[7] = LogicalDriveNumber;
  2179. }
  2181. static inline
  2182. void DAC960_P_To_PD_TranslateReadWriteCommand(DAC960_V1_CommandMailbox_T
  2183.       *CommandMailbox)
  2184. {
  2185.   int LogicalDriveNumber = CommandMailbox->Bytes[7];
  2186.   CommandMailbox->Bytes[7] = CommandMailbox->Bytes[3] >> 6;
  2187.   CommandMailbox->Bytes[3] &= 0x7;
  2188.   CommandMailbox->Bytes[3] |= LogicalDriveNumber << 3;
  2189. }
  2192. /*
  2193.   Define prototypes for the forward referenced DAC960 Driver Internal Functions.
  2194. */
  2196. static void DAC960_FinalizeController(DAC960_Controller_T *);
  2197. static void DAC960_V1_QueueReadWriteCommand(DAC960_Command_T *);
  2198. static void DAC960_V2_QueueReadWriteCommand(DAC960_Command_T *); 
  2199. static void DAC960_RequestFunction(struct request_queue *);
  2200. static irqreturn_t DAC960_BA_InterruptHandler(int, void *, struct pt_regs *);
  2201. static irqreturn_t DAC960_LP_InterruptHandler(int, void *, struct pt_regs *);
  2202. static irqreturn_t DAC960_LA_InterruptHandler(int, void *, struct pt_regs *);
  2203. static irqreturn_t DAC960_PG_InterruptHandler(int, void *, struct pt_regs *);
  2204. static irqreturn_t DAC960_PD_InterruptHandler(int, void *, struct pt_regs *);
  2205. static irqreturn_t DAC960_P_InterruptHandler(int, void *, struct pt_regs *);
  2206. static void DAC960_V1_QueueMonitoringCommand(DAC960_Command_T *);
  2207. static void DAC960_V2_QueueMonitoringCommand(DAC960_Command_T *);
  2208. static void DAC960_MonitoringTimerFunction(unsigned long);
  2209. static void DAC960_Message(DAC960_MessageLevel_T, unsigned char *,
  2210.    DAC960_Controller_T *, ...);
  2211. static void DAC960_CreateProcEntries(DAC960_Controller_T *);
  2212. static void DAC960_DestroyProcEntries(DAC960_Controller_T *);
  2214. #endif /* DAC960_DriverVersion */