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alucore_rtl.vhd
资源名称：8051的内核(vhdl).zip　[点击查看]
上传用户：sztwq510
上传日期：2007-04-20
资源大小：209k
文件大小：7k
源码类别：

VHDL/FPGA/Verilog

开发平台：

Matlab

alucore_rtl.vhd：源码内容
  1. -------------------------------------------------------------------------------
  2. --                                                                           --
  3. --          X       X   XXXXXX    XXXXXX    XXXXXX    XXXXXX      X          --
  4. --          XX     XX  X      X  X      X  X      X  X           XX          --
  5. --          X X   X X  X         X      X  X      X  X          X X          --
  6. --          X  X X  X  X         X      X  X      X  X         X  X          --
  7. --          X   X   X  X          XXXXXX   X      X   XXXXXX      X          --
  8. --          X       X  X         X      X  X      X         X     X          --
  9. --          X       X  X         X      X  X      X         X     X          --
  10. --          X       X  X      X  X      X  X      X         X     X          --
  11. --          X       X   XXXXXX    XXXXXX    XXXXXX    XXXXXX      X          --
  12. --                                                                           --
  13. --                                                                           --
  14. --                       O R E G A N O   S Y S T E M S                       --
  15. --                                                                           --
  16. --                            Design & Consulting                            --
  17. --                                                                           --
  18. -------------------------------------------------------------------------------
  19. --                                                                           --
  20. --         Web:           http://www.oregano.at/                             --
  21. --                                                                           --
  22. --         Contact:       mc8051@oregano.at                                  --
  23. --                                                                           --
  24. -------------------------------------------------------------------------------
  25. --                                                                           --
  26. --  MC8051 - VHDL 8051 Microcontroller IP Core                               --
  27. --  Copyright (C) 2001 OREGANO SYSTEMS                                       --
  28. --                                                                           --
  29. --  This library is free software; you can redistribute it and/or            --
  30. --  modify it under the terms of the GNU Lesser General Public               --
  31. --  License as published by the Free Software Foundation; either             --
  32. --  version 2.1 of the License, or (at your option) any later version.       --
  33. --                                                                           --
  34. --  This library is distributed in the hope that it will be useful,          --
  35. --  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
  36. --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
  37. --  Lesser General Public License for more details.                          --
  38. --                                                                           --
  39. --  Full details of the license can be found in the file LGPL.TXT.           --
  40. --                                                                           --
  41. --  You should have received a copy of the GNU Lesser General Public         --
  42. --  License along with this library; if not, write to the Free Software      --
  43. --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
  44. --                                                                           --
  45. -------------------------------------------------------------------------------
  46. --
  47. --
  48. --         Author:                 Roland H鰈ler
  49. --
  50. --         Filename:               alucore_rtl.vhd
  51. --
  52. --         Date of Creation:       Mon Aug  9 12:14:48 1999
  53. --
  54. --         Version:                $Revision: 1.5 $
  55. --
  56. --         Date of Latest Version: $Date: 2002/01/07 12:17:44 $
  57. --
  58. --
  59. --         Description: This unit performs simple logical operations.
  60. --
  61. --
  62. --
  63. --
  64. -------------------------------------------------------------------------------
  65. architecture rtl of alucore is
  67.   constant LAND : std_logic_vector(3 downto 0) := "0011";
  68.   constant LOR  : std_logic_vector(3 downto 0) := "0101";
  69.   constant LXOR : std_logic_vector(3 downto 0) := "0110";
  70.   constant RL   : std_logic_vector(3 downto 0) := "0111";
  71.   constant RLC  : std_logic_vector(3 downto 0) := "1000";
  72.   constant RR   : std_logic_vector(3 downto 0) := "1001";
  73.   constant RRC  : std_logic_vector(3 downto 0) := "1010";
  74.   constant COMP : std_logic_vector(3 downto 0) := "1011";
  75.   constant INV  : std_logic_vector(3 downto 0) := "1100";
  77. begin                 -- architecture structural
  79.   p_alu: process (alu_cmd_i, op_a_i, op_b_i, cy_i)
  81.   begin
  82.   
  83.   case alu_cmd_i is
  84. -------------------------------------------------------------------------------
  85.     when LAND =>  -- op_a_i and op_b_i
  86.       result_o <= op_a_i and op_b_i;
  87.       cy_o <= cy_i;      
  88. -------------------------------------------------------------------------------
  89.     when LOR =>  -- op_a_i or op_b_i
  90.       result_o <= op_a_i or op_b_i;
  91.       cy_o <= cy_i;      
  92. -------------------------------------------------------------------------------
  93.     when LXOR =>  -- op_a_i xor op_b_i
  94.       result_o <= op_a_i xor op_b_i;
  95.       cy_o <= cy_i;      
  96. -------------------------------------------------------------------------------
  97.     when RL =>  -- rotate left op_a_i
  98.       if DWIDTH > 1 then
  99.         result_o(DWIDTH-1 downto 1) <= op_a_i(DWIDTH-2 downto 0);
  100. result_o(0) <= op_a_i(DWIDTH-1);
  101.       else
  102.         result_o <= op_a_i;
  103.       end if;
  104.       cy_o <= cy_i;      
  105. -------------------------------------------------------------------------------
  106.     when RLC =>  -- rotate left op_a_i with CY
  107.       if DWIDTH > 1 then
  108.         result_o(DWIDTH-1 downto 1) <= op_a_i(DWIDTH-2 downto 0);
  109. result_o(0) <= cy_i((DWIDTH-1)/4);
  110.       else
  111.         result_o(0) <= cy_i((DWIDTH-1)/4);
  112.       end if;
  113.       cy_o <= cy_i;      
  114.       cy_o((DWIDTH-1)/4) <= op_a_i(DWIDTH-1);      
  115. -------------------------------------------------------------------------------
  116.     when RR =>  -- rotate right op_a_i
  117.       if DWIDTH > 1 then
  118.         result_o(DWIDTH-2 downto 0) <= op_a_i(DWIDTH-1 downto 1);
  119. result_o(DWIDTH-1) <= op_a_i(0);
  120.       else
  121.         result_o <= op_a_i;
  122.       end if;
  123.       cy_o <= cy_i;      
  124. -------------------------------------------------------------------------------
  125.     when RRC =>  -- rotate right op_a_i with CY
  126.       if DWIDTH > 1 then
  127.         result_o(DWIDTH-2 downto 0) <= op_a_i(DWIDTH-1 downto 1);
  128. result_o(DWIDTH-1) <= cy_i((DWIDTH-1)/4);
  129.       else
  130.         result_o(0) <= cy_i((DWIDTH-1)/4);
  131.       end if;
  132.       cy_o <= cy_i;      
  133.       cy_o((DWIDTH-1)/4) <= op_a_i(0);      
  134. -------------------------------------------------------------------------------
  135.     when COMP =>  -- Compare op_a_i with op_b_i
  136.       if op_a_i = op_b_i then
  137.         result_o <= (others => '0');
  138.       else
  139.         result_o <= (others => '1');
  140.       end if;
  141.       cy_o <= cy_i;         
  142.       if op_a_i < op_b_i then
  143.         cy_o((DWIDTH-1)/4) <= '1';
  144.       else
  145.         cy_o((DWIDTH-1)/4) <= '0';          
  146.       end if;
  147. -------------------------------------------------------------------------------
  148.     when INV =>  -- invert op_a_i
  149.       result_o <= not(op_a_i);
  150.       cy_o <= cy_i;      
  151. -------------------------------------------------------------------------------
  152.     when others =>  -- turn unit off
  153.       result_o <= (others => '0');      
  154.       cy_o <= (others => '0');
  155. -------------------------------------------------------------------------------
  156.   end case;
  157.   
  158.  end process p_alu;
  160. end rtl;