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comb_divider_.vhd
上传用户：sztwq510
上传日期：2007-04-20
资源大小：209k
文件大小：5k
源码类别：
VHDL/FPGA/Verilog
开发平台：
Matlab
- -------------------------------------------------------------------------------
- -- --
- -- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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- -- --
- -- --
- -- O R E G A N O S Y S T E M S --
- -- --
- -- Design & Consulting --
- -- --
- -------------------------------------------------------------------------------
- -- --
- -- Web: http://www.oregano.at/ --
- -- --
- -- Contact: mc8051@oregano.at --
- -- --
- -------------------------------------------------------------------------------
- -- --
- -- MC8051 - VHDL 8051 Microcontroller IP Core --
- -- Copyright (C) 2001 OREGANO SYSTEMS --
- -- --
- -- This library is free software; you can redistribute it and/or --
- -- modify it under the terms of the GNU Lesser General Public --
- -- License as published by the Free Software Foundation; either --
- -- version 2.1 of the License, or (at your option) any later version. --
- -- --
- -- This library is distributed in the hope that it will be useful, --
- -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
- -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
- -- Lesser General Public License for more details. --
- -- --
- -- Full details of the license can be found in the file LGPL.TXT. --
- -- --
- -- You should have received a copy of the GNU Lesser General Public --
- -- License along with this library; if not, write to the Free Software --
- -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
- -- --
- -------------------------------------------------------------------------------
- --
- --
- -- Author: Roland H鰈ler
- --
- -- Filename: comb_divider_.vhd
- --
- -- Date of Creation: Mon Aug 9 12:14:48 1999
- --
- -- Version: $Revision: 1.4 $
- --
- -- Date of Latest Version: $Date: 2002/01/07 12:17:44 $
- --
- --
- -- Description: Divider with parameteriseable data width. Realised
- -- using combinational logic only.
- --
- --
- --
- --
- -------------------------------------------------------------------------------
- library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_arith.all;
- -----------------------------ENTITY DECLARATION--------------------------------
- entity comb_divider is
- generic (DWIDTH : integer := 8);
- port (dvdnd_i : in std_logic_vector(DWIDTH-1 downto 0); -- Dividend
- dvsor_i : in std_logic_vector(DWIDTH-1 downto 0); -- Divisor
- qutnt_o : out std_logic_vector(DWIDTH-1 downto 0); -- Quotient
- rmndr_o : out std_logic_vector(DWIDTH-1 downto 0)); -- Remainder
- end comb_divider;
