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alumux_rtl.vhd
资源名称：8051的内核(vhdl).zip　[点击查看]
上传用户：sztwq510
上传日期：2007-04-20
资源大小：209k
文件大小：18k
源码类别：

VHDL/FPGA/Verilog

开发平台：

Matlab

alumux_rtl.vhd：源码内容
  1. -------------------------------------------------------------------------------
  2. --                                                                           --
  3. --          X       X   XXXXXX    XXXXXX    XXXXXX    XXXXXX      X          --
  4. --          XX     XX  X      X  X      X  X      X  X           XX          --
  5. --          X X   X X  X         X      X  X      X  X          X X          --
  6. --          X  X X  X  X         X      X  X      X  X         X  X          --
  7. --          X   X   X  X          XXXXXX   X      X   XXXXXX      X          --
  8. --          X       X  X         X      X  X      X         X     X          --
  9. --          X       X  X         X      X  X      X         X     X          --
  10. --          X       X  X      X  X      X  X      X         X     X          --
  11. --          X       X   XXXXXX    XXXXXX    XXXXXX    XXXXXX      X          --
  12. --                                                                           --
  13. --                                                                           --
  14. --                       O R E G A N O   S Y S T E M S                       --
  15. --                                                                           --
  16. --                            Design & Consulting                            --
  17. --                                                                           --
  18. -------------------------------------------------------------------------------
  19. --                                                                           --
  20. --         Web:           http://www.oregano.at/                             --
  21. --                                                                           --
  22. --         Contact:       mc8051@oregano.at                                  --
  23. --                                                                           --
  24. -------------------------------------------------------------------------------
  25. --                                                                           --
  26. --  MC8051 - VHDL 8051 Microcontroller IP Core                               --
  27. --  Copyright (C) 2001 OREGANO SYSTEMS                                       --
  28. --                                                                           --
  29. --  This library is free software; you can redistribute it and/or            --
  30. --  modify it under the terms of the GNU Lesser General Public               --
  31. --  License as published by the Free Software Foundation; either             --
  32. --  version 2.1 of the License, or (at your option) any later version.       --
  33. --                                                                           --
  34. --  This library is distributed in the hope that it will be useful,          --
  35. --  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
  36. --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
  37. --  Lesser General Public License for more details.                          --
  38. --                                                                           --
  39. --  Full details of the license can be found in the file LGPL.TXT.           --
  40. --                                                                           --
  41. --  You should have received a copy of the GNU Lesser General Public         --
  42. --  License along with this library; if not, write to the Free Software      --
  43. --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
  44. --                                                                           --
  45. -------------------------------------------------------------------------------
  46. --
  47. --
  48. --         Author:                 Roland H鰈ler
  49. --
  50. --         Filename:               alumux_rtl.vhd
  51. --
  52. --         Date of Creation:       Mon Aug  9 12:14:48 1999
  53. --
  54. --         Version:                $Revision: 1.6 $
  55. --
  56. --         Date of Latest Version: $Date: 2002/01/07 12:17:44 $
  57. --
  58. --
  59. --         Description: Select data path according to the actual command.
  60. --
  61. --
  62. --
  63. --
  64. -------------------------------------------------------------------------------
  65. architecture rtl of alumux is
  67.   constant DA             : std_logic_vector(5 downto 0) := "100000";
  68.   constant ADD_ACC_RAM    : std_logic_vector(5 downto 0) := "100001";
  69.   constant ADD_ACC_ROM    : std_logic_vector(5 downto 0) := "100010";
  70.   constant ADDC_ACC_RAM   : std_logic_vector(5 downto 0) := "100011";
  71.   constant ADDC_ACC_ROM   : std_logic_vector(5 downto 0) := "100100";
  72.   constant AND_ACC_RAM    : std_logic_vector(5 downto 0) := "100101";
  73.   constant AND_ACC_ROM    : std_logic_vector(5 downto 0) := "100110";
  74.   constant AND_RAM_ROM    : std_logic_vector(5 downto 0) := "100111";
  75.   constant SUB_ACC_RAM    : std_logic_vector(5 downto 0) := "101000";
  76.   constant SUB_ACC_ROM    : std_logic_vector(5 downto 0) := "101001";
  77.   constant MUL_ACC_RAM    : std_logic_vector(5 downto 0) := "101010";
  78.   constant DIV_ACC_RAM    : std_logic_vector(5 downto 0) := "101011";
  79.   constant OR_RAM_ACC     : std_logic_vector(5 downto 0) := "101100";
  80.   constant OR_ROM_ACC     : std_logic_vector(5 downto 0) := "101101";
  81.   constant OR_ROM_RAM     : std_logic_vector(5 downto 0) := "101110";
  82.   constant XOR_RAM_ACC    : std_logic_vector(5 downto 0) := "101111";
  83.   constant XOR_ROM_ACC    : std_logic_vector(5 downto 0) := "110000";
  84.   constant XOR_ROM_RAM    : std_logic_vector(5 downto 0) := "110001";
  85.   constant RL_ACC         : std_logic_vector(5 downto 0) := "110010";
  86.   constant RLC_ACC        : std_logic_vector(5 downto 0) := "110011";
  87.   constant RR_ACC         : std_logic_vector(5 downto 0) := "110100";
  88.   constant RRC_ACC        : std_logic_vector(5 downto 0) := "110101";
  89.   constant INV_ACC        : std_logic_vector(5 downto 0) := "110110";
  90.   constant INV_RAM        : std_logic_vector(5 downto 0) := "110111";
  91.   constant DEC_ACC        : std_logic_vector(5 downto 0) := "111000";
  92.   constant DEC_RAM        : std_logic_vector(5 downto 0) := "111001";
  93.   constant COMP_RAM_ACC   : std_logic_vector(5 downto 0) := "111010";
  94.   constant COMP_ROM_ACC   : std_logic_vector(5 downto 0) := "111011";
  95.   constant COMP_ROM_RAM   : std_logic_vector(5 downto 0) := "111100";
  96.   constant INC_ACC        : std_logic_vector(5 downto 0) := "111110";
  97.   constant INC_RAM        : std_logic_vector(5 downto 0) := "111111";
  99.   constant NOP  : std_logic_vector(3 downto 0) := "0000";
  100.   constant LAND : std_logic_vector(3 downto 0) := "0011";
  101.   constant LOR  : std_logic_vector(3 downto 0) := "0101";
  102.   constant LXOR : std_logic_vector(3 downto 0) := "0110";
  103.   constant RL   : std_logic_vector(3 downto 0) := "0111";
  104.   constant RLC  : std_logic_vector(3 downto 0) := "1000";
  105.   constant RR   : std_logic_vector(3 downto 0) := "1001";
  106.   constant RRC  : std_logic_vector(3 downto 0) := "1010";
  107.   constant COMP : std_logic_vector(3 downto 0) := "1011";
  108.   constant INV  : std_logic_vector(3 downto 0) := "1100";
  110. begin
  112.   -- Multiplex the input data and generate the command for the alu core.
  113.   p_alucore_mux : process (rom_data_i,
  114.                            ram_data_i,
  115.                            acc_i,     
  116.                            cmd_i)
  117.   begin
  118.     case cmd_i is
  119.        when AND_ACC_RAM   =>
  120.          alu_cmd_o <= LAND;
  121.          op_a_o    <= acc_i;
  122.          op_b_o    <= ram_data_i;
  123.        when AND_ACC_ROM   =>
  124.          alu_cmd_o <= LAND;
  125.          op_a_o    <= acc_i;
  126.          op_b_o    <= rom_data_i;
  127.        when AND_RAM_ROM   =>
  128.          alu_cmd_o <= LAND;
  129.          op_a_o    <= ram_data_i;
  130.          op_b_o    <= rom_data_i;
  131.        when OR_RAM_ACC    =>
  132.          alu_cmd_o <= LOR;
  133.          op_a_o    <= acc_i;
  134.          op_b_o    <= ram_data_i;
  135.        when OR_ROM_ACC    =>
  136.          alu_cmd_o <= LOR;
  137.          op_a_o    <= acc_i;
  138.          op_b_o    <= rom_data_i;
  139.        when OR_ROM_RAM    =>
  140.          alu_cmd_o <= LOR;
  141.          op_a_o    <= rom_data_i;
  142.          op_b_o    <= ram_data_i;
  143.        when XOR_RAM_ACC   =>
  144.          alu_cmd_o <= LXOR;
  145.          op_a_o    <= acc_i;
  146.          op_b_o    <= ram_data_i;
  147.        when XOR_ROM_ACC   =>
  148.          alu_cmd_o <= LXOR;
  149.          op_a_o    <= acc_i;
  150.          op_b_o    <= rom_data_i;
  151.        when XOR_ROM_RAM   =>
  152.          alu_cmd_o <= LXOR;
  153.          op_a_o    <= rom_data_i;
  154.          op_b_o    <= ram_data_i;
  155.        when RL_ACC        =>
  156.          alu_cmd_o <= RL;
  157.          op_a_o    <= acc_i;
  158.          op_b_o    <= ( others => '0' );
  159.        when RLC_ACC       =>
  160.          alu_cmd_o <= RLC;
  161.          op_a_o    <= acc_i;
  162.          op_b_o    <= ( others => '0' );
  163.        when RR_ACC        =>
  164.          alu_cmd_o <= RR;
  165.          op_a_o    <= acc_i;
  166.          op_b_o    <= ( others => '0' );
  167.        when RRC_ACC       =>          
  168.          alu_cmd_o <= RRC;            
  169.          op_a_o    <= acc_i;          
  170.          op_b_o    <= ( others => '0' );
  171.        when INV_ACC       =>          
  172.          alu_cmd_o <= INV;            
  173.          op_a_o    <= acc_i;          
  174.          op_b_o    <= ( others => '0' );
  175.        when INV_RAM       =>          
  176.          alu_cmd_o <= INV;            
  177.          op_a_o    <= ram_data_i;     
  178.          op_b_o    <= ( others => '0' );
  179.        when COMP_RAM_ACC  =>          
  180.          alu_cmd_o <= COMP;           
  181.          op_a_o    <= acc_i;          
  182.          op_b_o    <= ram_data_i;     
  183.        when COMP_ROM_ACC  =>          
  184.          alu_cmd_o <= COMP;           
  185.          op_a_o    <= acc_i;          
  186.          op_b_o    <= rom_data_i;     
  187.        when COMP_ROM_RAM  =>          
  188.          alu_cmd_o <= COMP;           
  189.          op_a_o    <= ram_data_i;     
  190.          op_b_o    <= rom_data_i;     
  191.        when others        =>          
  192.          alu_cmd_o <= NOP;            
  193.          op_a_o    <= ( others => '0' );
  194.          op_b_o    <= ( others => '0' );
  195.     end case;
  196.   end process p_alucore_mux;
  198.   -- Multiplex the input data for all the functions not included in the
  199.   -- alu core.
  200.   p_ext_mux : process (ram_data_i,
  201.                        rom_data_i,
  202.                        acc_i,
  203.        cy_i,
  204.                        cmd_i)
  205.   begin
  206.     case cmd_i is
  207.        when DA =>
  208.          dcml_data_o <= acc_i;
  209.          mltplcnd_o  <= ( others => '0' );
  210.          mltplctr_o  <= ( others => '0' );
  211.          dvdnd_o     <= ( others => '0' );
  212.          dvsor_o     <= ( others => '0' );
  213.          addsub_o    <= '0';
  214.          addsub_cy_o <= '0';
  215.          opa_o       <= ( others => '0' );
  216.          opb_o       <= ( others => '0' );
  217.        when DIV_ACC_RAM =>
  218.          dcml_data_o <= ( others => '0' );
  219.          mltplcnd_o  <= ( others => '0' );
  220.          mltplctr_o  <= ( others => '0' );
  221.          dvdnd_o     <= acc_i;
  222.          dvsor_o     <= ram_data_i;
  223.          addsub_o    <= '0';
  224.          addsub_cy_o <= '0';
  225.          opa_o       <= ( others => '0' );
  226.          opb_o       <= ( others => '0' );
  227.        when MUL_ACC_RAM =>
  228.          dcml_data_o <= ( others => '0' );
  229.          mltplcnd_o  <= acc_i;
  230.          mltplctr_o  <= ram_data_i;
  231.          dvdnd_o     <= ( others => '0' );
  232.          dvsor_o     <= ( others => '0' );
  233.          addsub_o    <= '0';
  234.          addsub_cy_o <= '0';
  235.          opa_o       <= ( others => '0' );
  236.          opb_o       <= ( others => '0' );
  237.        when INC_ACC =>
  238.          dcml_data_o <= ( others => '0' );
  239.          mltplcnd_o  <= ( others => '0' );
  240.          mltplctr_o  <= ( others => '0' );
  241.          dvdnd_o     <= ( others => '0' );
  242.          dvsor_o     <= ( others => '0' );
  243.          addsub_o    <= '1';
  244.          addsub_cy_o <= '0';
  245.          opa_o       <= acc_i;
  246.          opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));
  247.        when INC_RAM =>
  248.          dcml_data_o <= ( others => '0' );
  249.          mltplcnd_o  <= ( others => '0' );
  250.          mltplctr_o  <= ( others => '0' );
  251.          dvdnd_o     <= ( others => '0' );
  252.          dvsor_o     <= ( others => '0' );
  253.          addsub_o    <= '1';
  254.          addsub_cy_o <= '0';
  255.          opa_o       <= ram_data_i;
  256.          opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));
  257.        when DEC_ACC =>
  258.          dcml_data_o <= ( others => '0' );
  259.          mltplcnd_o  <= ( others => '0' );
  260.          mltplctr_o  <= ( others => '0' );
  261.          dvdnd_o     <= ( others => '0' );
  262.          dvsor_o     <= ( others => '0' );
  263.          addsub_o    <= '0';
  264.          addsub_cy_o <= '0';
  265.          opa_o       <= acc_i;
  266.          opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));
  267.        when DEC_RAM =>
  268.          dcml_data_o <= ( others => '0' );
  269.          mltplcnd_o  <= ( others => '0' );
  270.          mltplctr_o  <= ( others => '0' );
  271.          dvdnd_o     <= ( others => '0' );
  272.          dvsor_o     <= ( others => '0' );
  273.          addsub_o    <= '0';
  274.          addsub_cy_o <= '0';
  275.          opa_o       <= ram_data_i;
  276.          opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));
  277.        when SUB_ACC_RAM =>
  278.          dcml_data_o <= ( others => '0' );
  279.          mltplcnd_o  <= ( others => '0' );
  280.          mltplctr_o  <= ( others => '0' );
  281.          dvdnd_o     <= ( others => '0' );
  282.          dvsor_o     <= ( others => '0' );
  283.          addsub_o    <= '0';
  284.          addsub_cy_o <= cy_i((DWIDTH-1)/4);
  285.          opa_o       <= acc_i;
  286.          opb_o       <= ram_data_i;
  287.        when SUB_ACC_ROM =>
  288.          dcml_data_o <= ( others => '0' );
  289.          mltplcnd_o  <= ( others => '0' );
  290.          mltplctr_o  <= ( others => '0' );
  291.          dvdnd_o     <= ( others => '0' );
  292.          dvsor_o     <= ( others => '0' );
  293.          addsub_o    <= '0';
  294.          addsub_cy_o <= cy_i((DWIDTH-1)/4);
  295.          opa_o       <= acc_i;
  296.          opb_o       <= rom_data_i;
  297.        when ADD_ACC_RAM =>
  298.          dcml_data_o <= ( others => '0' );
  299.          mltplcnd_o  <= ( others => '0' );
  300.          mltplctr_o  <= ( others => '0' );
  301.          dvdnd_o     <= ( others => '0' );
  302.          dvsor_o     <= ( others => '0' );
  303.          addsub_o    <= '1';
  304.          addsub_cy_o <= '0';
  305.          opa_o       <= acc_i;
  306.          opb_o       <= ram_data_i;
  307.        when ADD_ACC_ROM =>
  308.          dcml_data_o <= ( others => '0' );
  309.          mltplcnd_o  <= ( others => '0' );
  310.          mltplctr_o  <= ( others => '0' );
  311.          dvdnd_o     <= ( others => '0' );
  312.          dvsor_o     <= ( others => '0' );
  313.          addsub_o    <= '1';
  314.          addsub_cy_o <= '0';
  315.          opa_o       <= acc_i;
  316.          opb_o       <= rom_data_i;
  317.        when ADDC_ACC_RAM =>
  318.          dcml_data_o <= ( others => '0' );
  319.          mltplcnd_o  <= ( others => '0' );
  320.          mltplctr_o  <= ( others => '0' );
  321.          dvdnd_o     <= ( others => '0' );
  322.          dvsor_o     <= ( others => '0' );
  323.          addsub_o    <= '1';
  324.          addsub_cy_o <= cy_i((DWIDTH-1)/4);
  325.          opa_o       <= acc_i;
  326.          opb_o       <= ram_data_i;
  327.        when ADDC_ACC_ROM =>
  328.          dcml_data_o <= ( others => '0' );
  329.          mltplcnd_o  <= ( others => '0' );
  330.          mltplctr_o  <= ( others => '0' );
  331.          dvdnd_o     <= ( others => '0' );
  332.          dvsor_o     <= ( others => '0' );
  333.          addsub_o    <= '1';
  334.          addsub_cy_o <= cy_i((DWIDTH-1)/4);
  335.          opa_o       <= acc_i;
  336.          opb_o       <= rom_data_i;
  337.        when others =>
  338.          dcml_data_o <= ( others => '0' );
  339.          mltplcnd_o  <= ( others => '0' );
  340.          mltplctr_o  <= ( others => '0' );
  341.          dvdnd_o     <= ( others => '0' );
  342.          dvsor_o     <= ( others => '0' );
  343.          addsub_o    <= '0';
  344.          addsub_cy_o <= '0';
  345.          opa_o       <= ( others => '0' );
  346.          opb_o       <= ( others => '0' );
  347.     end case;
  348.   end process p_ext_mux;
  350.   -- Multiplex the results for all the units contributing to the ALU.
  351.   p_rslt_mux : process (ram_data_i,
  352.                         cy_i,
  353.                         ov_i,
  354.                         product_i,
  355.                         qutnt_i,
  356.                         rmndr_i,
  357.                         result_i,
  358.                         new_cy_i,
  359. addsub_rslt_i,
  360. addsub_cy_i,
  361. addsub_ov_i,
  362.                         dcml_data_i,
  363.                         dcml_cy_i,
  364.                         cmd_i)
  365.   begin
  366.     case cmd_i is
  367.        when DA          =>
  368.  if (C_IMPL_DA /= 0) then
  369.            result_a_o         <= dcml_data_i;
  370.            result_b_o         <= ( others => '0' );
  371.            cy_o               <= cy_i;
  372.            cy_o((DWIDTH-1)/4) <= dcml_cy_i;
  373.            ov_o               <= ov_i;
  374.  else  
  375.            result_a_o         <= ( others => '0' );
  376.            result_b_o         <= ( others => '0' );
  377.            cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
  378.            ov_o               <= '0';
  379.  end if;
  380.        when DIV_ACC_RAM =>
  381.  if (C_IMPL_DIV /= 0) then
  382.            result_a_o         <= qutnt_i;
  383.            result_b_o         <= rmndr_i;
  384.            cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
  385.            if ram_data_i = conv_std_logic_vector(0,DWIDTH) then
  386.              ov_o             <= '1';
  387.            else
  388.              ov_o             <= '0';
  389.            end if;
  390.  else
  391.            result_a_o         <= ( others => '0' );
  392.            result_b_o         <= ( others => '0' );
  393.            cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
  394.    ov_o               <= '0';
  395.  end if;
  396.        when MUL_ACC_RAM =>
  397.  if (C_IMPL_MUL /= 0) then
  398.            result_a_o         <= product_i(DWIDTH-1 downto 0);
  399.            result_b_o         <= product_i(DWIDTH*2-1 downto DWIDTH);
  400.            cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
  401.            if product_i(DWIDTH*2-1 downto DWIDTH)
  402.                = conv_std_logic_vector(0, DWIDTH) then
  403.              ov_o             <= '0';
  404.            else
  405.              ov_o             <= '1';
  406.            end if;
  407.  else
  408.            result_a_o         <= ( others => '0' );
  409.            result_b_o         <= ( others => '0' );
  410.            cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
  411.            ov_o               <= '0';
  412.  end if;
  413.        when SUB_ACC_RAM | SUB_ACC_ROM | ADD_ACC_RAM | ADD_ACC_ROM |
  414.     ADDC_ACC_RAM | ADDC_ACC_ROM  =>
  415.          result_a_o         <= addsub_rslt_i;
  416.          result_b_o         <= ( others => '0' );
  417.          cy_o               <= addsub_cy_i;
  418.          ov_o               <= addsub_ov_i;
  419.        when INC_ACC | INC_RAM | DEC_ACC | DEC_RAM =>
  420.          result_a_o         <= addsub_rslt_i;
  421.          result_b_o         <= ( others => '0' );
  422.          cy_o               <= cy_i;
  423.          ov_o               <= addsub_ov_i;  
  424.        when others      =>
  425.          result_a_o         <= result_i;
  426.          result_b_o         <= ( others => '0' );
  427.          cy_o               <= new_cy_i;
  428.          ov_o               <= ov_i;
  429.     end case;
  430.   end process p_rslt_mux;
  432. end rtl;