VxWorks

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C/C++

dbgArchLib.c：源码内容

{
return (getOneReg (taskId, R_REG_OFFSET(3)));
}
int r4 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(4))); }
int r5 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(5))); }
int r6 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(6))); }
int r7 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(7))); }
int r8 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(8))); }
int r9 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(9))); }
int r10 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(10))); }
int r11 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(11))); }
int r12 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(12))); }
int r13 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(13))); }
int r14 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(14))); }
int r15 (int taskId) { return (getOneReg (taskId, R_REG_OFFSET(15))); }
/*******************************************************************************
*
* g0 - return the contents of register `g0' (also `g1' - `g14') (i960)
*
* This command extracts the contents of register `g0' from the TCB of a
* specified task.
* If <taskId> is omitted or 0, the current default task is assumed.
*
* Routines are provided for all global registers (`g0' - `g14'):
* g0() - g14().
*
* RETURNS: The contents of the `g0' register (or the requested register).
*
* SEE ALSO:
* .pG "Target Shell"
*
* INTERNAL
* Although this routine is hereby marked NOMANUAL, it actually gets
* published from arch/doc/dbgArchLib.c.
* ...not any more -- i960 no longer supported.
*
* NOMANUAL
*/
int g0
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, G_REG_OFFSET(0)));
}
int g1 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(1))); }
int g2 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(2))); }
int g3 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(3))); }
int g4 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(4))); }
int g5 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(5))); }
int g6 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(6))); }
int g7 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(7))); }
int g8 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(8))); }
int g9 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(9))); }
int g10 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(10))); }
int g11 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(11))); }
int g12 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(12))); }
int g13 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(13))); }
int g14 (int taskId) { return (getOneReg (taskId, G_REG_OFFSET(14))); }
/*******************************************************************************
*
* fp - return the contents of register `fp' (i960)
*
* This command extracts the contents of register `fp', the frame pointer,
* from the TCB of a specified task.
* If <taskId> is omitted or 0, the current default task is assumed.
*
* RETURNS: The contents of the `fp' register.
*
* SEE ALSO:
* .pG "Target Shell"
*
* NOMANUAL
*/
int fp
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, FP_OFFSET));
}
#if CPU==I960KB
/*******************************************************************************
*
* fp0 - return the contents of register `fp0' (also `fp1' - `fp3') (i960KB, i960SB)
*
* This command extracts the contents of the floating-point register `fp0' from
* the TCB of a specified task.
* If <taskId> is omitted or 0, the current default task is assumed.
*
* Routines are provided for the floating-point registers `fp0' - `fp3':
* fp0() - fp3().
*
* RETURNS: The contents of the `fp0' register (or the requested register).
*
* SEE ALSO:
* .pG "Target Shell"
*
* NOMANUAL
*/
double fp0
(
volatile int taskId /* task ID, 0 means default task */
)
{
return (getOneFPReg (taskId, FPX_0));
}
double fp1 (volatile int taskId) { return (getOneFPReg (taskId, FPX_1)); }
double fp2 (volatile int taskId) { return (getOneFPReg (taskId, FPX_2)); }
double fp3 (volatile int taskId) { return (getOneFPReg (taskId, FPX_3)); }
#endif /* CPU==I960KB */
/*******************************************************************************
*
* pcw - return the contents of the `pcw' register (i960)
*
* This command extracts the contents of the `pcw' register from the TCB of a
* specified task.
* If <taskId> is omitted or 0, the current default task is assumed.
*
* RETURNS: The contents of the `pcw' register.
*
* SEE ALSO:
* .pG "Target Shell"
*
* NOMANUAL
*/
int pcw
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, PCW_OFFSET));
}
/*******************************************************************************
*
* tcw - return the contents of the `tcw' register (i960)
*
* This command extracts the contents of the `tcw' register from the TCB of a
* specified task.
* If <taskId> is omitted or 0, the current default task is assumed.
*
* RETURNS: The contents of the `tcw' register.
*
* SEE ALSO:
* .pG "Target Shell"
*
* NOMANUAL
*/
int tcw
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, TCW_OFFSET));
}
/*******************************************************************************
*
* acw - return the contents of the `acw' register (i960)
*
* This command extracts the contents of the `acw' register from the TCB of a
* specified task.
* If <taskId> is omitted or 0, the current default task is assumed.
*
* RETURNS: The contents of the `acw' register.
*
* SEE ALSO:
* .pG "Target Shell"
*
* NOMANUAL
*/
int acw
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, ACW_OFFSET));
}
/* dbgArchLib.c - MIPS architecture dependent debugger library */
#include "copyright_wrs.h"
/*
* This file has been developed or significantly modified by the
* MIPS Center of Excellence Dedicated Engineering Staff.
* This notice is as per the MIPS Center of Excellence Master Partner
* Agreement, do not remove this notice without checking first with
* WR/Platforms MIPS Center of Excellence engineering management.
*/
/*
modification history
--------------------
01r,16jul01,ros add CofE comment
01q,20dec00,pes Update for MIPS32/MIPS64 target combinations.
01p,22sep99,myz added CW4000_16 support.
01o,29jul99,alp added CW4000 and CW4010 support.
01n,18jan99,elg Authorize breakpoints on branch delay slot (SPR 24356).
01m,08jan98,dbt modified for new breakpoint scheme
01l,14oct96,kkk added R4650 support.
01k,10feb95,jdi doc tweaks.
01j,27jan95,rhp doc cleanup.
01i,19oct93,cd added R4000 support
01h,29sep93,caf undid fix of SPR #2359.
01g,07jul93,yao fixed to preserve parity error bit of status
register (SPR #2359). changed copyright notice.
01f,01oct92,ajm added dynamically bound handlers, general cleanup
01e,23aug92,jcf made filename consistant.
01d,22jul92,yao fixed bug when adding a temporary breakpoint at a branch
instruction in _dbgStepAdd().
01c,06jul92,yao removed dbgCacheClear(). made user uncallable globals
started with '_'.
01b,04jul92,jcf scalable/ANSI/cleanup effort.
01a,16jun92,yao written based on mips dbgLib.c ver01k.
*/
/*
DESCRIPTION
NOMANUAL
*/
#include "vxWorks.h"
#include "private/dbgLibP.h"
#include "private/taskLibP.h"
#include "taskArchLib.h"
#include "intLib.h"
#include "excLib.h"
#include "regs.h"
#include "iv.h"
#include "cacheLib.h"
#include "ioLib.h"
#include "dsmLib.h"
#include "vxLib.h"
#include "stdio.h"
#include "wdb/wdbDbgLib.h"
#include "dbgLib.h"
/* externals */
IMPORT int dsmInst (FAST long * binInst, int address, FUNCPTR prtAddress);
IMPORT FUNCPTR wdbDbgArchHandler[8];
IMPORT int dsmNbytes (ULONG);
IMPORT BOOL mips16Instructions(ULONG);
/* globals */
char * _archHelp_msg = /* help message */
#if (DBG_HARDWARE_BP)
"bh addr[,access[,task[,count[,quiet]]]] Set hardware breakpointn"
" access : 1 - write 2 - readn"
" 3 - read/write"
" For R4650 processors:n"
" access : 0 - instruction 1 - writen"
" 2 - read 3 - read/write"
#endif /* (DBG_HARDWARE_BP) */
"n";
/*******************************************************************************
*
* _dbgArchInit - architecture dependent initialization routine
*
* This routine initialize global function pointers that are specific for
* MIPS architecture.
*
* RETURNS:N/A
*
* NOMANUAL
*/
void _dbgArchInit (void)
{
_dbgDsmInstRtn = (FUNCPTR) dsmInst;
}
/*******************************************************************************
*
* _dbgInstSizeGet - set up breakpoint instruction
*
* RETURNS: size of the instruction at specified location.
*
* NOMANUAL
*/
int _dbgInstSizeGet
(
INSTR * brkInst /* pointer to hold breakpoint instruction */
)
{
return (2);
}
/*******************************************************************************
*
* _dbgRetAdrsGet - get return address for current routine
*
* RETURNS: return address for current routine.
*
* NOMANUAL
*/
INSTR * _dbgRetAdrsGet
(
REG_SET * pRegSet /* pointer to register set */
)
{
#if FALSE
INSTR * scanpc; /* instruction scan pc pointer */
/*
* scan instructions forward. If we find a "sw ra,x(sp)" or a "jr ra"
* then the return address in already in register "ra". If we find
* a "lw ra,x(sp)" then the return address is saved in offset "x"
* on the stack. If the instruction space is corrupted, could get
* a bus error eventually or could find a return address for a
* neighboring subprogram.
*/
for (scanpc = pRegSet->pc; TRUE; scanpc++)
{
/* match "sw ra,x(sp)" or "jr ra" means return address in ra */
if (INST_CMP(scanpc,(SW_INSTR|RA<<RT_POS|SP<<BASE_POS),
(GENERAL_OPCODE_MASK|RT_MASK|BASE_MASK)) ||
INST_CMP(scanpc,(SPECIAL|JR_INSTR|RA<<RS_POS),
(GENERAL_OPCODE_MASK|SPECIAL_MASK|RS_MASK)))
{
return ((INSTR *) pRegSet->raReg);
}
/* match "lw ra, x(sp)" means return address is on the stack */
if (INST_CMP(scanpc,(LW_INSTR|RA<<RT_POS|SP<<BASE_POS),
(GENERAL_OPCODE_MASK|RT_MASK|BASE_MASK)))
{
/* Note that the "C" compiler treats "short" as the lower
* 16 bits of the word and automatically performs the sign
* extend when the "short" is converted to a "long"
*/
return ((INSTR *)(*(INSTR **) (pRegSet->spReg + (short) *scanpc)));
}
}
return (NULL);
#endif /* FALSE */
return ((INSTR *) ERROR);
}
/*******************************************************************************
*
* _dbgFuncCallCheck - check next instruction
*
* This routine checks to see if the next instruction is a JAL or BAL.
* If it is, it returns TRUE, otherwise, returns FALSE.
*
* RETURNS: TRUE if next instruction is JAL or BAL, or FALSE otherwise.
*
* NOMANUAL
*/
BOOL _dbgFuncCallCheck
(
INSTR * addr /* pointer to instruction */
)
{
if (mips16Instructions((ULONG)addr))
{
/* mips16 jal, jalr instructions */
if ( (M16_INSTR_OPCODE(*(UINT16 *)addr) == M16_JALNX_INSTR)||
(((*(UINT16 *)addr) & 0xf81f) == 0xe800) ) /* j(al)r */
return (TRUE);
else
return(FALSE);
}
return (INST_CMP (addr, JAL_INSTR, GENERAL_OPCODE_MASK) ||
#ifdef _WRS_MIPS16
#define JALX_INSTR 0x74000000
INST_CMP (addr, JALX_INSTR, GENERAL_OPCODE_MASK) ||
#endif
INST_CMP (addr, (SPECIAL|JALR_INSTR),
(GENERAL_OPCODE_MASK | SPECIAL_MASK)) ||
INST_CMP (addr, (BCOND|BLTZAL_INSTR),
(GENERAL_OPCODE_MASK | BCOND_MASK)) ||
INST_CMP (addr, (BCOND | BGEZAL_INSTR),
(GENERAL_OPCODE_MASK | BCOND_MASK)) ||
INST_CMP (addr, (BCOND | BLTZALL_INSTR),
(GENERAL_OPCODE_MASK | BCOND_MASK)) ||
INST_CMP (addr, (BCOND | BGEZALL_INSTR),
(GENERAL_OPCODE_MASK | BCOND_MASK))
);
}
/*******************************************************************************
*
* _dbgTaskPCGet - get task's pc
*
* RETURNS:task's program counter
*
* NOMANUAL
*/
INSTR * _dbgTaskPCGet
(
int tid /* task's id */
)
{
REG_SET regSet;
(void) taskRegsGet (tid, &regSet);
#ifdef _WRS_MIPS16
/* mask off possible mips16 function indicator */
return((INSTR *)((int)(regSet.pc) & ~0x1));
#else
return ((INSTR *) regSet.pc);
#endif
}
/*******************************************************************************
*
* _dbgTaskPCSet - set task's pc
*
* RETURNS:N/A
*
* NOMANUAL
*/
void _dbgTaskPCSet
(
int tid, /* task id */
INSTR * pc, /* task's pc */
INSTR * npc /* task's npc */
)
{
REG_SET regSet; /* task's register set */
if (taskRegsGet (tid, &regSet) != OK)
return;
regSet.pc = pc;
taskRegsSet (tid, &regSet);
}
/*******************************************************************************
*
* dbgBpTypeBind - bind a breakpoint handler to a breakpoint type (MIPS R3000, R4000, R4650)
*
* Dynamically bind a breakpoint handler to breakpoints of type 0 - 7.
* By default only breakpoints of type zero are handled with the
* vxWorks breakpoint handler (see dbgLib). Other types may be used for
* Ada stack overflow or other such functions. The installed handler
* must take the same parameters as excExcHandle() (see excLib).
*
* RETURNS:
* OK, or
* ERROR if <bpType> is out of bounds.
*
* SEE ALSO
* dbgLib, excLib
*/
STATUS dbgBpTypeBind
(
int bpType, /* breakpoint type */
FUNCPTR routine /* function to bind */
)
{
if ((bpType > 7) || (bpType < 0))
{
return (ERROR);
}
else
{
wdbDbgArchHandler[bpType] = routine;
return (OK);
}
}
#if (DBG_HARDWARE_BP)
/******************************************************************************
*
* _dbgBrkDisplayHard - print hardware breakpoint
*
* This routine print hardware breakpoint.
*
* NOMANUAL
*/
void _dbgBrkDisplayHard
(
BRKPT * pBp /* breakpoint table entry */
)
{
int type;
if ((pBp->bp_flags & BRK_HARDWARE) == 0)
return;
type = pBp->bp_flags & BRK_HARDMASK;
printf (" (hard-");
switch (type)
{
case BRK_INST:
printf ("inst.)");
break;
case BRK_READ:
printf ("data read)");
break;
case BRK_WRITE:
printf ("data write)");
break;
case BRK_RW:
printf ("data r/w)");
break;
default:
printf ("unknown)");
break;
}
}
#endif /* DBG_HARDWARE_BP */
/* dbgArchLib.c - i80x86 architecture-specific debugging facilities */
#include "copyright_wrs.h"
/*
modification history
--------------------
01h,20nov01,hdn doc clean up for 5.5. revived edi() - eflags().
01g,08jan98,dbt modified for new breakpoint scheme
01f,10feb95,jdi doc tweak for 5.2.
01e,14dec93,hdn added _archHelp_msg.
01d,29nov93,hdn added eax() - eflags().
01c,27aug93,hdn added _dbgTaskPCSet().
01b,16jun93,hdn updated to 5.1.
- changed functions to ansi style
- changed VOID to void
- changed copyright notice
01a,08jul92,hdn written based on tron/dbgLib.c.
*/
/*
DESCRIPTION
This module provides the architecture dependent support functions for
dbgLib.
x86 including P5(Pentium), P6(PentiumPro, II, III), and P7(Pentium4) family
processors have four breakpoint registers and the following types of
hardware breakpoint:
.CS
BRK_INST /@ instruction hardware breakpoint @/
BRK_DATAW1 /@ data write 1 byte breakpoint @/
BRK_DATAW2 /@ data write 2 byte breakpoint @/
BRK_DATAW4 /@ data write 4 byte breakpoint @/
BRK_DATARW1 /@ data read-write 1 byte breakpoint @/
BRK_DATARW2 /@ data read-write 2 byte breakpoint @/
BRK_DATARW4 /@ data read-write 4 byte breakpoint @/
.CE
NOMANUAL
*/
/* LINTLIBRARY */
#include "vxWorks.h"
#include "taskLib.h"
#include "taskArchLib.h"
#include "intLib.h"
#include "regs.h"
#include "iv.h"
#include "cacheLib.h"
#include "ioLib.h"
#include "dsmLib.h"
#include "vxLib.h"
#include "usrLib.h"
#include "stdio.h"
#include "dbgLib.h"
/* defines */
#define DSM(addr,inst,mask) ((*(addr) & (mask)) == (inst))
/* externs */
IMPORT int dsmInst ();
/* globals */
char * _archHelp_msg =
#ifdef DBG_HARDWARE_BP
"bh addr[,access[,task[,count[,quiet]]]] Set hardware breakpointn"
" access : 0 - instruction 1 - write 1 byten"
" 3 - read/write 1 byte 5 - write 2 bytesn"
" 7 - read/write 2 bytes d - write 4 bytesn"
" f - read/write 4 bytes"
#endif /* DBG_HARDWARE_BP */
"n";
/* forward declarations */
LOCAL int getOneReg (int taskId, int regCode);
/*******************************************************************************
*
* _dbgArchInit - architecture dependent initialization routine
*
* This routine initialize global function pointers that are architecture
* specific.
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgArchInit (void)
{
_dbgDsmInstRtn = (FUNCPTR) dsmInst;
}
/*******************************************************************************
*
* _dbgRetAdrsGet - get a next instruction for cret ()
*
* if next instruction is a ENTER or RET, return address is on top of stack.
* otherwise it follows saved frame pointer.
*
*
* NOMANUAL
*/
INSTR * _dbgRetAdrsGet
(
REG_SET * pRegSet /* register set */
)
{
INSTR *returnAddress;
if (DSM(pRegSet->pc, PUSH_EBP, PUSH_EBP_MASK) &&
DSM(pRegSet->pc+1, MOV_ESP0, MOV_ESP0_MASK) &&
DSM(pRegSet->pc+2, MOV_ESP1, MOV_ESP1_MASK))
{
returnAddress = *(INSTR **)pRegSet->spReg;
}
else if (DSM(pRegSet->pc-1, PUSH_EBP, PUSH_EBP_MASK) &&
DSM(pRegSet->pc, MOV_ESP0, MOV_ESP0_MASK) &&
DSM(pRegSet->pc+1, MOV_ESP1, MOV_ESP1_MASK))
{
returnAddress = *((INSTR **)pRegSet->spReg + 1);
}
else if (DSM(pRegSet->pc, ENTER, ENTER_MASK))
{
returnAddress = *(INSTR **)pRegSet->spReg;
}
else if ((DSM(pRegSet->pc, RET, RET_MASK)) ||
(DSM(pRegSet->pc, RETADD, RETADD_MASK)))
{
returnAddress = *(INSTR **)pRegSet->spReg;
}
else
{
returnAddress = *((INSTR **)pRegSet->fpReg + 1);
}
return (returnAddress);
}
/*******************************************************************************
*
* _dbgFuncCallCheck - check next instruction
*
* This routine checks to see if the next instruction is a CALL
* If it is, it returns TRUE, otherwise, returns FALSE.
*
* RETURNS: TRUE if next instruction is a CALL, or FALSE otherwise.
*
* NOMANUAL
*/
BOOL _dbgFuncCallCheck
(
INSTR * addr /* pointer to instruction */
)
{
return ((DSM (addr, CALL_INDIR0, CALL_INDIR0_MASK) &&
DSM (addr + 1, CALL_INDIR1, CALL_INDIR1_MASK)) ||
(DSM (addr, CALL_DIR, CALL_DIR_MASK)));
}
/*******************************************************************************
*
* _dbgInstSizeGet - set up the breakpoint instruction
*
* RETURNS: size of the instruction at specified location.
*
* NOMANUAL
*/
int _dbgInstSizeGet
(
INSTR * pBrkInst /* pointer to hold breakpoint instruction */
)
{
return (dsmNbytes (pBrkInst));
}
/*******************************************************************************
*
* _dbgTaskPCGet - get task's program counter PC
*
* RETURNS:task's program counter
*
* NOMANUAL
*/
INSTR * _dbgTaskPCGet
(
int tid /* task's id */
)
{
REG_SET regSet;
(void) taskRegsGet (tid, &regSet);
return ((INSTR *) regSet.pc);
}
/*******************************************************************************
*
* _dbgTaskPCSet - set task's program counter PC
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgTaskPCSet
(
int task, /* task id */
INSTR * pc, /* new PC */
INSTR * npc /* not supported on I80X86 */
)
{
REG_SET regSet;
if (taskRegsGet (task, &regSet) != OK)
return;
regSet.pc = pc;
(void)taskRegsSet (task, &regSet);
}
#ifdef DBG_HARDWARE_BP
/*******************************************************************************
*
* _dbgBrkDisplayHard - display a hardware breakpoint
*
* This routine displays a hardware breakpoint.
*
* NOMANUAL
*/
void _dbgBrkDisplayHard
(
BRKPT * pBp /* breakpoint table entry */
)
{
int type;
if ((pBp->bp_flags & BRK_HARDWARE) == 0)
return;
type = pBp->bp_flags & BRK_HARDMASK;
printf (" (hard-");
switch (type)
{
case BRK_INST:
printf ("inst)");
break;
case BRK_DATAW1:
printf ("dataw1)");
break;
case BRK_DATAW2:
printf ("dataw2)");
break;
case BRK_DATAW4:
printf ("dataw4)");
break;
case BRK_DATARW1:
printf ("datarw1)");
break;
case BRK_DATARW2:
printf ("datarw2)");
break;
case BRK_DATARW4:
printf ("datarw4)");
break;
default:
printf ("unknown)");
break;
}
}
#endif /* DBG_HARDWARE_BP */
/*******************************************************************************
*
* getOneReg - return the contents of one register
*
* Given a task's ID, this routine returns the contents of the register
* specified by the register code. This routine is used by eax, edx, etc.
* The register codes are defined in dbgI86Lib.h.
*
* RETURNS: register contents, or ERROR.
*/
LOCAL int getOneReg (taskId, regCode)
int taskId; /* task's id, 0 means default task */
int regCode; /* code for specifying register */
{
REG_SET regSet; /* get task's regs into here */
taskId = taskIdFigure (taskId); /* translate super name to id */
if (taskId == ERROR) /* couldn't figure out super name */
return (ERROR);
taskId = taskIdDefault (taskId); /* set the default id */
if (taskRegsGet (taskId, &regSet) != OK)
return (ERROR);
switch (regCode)
{
case EDI: return (regSet.edi);
case ESI: return (regSet.esi);
case EBP: return (regSet.ebp);
case ESP: return (regSet.esp);
case EBX: return (regSet.ebx);
case EDX: return (regSet.edx);
case ECX: return (regSet.ecx);
case EAX: return (regSet.eax);
case EFLAGS: return (regSet.eflags);
}
return (ERROR); /* unknown regCode */
}
/*******************************************************************************
*
* edi - return the contents of register `edi' (also `esi' - `eax') (x86)
*
* This command extracts the contents of register `edi' from the TCB of a
* specified task. If <taskId> is omitted or zero, the last task
* referenced is assumed.
*
* Similar routines are provided for all general registers (`edi' - `eax'):
* edi() - eax().
*
* The stack pointer is accessed via eax().
*
* RETURNS: The contents of register `edi' (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*/
int edi
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, EDI));
}
int esi (taskId) int taskId; { return (getOneReg (taskId, ESI)); }
int ebp (taskId) int taskId; { return (getOneReg (taskId, EBP)); }
int esp (taskId) int taskId; { return (getOneReg (taskId, ESP)); }
int ebx (taskId) int taskId; { return (getOneReg (taskId, EBX)); }
int edx (taskId) int taskId; { return (getOneReg (taskId, EDX)); }
int ecx (taskId) int taskId; { return (getOneReg (taskId, ECX)); }
int eax (taskId) int taskId; { return (getOneReg (taskId, EAX)); }
/*******************************************************************************
*
* eflags - return the contents of the status register (x86)
*
* This command extracts the contents of the status register from the TCB of a
* specified task. If <taskId> is omitted or zero, the last task referenced is
* assumed.
*
* RETURNS: The contents of the status register.
*
* SEE ALSO:
* .pG "Debugging"
*/
int eflags
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, EFLAGS));
}
/* dbgArchLib.c - ARM-dependent debugger library */
#include "copyright_wrs.h"
/*
modification history
--------------------
01b,20feb97,jpd Tidied comments/documentation.
01a,18jul96,jpd written, based on 680x0 version 01h.
*/
/*
DESCRIPTION
This module provides the Advanced Risc Machines Ltd, ARM-specific support
functions for dbgLib. Note that no support is provided here (yet) for Thumb
state code or for the EmbeddedICE hardware debugging facilities.
NOMANUAL
*/
#include "vxWorks.h"
#include "private/dbgLibP.h"
#include "taskLib.h"
#include "regs.h"
#include "dsmLib.h"
#include "usrLib.h"
#include "arch/arm/arm.h"
#include "stdio.h"
#include "string.h"
/* externals */
/* architecture-independent breakpoint handling routine from dbgLib.c */
IMPORT STATUS dbgBreakpoint (BREAK_ESF *pInfo, int * Regs);
/* architecture-depdendent instruction decoding routines from dbgArmLib.c */
IMPORT INSTR * armGetNpc (INSTR, REG_SET *);
IMPORT BOOL armInstrChangesPc (INSTR *);
/* globals */
extern char * _archHelp_msg;
char * _archHelp_msg =
"r0-r14 [task] Display a register of a taskn"
"cpsr [task] Display cpsr of a taskn"
"psrShow value Display meaning of psr valuen";
/* locals */
/* forward declarations */
LOCAL void armBreakpoint(ESF *pEsf, REG_SET * pRegs);
/* pseudo-register num to pass to getOneReg() to get CPSR, local to this file */
#define ARM_REG_CPSR 16
/*******************************************************************************
*
* _dbgArchInit - architecture dependent initialization routine
*
* This routine initialises global function pointers that are architecture
* specific.
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgArchInit (void)
{
/* Install the ARM disassembler from dsmLib.c */
_dbgDsmInstRtn = dsmInst;
/*
* The ARM undefined instruction exception handler will check that the
* undefined instruction is the breakpoint instruction and pass control
* to an installed breakpoint handler via a function pointer. So, install
* our handler.
*/
_func_excBreakpoint = armBreakpoint;
}
/*******************************************************************************
*
* _dbgVecInit - insert new breakpoint and trace vectors
*
* NOTE
* Does nothing, since neither hardware breakpoints nor trace mode are
* supported on the ARM and the breakpoint handler has been installed in
* _dbgArchInit() above.
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgVecInit (void)
{
}
/*******************************************************************************
*
* _dbgInstSizeGet - get size of breakpoint instruction
*
* NOTE
* In contrast to the Architecture Porting Guidelines, this routine should not
* return the size in units of 16-bit words. It should return the size in units
* of sizeof(INSTR). The only place this routine is called from, is in so(), in
* dbgLib.c which uses this to add a breakpoint at:
* (INSTR *)(pc + _dbgInstSizeGet(pc).
*
* RETURNS: size of the instruction at specified location.
*
* NOMANUAL
*/
int _dbgInstSizeGet
(
INSTR * pBrkInst /* pointer to hold breakpoint instruction */
)
{
return dsmNbytes (pBrkInst) / sizeof(INSTR);
}
/*******************************************************************************
*
* _dbgRetAdrsGet - get return address for current routine
*
* This routine is used by the cret() routine to set a breakpoint at the return
* address of the current subroutine.
*
* NOTE
* In order to find the return address, a number of assumptions are made.
* In general, it will work for all C language routines and for assembly
* language routines that start with a standard entry sequence i.e.
* MOV ip,sp
* STMDB sp!,{..fp,ip,lr,pc}
* SUB fp,ip,#4
*
* This will need extending for Thumb.
*
* Most VxWorks assembly language routines establish a stack frame in this
* fashion for exactly this reason. However, routines written in other
* languages, strange entries into routines, or tasks with corrupted stacks
* can confuse this routine
*
* RETURNS: return address for current routine.
*
* NOMANUAL
*/
INSTR * _dbgRetAdrsGet
(
REG_SET * pRegSet /* pointer to register set */
)
{
int i; /* an index */
INSTR instr; /* next instruction */
FAST INSTR *pc = pRegSet->pc; /* pointer to instruction */
/*
* If the current routine doesn't have a stack frame, then we will have
* to guess that the return address is in the link register.
* We KNOW we don't have a stack frame in a few restricted but useful
* cases:
* 1) we are in the entry sequence of a routine which establishes the
* stack frame. We try to cope with this.
* 2) we are in a routine which doesn't create a stack frame. We cannot
* do much about this.
*/
instr = *pc;
/*
* look for the first instruction of the entry sequence which can be up
* to two instructions before the current pc
*/
for (i = 0; i >= -2 ; --i)
if (INSTR_IS(pc[i], MOV_IP_SP))
break;
/*
* If either the frame pointer is 0 or we are in the entry sequence of the
* routine, use lr.
*/
if ((pRegSet->fpReg == 0) ||
((i >= -2) &&
INSTR_IS(pc[i + 1], STMDB_SPP_FP_IP_LR_PC) &&
INSTR_IS(pc[i + 2], SUB_FP_IP_4)))
return (INSTR *)pRegSet->r[14];
else
return *(((INSTR **)(pRegSet->fpReg)) - 1);
}
/*******************************************************************************
*
* _dbgSStepClear - clear single step mode
*
* RETURNS: N/A
*
* NOMANUAL
*
* We believe that this routine can be null on the ARM which has no Single-Step
* processor mode.
*
*/
void _dbgSStepClear (void)
{
}
/*******************************************************************************
*
* _dbgSStepSet - set single step mode
*
* RETURNS: N/A
*
* NOMANUAL
*
* I believe that this routine can be null on the ARM which has no Single-Step
* processor mode. The SPARC architecture, sets a temporary breakpoint using
* _dbgStepAdd(), but I believe that this is redundant, as such a temporary
* breakpoint has already been set by dbgBreakpoint() in dbgLib.c which calls
* this routine.
*
*/
void _dbgSStepSet
(
BREAK_ESF * pInfo /* pointer to info saved on stack */
)
{
}
/******************************************************************************
*
* _dbgTaskSStepSet - set single step mode of task
*
* NOTE
* Does nothing since trace mode are not supported and temporary breakpoint
* is added in c() or s().
*
* RETURNS:N/A
*
* NOMANUAL
*/
void _dbgTaskSStepSet
(
int tid /* task's id */
)
{
}
/******************************************************************************
*
* _dbgTaskBPModeSet - set breakpoint mode of task
*
* NOMANUAL
*
* It has been suggested by WRS that it may be necessary to lock interrupts in
* this routine on some architectures to protect dbgTaskSwitch().
*
*/
void _dbgTaskBPModeSet
(
int tid /* task's id */
)
{
}
/******************************************************************************
*
* _dbgTaskBPModeClear - clear breakpoint mode of task
*
* NOMANUAL
*
* It has been suggested by WRS that it may be necessary to unlock interrupts in
* this routine on some architectures.
*
*/
void _dbgTaskBPModeClear
(
int tid
)
{
}
/*******************************************************************************
*
* _dbgFuncCallCheck - check if instruction calls a function
*
* This routine checks to see if the instruction calls a function.
* On the ARM, many classes of instruction could be used to do this. We check to
* see if the instruction is a BL, or if it changes the PC and the previous
* instruction is a MOV lr, pc instruction.
*
* This will need extending for Thumb.
*
* RETURNS: TRUE if next instruction calls a function, FALSE otherwise.
*
* NOMANUAL
*/
BOOL _dbgFuncCallCheck
(
INSTR * addr /* pointer to instruction */
)
{
return (INSTR_IS (*addr, BL) ||
(INSTR_IS (*(addr - 1), MOVXX_LR_PC) &&
armInstrChangesPc (addr)));
}
/*******************************************************************************
*
* _dbgRegsAdjust - set register set
*
* Comments from Am29k version:
*
* This routine restores the task's registers. It uses the register set stored
* in the task's memory stack to update the task's regSet.
*
* INTERNAL
* This routine is required since the breakpoint/trace ISR never returns in
* the breakpoint/trace stub (except when the breakpoint is ignored). So,
* excExit() cannot generally be used to re-fill the task's TCB with the
* register set saved in the ESF.
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgRegsAdjust
(
FAST int tid, /* id of task that hit breakpoint */
TRACE_ESF * pInfo, /* pointer to esf info saved on stack */
int * pRegs, /* pointer to buf containing saved regs */
BOOL stepBreakFlag /* TRUE if this was a trace exception */
/* FALSE if this was a SO or CRET breakpoint */
)
{
/*
* In the ARM implementation, may reload the task regSet using the pointer
* on this saved regSet.
*/
taskRegsSet (tid, (REG_SET *) pRegs);
}
/*******************************************************************************
*
* _dbgIntrInfoSave - save information when breakpoints are hit at interrupt
* level
*
* RETURNS: N/A
*
* NOMANUAL
*
* On advice from philm, this pair of routines can be null on the ARM as there
* is no trace or step-specific bit to save.
*
*/
void _dbgIntrInfoSave
(
BREAK_ESF * pInfo /* pointer to info saved on stack */
)
{
}
/******************************************************************************
*
* _dbgIntrInfoRestore - restore the info saved by dbgIntrInfoSave
*
* NOMANUAL
*/
void _dbgIntrInfoRestore
(
TRACE_ESF * pInfo /* pointer to execption frame */
)
{
}
/******************************************************************************
*
* _dbgInstPtrAlign - align pointer to appropriate boundary
*
* REUTRNS: align given instruction pointer to appropriate boundary
*
* NOMANUAL
*/
INSTR * _dbgInstPtrAlign
(
INSTR * addr /* instruction pointer */
)
{
addr = (INSTR *) ((int)addr & ~(0x03)); /* force address to a long
* word boundary.
*/
/* This will need extending for Thumb */
return addr;
}
/*******************************************************************************
*
* _dbgInfoPCGet - get pc
*
* RETURNS: value of pc saved on stack
*
* NOMANUAL
*/
INSTR * _dbgInfoPCGet
(
BREAK_ESF * pInfo /* pointer to info saved on stack */
)
{
return pInfo->pc;
}
/*******************************************************************************
*
* _dbgTaskPCSet - set task's pc
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgTaskPCSet
(
int tid, /* task id */
INSTR* pc, /* task's pc */
INSTR* npc /* next pc, not supported on ARM */
)
{
REG_SET regSet; /* task's register set */
if (taskRegsGet (tid, &regSet) != OK)
return;
regSet.pc = pc;
taskRegsSet (tid, &regSet);
}
/*******************************************************************************
*
* _dbgTaskPCGet - restore register set
*
* RETURNS: N/A
*
* NOMANUAL
*/
INSTR * _dbgTaskPCGet
(
int tid /* task id */
)
{
REG_SET regSet; /* task's register set */
taskRegsGet (tid, &regSet);
return regSet.pc;
}
/*******************************************************************************
*
* _dbgTraceDisable - disable trace mode
*
* NOMANUAL
*
* Can be a null routine on the ARM which has no trace mode.
*/
void _dbgTraceDisable (void)
{
}
/*******************************************************************************
*
* getOneReg - return the contents of one register
*
* Given a task's ID, this routine returns the contents of the register
* specified by the register code. This routine is used by `a1', `cpsr', etc.
*
* RETURNS: register contents, or ERROR.
*/
LOCAL int getOneReg (taskId, regCode)
int taskId; /* task's id, 0 means default task */
int regCode; /* code for specifying register */
{
REG_SET regSet; /* get task's regs into here */
taskId = taskIdFigure (taskId); /* translate super name to id */
if (taskId == ERROR) /* couldn't figure out super name */
return ERROR;
taskId = taskIdDefault (taskId); /* set the default id */
if (taskRegsGet (taskId, &regSet) != OK)
return ERROR;
switch (regCode)
{
case 0: return regSet.r[0]; /* general registers */
case 1: return regSet.r[1];
case 2: return regSet.r[2];
case 3: return regSet.r[3];
case 4: return regSet.r[4];
case 5: return regSet.r[5];
case 6: return regSet.r[6];
case 7: return regSet.r[7];
case 8: return regSet.r[8];
case 9: return regSet.r[9];
case 10: return regSet.r[10];
case 11: return regSet.r[11];
case 12: return regSet.r[12];
case 13: return regSet.r[13];
case 14: return regSet.r[14];
case 15: return (int) regSet.pc;
case ARM_REG_CPSR: return regSet.cpsr;
}
return ERROR; /* unknown regCode */
}
/*******************************************************************************
*
* r0 - return the contents of register `r0' (also `r1' - `r14') (ARM)
*
* This command extracts the contents of register `r0' from the TCB of a
* specified task. If <taskId> is omitted or zero, the last task referenced is
* assumed.
*
* Similar routines are provided for registers (`r1' - `r14'):
* r1() - r14().
*
* RETURNS: The contents of register `r0' (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*/
int r0
(
int taskId /* task ID, 0 means default task */
)
{
return getOneReg (taskId, 0);
}
int r1 (taskId) int taskId; { return getOneReg (taskId, 1); }
int r2 (taskId) int taskId; { return getOneReg (taskId, 2); }
int r3 (taskId) int taskId; { return getOneReg (taskId, 3); }
int r4 (taskId) int taskId; { return getOneReg (taskId, 4); }
int r5 (taskId) int taskId; { return getOneReg (taskId, 5); }
int r6 (taskId) int taskId; { return getOneReg (taskId, 6); }
int r7 (taskId) int taskId; { return getOneReg (taskId, 7); }
int r8 (taskId) int taskId; { return getOneReg (taskId, 8); }
int r9 (taskId) int taskId; { return getOneReg (taskId, 9); }
int r10 (taskId) int taskId; { return getOneReg (taskId, 10); }
int r11 (taskId) int taskId; { return getOneReg (taskId, 11); }
int r12 (taskId) int taskId; { return getOneReg (taskId, 12); }
int r13 (taskId) int taskId; { return getOneReg (taskId, 13); }
int r14 (taskId) int taskId; { return getOneReg (taskId, 14); }
/*******************************************************************************
*
* cpsr - return the contents of the current processor status register (ARM)
*
* This command extracts the contents of the status register from the TCB of a
* specified task. If <taskId> is omitted or zero, the last task referenced is
* assumed.
*
* RETURNS: The contents of the current processor status register.
*
* SEE ALSO:
* .pG "Debugging"
*/
int cpsr
(
int taskId /* task ID, 0 means default task */
)
{
return getOneReg (taskId, ARM_REG_CPSR);
}
/*******************************************************************************
*
* psrShow - display the meaning of a specified PSR value, symbolically (ARM)
*
* This routine displays the meaning of all fields in a specified PSR value,
* symbolically.
*
* RETURNS: OK, always.
*
*/
STATUS psrShow
(
UINT32 psrval /* psr value to show */
)
{
char str[16]; /* NZVCIFTSYSTEM32 */
strcpy(str, "nzcvift");
if (psrval & N_BIT)
str[0] = 'N';
if (psrval & Z_BIT)
str[1] = 'Z';
if (psrval & C_BIT)
str[2] = 'C';
if (psrval & V_BIT)
str[3] = 'V';
if (psrval & I_BIT)
str[4] = 'I';
if (psrval & F_BIT)
str[5] = 'F';
if (psrval & T_BIT)
str[6] = 'T';
switch (psrval & 0x1F)
{
case MODE_USER32:
strcat(str, "USER32");
break;
case MODE_FIQ32:
strcat(str, "FIQ32");
break;
case MODE_IRQ32:
strcat(str, "IRQ32");
break;
case MODE_SVC32:
strcat(str, "SVC32");
break;
case MODE_ABORT32:
strcat(str, "ABORT32");
break;
case MODE_UNDEF32:
strcat(str, "UNDEF32");
break;
case MODE_SYSTEM32:
strcat(str, "SYSTEM32");
break;
default:
strcat(str, "------");
break;
}
printf("%sn", str);
return OK;
}
/*******************************************************************************
*
* armBreakpoint - handle breakpoint
*
* This routine is installed via a function pointer into the exception handling
* code. It handles the breakpoint exception and chains on to the
* architecture-independent breakpoint handling code from dbgLib.c.
* Note that this and wdbArchLib cannot be used at the same time as they
* use the same mechanism.
*
* RETURNS: N/A
*
*/
LOCAL void armBreakpoint
(
ESF * pInfo, /* pointer to info saved on stack */
REG_SET *pRegs /* pointer to saved registers */
)
{
dbgBreakpoint ((BREAK_ESF *)pInfo, (int *)pRegs);
}
/*******************************************************************************
*
* _dbgStepAdd - add a breakpoint
*
* NOMANUAL
*
* This requirement for this routine appears to be to set a single-stepping
* breakpoint at the "next" instruction. Branches and so on must be predicted
* and we are allowed to put breakpoints at all possible "next" instructions.
* Deciding all possible next instructions on the ARM is sufficiently complex
* that in fact, we might as well work out exactly where the next instruction
* will be and put only one breakpoint there.
*
* RETURNS: status of adding breakpoints
*
*/
STATUS _dbgStepAdd
(
int task, /* task for which breakpoint is to be set */
int type, /* breakpoint type (either BRK_STEP or BRK_TEMP) */
BREAK_ESF * pEsf,
int * pRegs
)
{
REG_SET regSet; /* task's register set */
/* It appears to be the case that if the pointer to the ESF is null, then
* there will be no regs either, so get them */
if (pEsf == NULL)
(void) taskRegsGet (task, &regSet);
else
regSet.pc = _dbgInfoPCGet (pEsf);
/* find the next instruction to be executed and set a breakpoint there */
return dbgBrkAdd (armGetNpc (*(regSet.pc), &regSet), task, 0, type);
}
/* dbgArchLib.c - SH-dependent debugger library */
#include "copyright_wrs.h"
/*
modification history
--------------------
02t,24oct01,zl fixes for doc builds.
02s,15nov00,zl fixed _dbgInstSizeGet().
02r,06sep00,zl simplified CPU conditionals. Updated _archHelp_msg.
02q,03may00,rsh fix instruction mask error and add some better documentation
02p,21apr00,rsh implement cret
02o,19apr00,frf Modified dbgHelp and dbgBrkDisplayHard functions
02n,13apr00,frf Removed BRKENTRY and HWBP
02m,27mar00,frf Add SH support for T2: dbg API updated
02l,11mar99,hk changed TBH_ to TSH_BH_, simplified CPU conditionals.
merged _archHelp_msg for all SH CPUs.
02k,09mar99,hk changed to include CPU specific header for UBC register defs.
02j,09mar99,hk changed macro prefix BH_ to TBH_, to recover target shell tool.
02i,02mar99,hk retrieved _archHelp_msg for non-SENS branch.
02h,09oct98,hk code review: sorted CPU conditionals. fixed dBRCR for SH7750.
02g,07oct98,st changed BBRA,BBRB default setting for SH7750 from
BBR_BREAK_AT_INST_OR_DATA_ACCESS to BBR_BREAK_AT_INST_FETCH.
02f,16jul98,st added support for SH7750.
02g,15oct98,kab removed obsolete archHelp_msg.
02f,08may97,jmc added support for SH-DSP and SH3-DSP.
02e,23apr98,hk fixed _dbgStepAdd() against slot instr exception by s().
02d,25apr97,hk changed SH704X to SH7040.
02c,09feb97,hk renamed excBpHandle/excBpHwHandle to dbgBpStub/dbgHwBpStub.
02b,08aug96,hk code layout review. changed some #if (CPU==SH7xxx) controls.
02a,24jul96,ja added support for SH7700.
01z,21may96,hk workarounded for SH7700 build.
01y,10may96,hk added support for SH7700 (first phase).
01x,19dec95,hk added support for SH704X.
01w,08aug95,sa fixed _dbgStepAdd().
01v,28jun95,hk rewrote _dbgBranchDelay().
01u,27jun95,hk deleted _dbgBranchDelay().
01t,16mar95,hk added bypass to the delay slot checking in _dbgBranchDelay().
01s,28feb95,hk changed _dbgVecInit() to conform ivSh.h 01e.
01r,22feb95,hk added SH7000 support. moved printBbr(), printBrcr() to sysLib.
01q,21feb95,hk obsoleted bh(,4), more refinements, wrote some docs.
01p,20feb95,hk limited data break setup only for ch.B.
01o,17feb95,hk added bh(,4) to allow parameter customization.
01n,15feb95,hk debugging bh() problem.
01m,07feb95,hk copyright year 1995. more rewriting.
01l,11jan95,hk rewriting h/w breakpoint stuff.
01k,25dec94,hk fixed _archHelp_msg, clean-up. added _dbgBranchDelay().
fixed _dbgInstSizeGet(), so() now functional.
01j,23dec94,hk changing macro names.
01i,21dec94,hk working on UBC code. adding sequence diagram.
01h,18dec94,hk writing UBC support code.
01g,15dec94,hk adding hardware breakpoint function prototypes from i960 01t.
01f,15dec94,hk use SR_BIT_T.
01e,15dec94,hk more fixing. Now s() command is functional.
01d,06dec94,hk fixing.
01c,01dec94,hk included archPortKit notes. wrote most routines.
01b,26nov94,hk wrote _dbgArchInit body.
01a,09oct94,hk written based on sparc 01i.
*/
/*
DESCRIPTION
This module provides the SH specific support functions for dbgLib.
NOMANUAL
INTERNAL
This architecture-dependent debugger library contains some simple routines
that support the architecture-independent dbgLib.c. The complex portions of
the debugger have been abstracted.
*/
#include "vxWorks.h"
#include "private/dbgLibP.h"
#include "taskLib.h"
#include "fppLib.h"
#include "taskArchLib.h"
#include "intLib.h"
#include "regs.h"
#include "iv.h"
#include "cacheLib.h"
#include "ioLib.h"
#include "dsmLib.h"
#include "vxLib.h"
#include "stdio.h"
#include "usrLib.h"
IMPORT int dsmNbytes ();
IMPORT int dsmInst ();
IMPORT INST * dsmCheck ();
/* globals */
/* _archHelp_msg
*
* INTERNAL
* Architecture-specific help routines for the debugger are summarized in this
* string. The routine syntax is added to the end of the architecture-indepent
* routines displayed by dbgHelp(). The register display routines comprise the
* minimal set, and it should include any additional functionality that may be
* useful for debugging. [Arch port kit]
*/
char * _archHelp_msg =
"bh addr[,access[,task[,count[,quiet]]]] Set hardware breakpointn"
" access values:n"
" - Break on any access ( 00)n"
" - Break on instruction fetch ( 01)n"
" - Break on data access ( 10)n"
" - Bus cycle any ( 00 )n"
" - Bus cycle read ( 01 )n"
" - Bus cycle write ( 10 )n"
" - Operand size any ( 00 )n"
" - Operand size byte ( 01 )n"
" - Operand size word ( 10 )n"
" - Operand size long ( 11 )n"
" - CPU access ( 00 )n"
" - DMAC access ( 01 )n"
" - CPU or DMAC access ( 10 )n"
" - IBUS ( 00 )n"
" - XBUS ( 01 )n"
" - YBUS ( 10 )n"
" *Not all access combinations are supported by all SuperH CPUs.n"
" Use of an invalid combination is not always reported as an error.n"
"r0-r15,sr,gbr,vbr,mach,macl,pr,pc [task] Get a register of a taskn";
/* forward declarations */
/*******************************************************************************
*
* _dbgArchInit - architecture dependent initialization routine
*
* This routine initialize global function pointers that are architecture
* specific.
*
* NOMANUAL
*
* INTERNAL
* This function is identical for all architectures. It is used to link the
* architecture-specific routines in this file to the architecture-independent
* debugger support. The generic function call attaches the new processor's
* debugger library support. [Arch port kit]
*
* NOTE
* This routine is called from dbgInit() only.
*/
void _dbgArchInit (void)
{
_dbgDsmInstRtn = (FUNCPTR) dsmInst;
}
/*******************************************************************************
*
* _dbgInstSizeGet - set up breakpoint instruction
*
* RETURNS: size of the instruction at specified location.
*
* NOMANUAL
*
* INTERNAL
* This routine currently returns the number of 16-bit words needed to implement
* the breakpoint instruction at the specified address. It returns 16-bit words,
* instead of bytes, for compatibility with the original 68K debugger design;
* this does not make much sense for other architectures. In some future release
* the return value will be more architecture-independent, in other words, in
* bytes. [Arch port kit]
*
* NOTE
* This routine is called from so() only. Any SH instruction is 16-bit length,
* but we treat a delayed branch instruction as 32-bit. Otherwise we may insert
* the trapa instruction in a delay slot and gets an illegal slot exception.
*/
int _dbgInstSizeGet
(
INSTR * pBrkInst /* pointer to hold breakpoint instruction */
)
{
return (dsmNbytes (pBrkInst) / sizeof (INSTR));
}
/*******************************************************************************
*
* _dbgRetAdrsGet - get return address for current routine
*
* RETURNS: return address for current routine.
*
* NOMANUAL
*
* INTERNAL
* A pointer to a REG_SET is passed to this routine. It returns the adress of the
* instruction in the calling routine that will be executed when this function
* returns. Depending on the processor's function call mechanism and pipelining,
* the calling routine's program counter may have to be adjusted to create the
* return address. [Arch port kit]
*
* INTERNAL
* While executing a leaf procedure, the pr register always holds the correct
* return address. In case of a non-leaf procedure, this is not always true.
* After returning from a subroutine, pr keeps holding a return address of the
* subroutine. The correct return address of non-leaf procedure is on stack.
*
* ex. proc: <<< pr valid >>>
* :
* 4f22 sts.l pr, @-sp
* :
* mov.l &subr,r0
* jsr @r0
* nop
* :
* <<< pr invalid >>> ---> pr contains the return adrs of "subr".
* :
* 4f26 lds.l @sp+,pr ---> return adrs of "proc" is popped at here.
* :
* 000b rts
* nop
*
* NOTE
* This routine currently only detects #imm adjustment of the stack. Consequently,
* it will not find the correct frame pointer adjustment in functions which have
* greater than 127 (7 #imm bits) bytes of parameters and local data. A search
* through usrConfig.o indicates such a case only occurs once. For Beta, this
* should be sufficient.
*
*/
INSTR * _dbgRetAdrsGet
(
REG_SET * pRegSet
)
{
INSTR * scanpc; /* instruction scan pc pointer for forward scan */
UINT16 immed;
INT32 offset;
void * fp;
/*
* scan instructions forward. If we find a "sts.l pr,@-sp" or a "jsr @rm"
* then the return address in already in the link register. If we
* find a "lds.l @sp+,pr" then the return address is saved on the
* stack. We need to search back to find the offset.
* If we find "rts" without encountering the above instructions, it is
* a leaf function and the return address is in register "pr".
*/
for (scanpc = pRegSet->pc; TRUE; scanpc++)
{
/*
* if inst is "sts.l pr,@-sp" we are in the prolog.
* if inst is "rts" we are in a leaf proceedure. Note that
* this assumes you cannot break in the epilog, which would be
* true for c code, but not necessarily for assembly.
* Either way, the TCB's pr value is valid.
*/
if ((INST_CMP(scanpc, INST_PUSH_PR, 0xffff)) ||
(INST_CMP(scanpc, INST_RTS, 0xffff)))
{
return (pRegSet->pr);
}
/*
* we are somewhere in the function body of a non-leaf
* routine and the pr may have been modified by a previous
* function call. The correct pr is on the stack and must
* be retrieved. Break from here and enter the search backwards
* loop.
*/
else if (INST_CMP(scanpc, INST_POP_PR, 0xffff))
{
break;
}
}
/* if we arrive here, we are inside the function body and the current
* tcb's pr value may be invalid (i.e. we may have called a subroutine
* within the current function body which would have modified pr).
* Consequently, we'll need to search backwards to find 1) the current
* frame pointer (stored in r14) and 2) the offset from the current
* frame pointer back to the pr location on the stack. The sh compiler
* sets the frame pointer to the stack location of the last parameter
* or local allocation so that we have a variable offset back to the
* pr location.
*/
scanpc = pRegSet->pc;
/* search back until we have the SET_FP instruction (mov.l sp,r14) */
while (!(INST_CMP(scanpc, INST_SET_FP, 0xffff)))
{
scanpc--;
}
/* search back until the PUSH_PR instruction looking for a frame
* adjustment instruction that modifies r15 before storing to r14.
* (add #imm,sp). The #imm argument
*/
while (!(INST_CMP(scanpc, INST_PUSH_PR, 0xffff)))
{
if (INST_CMP(scanpc, INST_ADD_IMM_SP, MASK_ADD_IMM_SP))
{
immed = *(scanpc) & 0x00ff;
/* "add #imm,sp" instruction sign extends #imm. Since this instruction
* descremented the sp, #imm will be a negative value. sign extend
* it to get it's proper negative value. And then reverse the sign.
*/
offset = (0xffffff00 | (long) immed); /* negative offset */
offset = 0 - (offset);
/* add offset to frame pointer */
(ULONG *) fp = pRegSet->fpReg;
(char *) fp += offset;
/* retrieve and return pr */
return ((INSTR *) *((ULONG *) fp));
}
scanpc--;
}
/* if we get here, then the offset is zero, so just return the value
* held in r14 (the frame pointer).
*/
return ((INSTR *) *((ULONG *) pRegSet->fpReg));
#if FALSE
return ((INSTR *) ERROR);
#endif
}
/*******************************************************************************
*
* _dbgFuncCallCheck - check next instruction
*
* This routine checks to see if the next instruction is a JSR or BSR.
* If it is, it returns TRUE, otherwise, returns FALSE.
*
* RETURNS: TRUE if next instruction is JSR or BSR, or FALSE otherwise.
*
* NOMANUAL
*
* INTERNAL
* This routine checks the instruction pointed to by the input argument to
* determine if it is an instruction that is used to implement a function call.
* If so, the function returns TRUE, otherwise the return value is FALSE.
* Note the use of the INST_CMP macro defined in dbgLib.h. [Arch port kit]
*
* NOTE
* This routine is called from so() only.
*/
BOOL _dbgFuncCallCheck
(
INSTR * addr
)
{
/* SH JSR and BSR instructions:
*
* JSR @Rn 0100nnnn00001011 itAtOneReg - 2/3
* BSRF Rn 0000nnnn00000011 itBraDispRn - 2/2
* BSR disp 1011dddddddddddd itBraDisp12 - 2/2
*/
return (INST_CMP (addr, 0x400b, 0xf0ff) /* JSR */
|| INST_CMP (addr, 0x0003, 0xf0ff) /* BSRF */
|| INST_CMP (addr, 0xb000, 0xf000) /* BSR */ );
}
/*******************************************************************************
*
* _dbgInfoPCGet - get pc from stack
*
* RETURNS: value of pc saved on stack
*
* NOMANUAL
*
* INTERNAL
* This routine returns a pointer to the instruction addressed by the program
* counter. The input argument is a pointer to the breakpoint stack frame. The
* return value is the program counter element of that structure, whose type
* should be an INSTR*. [Arch port kit]
*
* NOTE
* This routine is called from dbgBreakpoint() only.
*/
INSTR * _dbgInfoPCGet
(
BREAK_ESF * pInfo
)
{
return (pInfo->pc);
}
/*******************************************************************************
*
* _dbgTaskPCSet - set task's pc
*
* NOMANUAL
*
* INTERNAL
* The task identification and the program counter(s) are passed to this
* function which will set new program counter(s) for the specified task.
* A local copy of REG_SET is filled by the call to taskRegsGet(), the program
* counter(s) set, and then copied back to the task's TCB by taskRegsSet().
* This routine is similar for all architectures. [Arch port kit]
*
* NOTE
* This routine is called from c() and s().
*/
void _dbgTaskPCSet
(
int tid,
INSTR * pc, /* task's pc */
INSTR * npc /* task's npc (not supported by SH) */
)
{
REG_SET regSet;
if (taskRegsGet (tid, &regSet) != OK)
return;
regSet.pc = pc;
taskRegsSet (tid, &regSet);
}
/*******************************************************************************
*
* _dbgTaskPCGet - get task's pc
*
* RETURNS: specified task's program counter
*
* NOMANUAL
*
* INTERNAL
* This routine returns a pointer to the instruction addressed by the program
* counter. The input argument is the task identifier used with taskRegsGet().
* The return value is the program counter element of that structure, whose
* type should be an INSTR*. [Arch port kit]
*
* NOTE
* This routine is called from c(), so(), dbgTlSnglStep(), and dbgTaskSwitch().
*/
INSTR * _dbgTaskPCGet
(
int tid
)
{
REG_SET regSet;
(void) taskRegsGet (tid, &regSet);
return ((INSTR *) regSet.pc);
}
/*******************************************************************************
*
* getOneReg - return the contents of one register
*
* Given a task's ID, this routine returns the contents of the register
* specified by the register code. This routine is used by r0, sr, etc.
* The register codes are defined in regsSh.h.
*
* NOMANUAL
*
* RETURNS: register contents, or ERROR.
*
* INTERNAL
* This routine gets the contents of a specific register in the REG_SET based on
* the task identifier and the register index. A call is made to taskIdFigure(),
* and the return value checked for an ERROR. taskIdDefault() and taskRegsGer()
* are called to fill a local copy of REG_SET. The index is used to return the
* contents of the register. [Arch port kit]
*
*/
LOCAL int getOneReg
(
int taskId, /* task ID, 0 means default task */
int regCode /* code for specifying register */
)
{
REG_SET regSet; /* get task's regs into here */
taskId = taskIdFigure (taskId); /* translate super name to ID */
if (taskId == ERROR) /* couldn't figure out super name */
return (ERROR);
taskId = taskIdDefault (taskId); /* set the default ID */
if (taskRegsGet (taskId, &regSet) != OK)
return (ERROR);
return (*(int *)((int)&regSet + regCode));
}
/*******************************************************************************
*
* r0 - return the contents of general register `r0' (also `r1'-`r15') (SH)
*
* This command extracts the contents of register `r0' from the TCB of a specified
* task. If <taskId> is omitted or zero, the last task referenced is assumed.
*
* Similar routines are provided for all general registers (`r1' - `r15'):
* r1() - r15().
*
* RETURNS: The contents of register r0 (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*
* INTERNAL
* Each control and general-purpose register should have a routine to display
* its contents in the REG_SET structure in the TCB. The task identifier and
* a register index is passed to the hidden (local) function getOneReg() which
* returns the contents. [Arch port kit]
*/
int r0
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_R0 ));
}
int r1 (int taskId) { return (getOneReg (taskId, REG_SET_R1 )); }
int r2 (int taskId) { return (getOneReg (taskId, REG_SET_R2 )); }
int r3 (int taskId) { return (getOneReg (taskId, REG_SET_R3 )); }
int r4 (int taskId) { return (getOneReg (taskId, REG_SET_R4 )); }
int r5 (int taskId) { return (getOneReg (taskId, REG_SET_R5 )); }
int r6 (int taskId) { return (getOneReg (taskId, REG_SET_R6 )); }
int r7 (int taskId) { return (getOneReg (taskId, REG_SET_R7 )); }
int r8 (int taskId) { return (getOneReg (taskId, REG_SET_R8 )); }
int r9 (int taskId) { return (getOneReg (taskId, REG_SET_R9 )); }
int r10 (int taskId) { return (getOneReg (taskId, REG_SET_R10 )); }
int r11 (int taskId) { return (getOneReg (taskId, REG_SET_R11 )); }
int r12 (int taskId) { return (getOneReg (taskId, REG_SET_R12 )); }
int r13 (int taskId) { return (getOneReg (taskId, REG_SET_R13 )); }
int r14 (int taskId) { return (getOneReg (taskId, REG_SET_R14 )); }
int r15 (int taskId) { return (getOneReg (taskId, REG_SET_R15 )); }
/*******************************************************************************
*
* sr - return the contents of control register `sr' (also `gbr', `vbr') (SH)
*
* This command extracts the contents of register sr from the TCB of a specified
* task. If <taskId> is omitted or zero, the last task referenced is assumed.
*
* Similar routines are provided for all control registers (`gbr', `vbr'):
* gbr(), vbr().
*
* RETURNS: The contents of register sr (or the requested control register).
*
* SEE ALSO:
* .pG "Debugging"
*
* INTERNAL
* Each control and general-purpose register should have a routine to display
* its contents in the REG_SET structure in the TCB. The task identifier and
* a register index is passed to the hidden (local) function getOneReg() which
* returns the contents. [Arch port kit]
*/
int sr
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_SR ));
}
int gbr (int taskId) { return (getOneReg (taskId, REG_SET_GBR )); }
int vbr (int taskId) { return (getOneReg (taskId, REG_SET_VBR )); }
/*******************************************************************************
*
* mach - return the contents of system register `mach' (also `macl', `pr') (SH)
*
* This command extracts the contents of register mach from the TCB of
* a specified task. If <taskId> is omitted or zero, the last task referenced
* is assumed.
*
* Similar routines are provided for other system registers (`macl', `pr'):
* macl(), pr(). Note that pc() is provided by usrLib.c.
*
* RETURNS: The contents of register mach (or the requested system register).
*
* SEE ALSO:
* .pG "Debugging"
*
* INTERNAL
* Each control and general-purpose register should have a routine to display
* its contents in the REG_SET structure in the TCB. The task identifier and
* a register index is passed to the hidden (local) function getOneReg() which
* returns the contents. [Arch port kit]
*/
int mach
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_MACH));
}
int macl(int taskId) { return (getOneReg (taskId, REG_SET_MACL)); }
int pr (int taskId) { return (getOneReg (taskId, REG_SET_PR )); }
#if FALSE
int pc (int taskId) { return (getOneReg (taskId, REG_SET_PC )); }
#endif /* FALSE, usrLib provides this. */
#if DBG_HARDWARE_BP /* TO THE END OF THIS FILE */
/******************************************************************************
*
* _dbgBrkDisplayHard - display a hardware breakpoint
*
* NOMANUAL
*
* NOTE
* This routine is called from dbgBrkDisplay() only.
*/
void _dbgBrkDisplayHard
(
BRKPT * pBp /* breakpoint table entry */
)
{
int type;
if ((pBp->bp_flags & BRK_HARDWARE) == 0)
return;
type = pBp->bp_flags & BRK_HARDMASK;
printf ("n UBC");
switch (type & BH_BREAK_MASK)
{
/* HW breakpoint on bus... */
case BH_BREAK_INSN: printf(" INST"); break; /* istruction access */
case BH_BREAK_DATA: printf(" DATA"); break; /* data access */
default: printf(" I/D"); break; /* any */
}
switch (type & BH_CYCLE_MASK)
{
/* HW breakpoint on bus cycle... */
case BH_CYCLE_READ: printf(" READ"); break; /* read */
case BH_CYCLE_WRITE: printf(" WRITE"); break; /* write */
default: printf(" R/W"); break; /* any */
}
switch (type & BH_SIZE_MASK)
{
/* HW breakpoint on operand size */
case BH_8: printf(" BYTE"); break; /* 8 bit */
case BH_16: printf(" WORD"); break; /* 16 bit */
case BH_32: printf(" LONG"); break; /* 32 bit */
}
switch (type & BH_CPU_MASK)
{
/* HW breakpoint on bus cycle... */
case BH_CPU: printf(" CPU"); break; /* CPU */
case BH_DMAC: printf(" DMA"); break; /* DMA ctrl */
case BH_DMAC_CPU: printf(" DMA/CPU");break; /* DMA/CPU */
}
switch (type & BH_BUS_MASK)
{
/* HW breakpoint on bus cycle... */
case BH_XBUS: printf(" XBUS"); break; /* XBUS, DSP only */
case BH_YBUS: printf(" YBUS"); break; /* YBUS, DSP only */
}
}
#endif /* DBG_HARDWARE_BP */
/* dbgArchLib.c - solaris simulator debugger library */
#include "copyright_wrs.h"
/*
modification history
--------------------
02e,13nov01,hbh Fixed return address in _dbgRetAdrsGet and updated comments.
02d,30apr98,dbt removed unused _dbgInfoPCGet() routine.
02c,09jan98,dbt modified for new breakpoint scheme.
02b,26jan96,ism cleaned up
02a,07jun95,ism converted to simsolaris
01f,26jan94,gae minor improvement to exception display.
01e,17dec93,gae fixed "Segmentaion" spelling.
01d,23aug93,rrr fixup of trcStack and excShow routines.
01c,14jul93,gae trcStack prints not supported; excShowInit() installs routines.
01b,09jul93,rrr added trap handling.
01a,19jun93,rrr written.
*/
/*
DESCRIPTION
This module provides the simsolaris specific support
functions for dbgLib.c.
*/
#include "vxWorks.h"
#include "private/dbgLibP.h"
#include "taskLib.h"
#include "taskArchLib.h"
#include "intLib.h"
#include "ioLib.h"
#include "iv.h"
#include "dsmLib.h"
#include "regs.h"
#include "stdio.h"
#include "usrLib.h"
/* externs */
IMPORT int dsmNbytes ();
IMPORT int dsmInst ();
/* defines */
#undef pc
/* globals */
char * _archHelp_msg =
"i0-i7,l0-l7,o0-o7,g1-g7,n"
"pc,npc,psr,wim,y [task] Display a register of a taskn"
"psrShow value Display meaning of psr valuen";
/*******************************************************************************
*
* _dbgArchInit - architecture dependent initialization routine
*
* This routine initialize global function pointers that are architecture
* specific.
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgArchInit (void)
{
_dbgDsmInstRtn = (FUNCPTR) dsmInst;
}
/*******************************************************************************
*
* _dbgInstSizeGet - set up breakpoint instruction
*
* RETURNS: size of the instruction at specified location.
*
* NOMANUAL
*/
int _dbgInstSizeGet
(
INSTR * pBrkInst /* pointer to hold breakpoint instruction */
)
{
return ((2 * sizeof (INSTR)) / sizeof (INSTR));
}
/*******************************************************************************
*
* _dbgRetAdrsGet - get return address for current routine
*
* RETURNS: return address for current routine.
*
* NOMANUAL
*/
INSTR * _dbgRetAdrsGet
(
REG_SET * pRegSet /* pointer to register set */
)
{
int *sp = (int *) pRegSet->spReg;
/*
* check if the following instruction is like :
* 9de3bxxx save %sp, 0xffffffxx, %sp
* if yes, then return address is in o7 register not in i7
*/
if (INST_CMP (((INSTR *) (pRegSet->reg_pc)),INST_SAV,INST_SAV_MASK))
return ((INSTR *) ((pRegSet->reg_out[7]) + 8));
if (I7_CONTENTS (sp) != 0)
{
if (INST_CMP (I7_CONTENTS (sp), INST_CALL, INST_CALL_MASK) ||
INST_CMP (I7_CONTENTS (sp), JMPL_o7, JMPL_o7_MASK))
{
return ((INSTR *) (I7_CONTENTS(sp) + 2));
}
}
return (NULL);
}
/*******************************************************************************
*
* _dbgFuncCallCheck - check next instruction
*
* This routine checks to see if the next instruction is a JSR or BSR.
* If it is, it returns TRUE, otherwise, returns FALSE.
*
* RETURNS: TRUE if next instruction is JSR or BSR, or FALSE otherwise.
*
* NOMANUAL
*/
BOOL _dbgFuncCallCheck
(
INSTR * addr /* pointer to instruction */
)
{
return (INST_CMP (addr, INST_CALL, INST_CALL_MASK) ||
INST_CMP (addr, JMPL_o7, JMPL_o7_MASK));
}
/*******************************************************************************
*
* _dbgTaskPCSet - set task's pc
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgTaskPCSet
(
int tid, /* task id */
INSTR * pc, /* task's pc */
INSTR * npc /* task's npc */
)
{
REG_SET regSet; /* task's register set */
taskRegsGet (tid, &regSet);
regSet.reg_pc = pc;
if (npc == NULL)
regSet.reg_npc = pc + 1;
else
regSet.reg_npc = npc;
taskRegsSet (tid, &regSet);
}
/*******************************************************************************
*
* _dbgTaskPCGet - get task's pc
*
* RETURNS: N/A
*
* NOMANUAL
*/
INSTR * _dbgTaskPCGet
(
int tid /* task's id */
)
{
REG_SET regSet;
taskRegsGet (tid, &regSet);
return ((INSTR *) regSet.reg_pc);
}
/*******************************************************************************
*
* getOneReg - return the contents of one register
*
* Given a task's ID, this routine returns the contents of the register
* specified by the register code. This routine is used by g0, i0, psr, etc.
* The register codes are defined in regsSimsolaris.h.
*
* RETURNS: register contents, or ERROR.
*/
LOCAL int getOneReg
(
int taskId, /* task ID, 0 means default task */
int regCode /* code for specifying register */
)
{
REG_SET regSet; /* get task's regs into here */
taskId = taskIdFigure (taskId); /* translate super name to ID */
if (taskId == ERROR) /* couldn't figure out super name */
return (ERROR);
taskId = taskIdDefault (taskId); /* set the default ID */
if (taskRegsGet (taskId, &regSet) != OK)
return (ERROR);
return (*(int *)((int)&regSet + regCode));
}
/*******************************************************************************
*
* g0 - return the contents of register g0 (also g1-g7) (SimSolaris)
*
* This command extracts the contents of global register g0 from the TCB of a
* specified task. If <taskId> is omitted or 0, the current default task is
* assumed.
*
* Similar routines are provided for all global registers (g0 - g7):
* g0() - g7().
*
* RETURNS: The contents of register g0 (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*
* INTERNAL
* Although this routine is hereby marked NOMANUAL, it actually gets
* published, but from arch/doc/dbgArchLib.c.
*/
int g0
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_GLOBAL(0)));
}
int g1 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(1))); }
int g2 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(2))); }
int g3 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(3))); }
int g4 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(4))); }
int g5 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(5))); }
int g6 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(6))); }
int g7 (int taskId) { return (getOneReg (taskId, REG_SET_GLOBAL(7))); }
/*******************************************************************************
*
* o0 - return the contents of register o0 (also o1-o7) (SimSolaris)
*
* This command extracts the contents of out register o0 from the TCB of a
* specified task. If <taskId> is omitted or 0, the current default task is
* assumed.
*
* Similar routines are provided for all out registers (o0 - o7):
* o0() - o7().
*
* The stack pointer is accessed via o6.
*
* RETURNS: The contents of register o0 (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*/
int o0
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_OUT(0)));
}
int o1 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(1))); }
int o2 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(2))); }
int o3 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(3))); }
int o4 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(4))); }
int o5 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(5))); }
int o6 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(6))); }
int o7 (int taskId) { return (getOneReg (taskId, REG_SET_OUT(7))); }
/*******************************************************************************
*
* l0 - return the contents of register l0 (also l1-l7) (SimSolaris)
*
* This command extracts the contents of local register l0 from the TCB of a
* specified task. If <taskId> is omitted or 0, the current default task is
* assumed.
*
* Similar routines are provided for all local registers (l0 - l7):
* l0() - l7().
*
* RETURNS: The contents of register l0 (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*/
int l0
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_LOCAL(0)));
}
int l1 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(1))); }
int l2 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(2))); }
int l3 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(3))); }
int l4 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(4))); }
int l5 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(5))); }
int l6 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(6))); }
int l7 (int taskId) { return (getOneReg (taskId, REG_SET_LOCAL(7))); }
/*******************************************************************************
*
* i0 - return the contents of register i0 (also i1-i7) (SimSolaris)
*
* This command extracts the contents of in register i0 from the TCB of a
* specified task. If <taskId> is omitted or 0, the current default task is
* assumed.
*
* Similar routines are provided for all in registers (i0 - i7):
* i0() - i7().
*
* The frame pointer is accessed via i6.
*
* RETURNS: The contents of register i0 (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*/
int i0
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_IN(0)));
}
int i1 (int taskId) { return (getOneReg (taskId, REG_SET_IN(1))); }
int i2 (int taskId) { return (getOneReg (taskId, REG_SET_IN(2))); }
int i3 (int taskId) { return (getOneReg (taskId, REG_SET_IN(3))); }
int i4 (int taskId) { return (getOneReg (taskId, REG_SET_IN(4))); }
int i5 (int taskId) { return (getOneReg (taskId, REG_SET_IN(5))); }
int i6 (int taskId) { return (getOneReg (taskId, REG_SET_IN(6))); }
int i7 (int taskId) { return (getOneReg (taskId, REG_SET_IN(7))); }
/*******************************************************************************
*
* npc - return the contents of the next program counter (SimSolaris)
*
* This command extracts the contents of the next program counter from the TCB
* of a specified task. If <taskId> is omitted or 0, the current default
* task is assumed.
*
* RETURNS: The contents of the next program counter.
*
* SEE ALSO: ti()
*/
int npc
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_NPC));
}
/*******************************************************************************
*
* psr - return the contents of the processor status register (SimSolaris)
*
* This command extracts the contents of the processor status register from
* the TCB of a specified task. If <taskId> is omitted or 0, the default
* task is assumed.
*
* RETURNS: The contents of the processor status register.
*
* SEE ALSO:
* .pG "Debugging"
*/
int psr
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_PSR));
}
/*******************************************************************************
*
* wim - return the contents of the window invalid mask register (SimSolaris)
*
* This command extracts the contents of the window invalid mask register from
* the TCB of a specified task. If <taskId> is omitted or 0, the default
* task is assumed.
*
* RETURNS: The contents of the window invalid mask register.
*
* SEE ALSO:
* .pG "Debugging"
*/
int wim
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_WIM));
}
/*******************************************************************************
*
* y - return the contents of the y register (SimSolaris)
*
* This command extracts the contents of the y register from the TCB of a
* specified task. If <taskId> is omitted or 0, the default task is assumed.
*
* RETURNS: The contents of the y register.
*
* SEE ALSO:
* .pG "Debugging"
*/
int y
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, REG_SET_Y));
}
/* dbgArchLib.c - windows NT debugger library */
#include "copyright_wrs.h"
/*
modification history
--------------------
01c,23jul98,dbt code cleanup
01b,19feb98,jmb fix typo in symbol name and switch to dbgLibNew header.
01a,13jan98,cym written.
*/
/*
DESCRIPTION
This module provides the windows specific support
functions for dbgLib.c.
*/
#include "vxWorks.h"
#include "dbgLib.h"
#include "taskLib.h"
#include "fppLib.h"
#include "taskArchLib.h"
#include "intLib.h"
#include "ioLib.h"
#include "iv.h"
#include "dsmLib.h"
#include "regs.h"
#include "vxLib.h"
#include "logLib.h"
#include "fioLib.h"
#include "stdio.h"
#include "usrLib.h"
/* interrupt driver routines from dsmLib.c */
IMPORT int dsmNbytes ();
IMPORT int dsmInst ();
/* globals */
char * _archHelp_msg =
"Sorry, no help yetn";
LOCAL oldIntLevel; /* old interrupt level */
/*******************************************************************************
*
* _dbgArchInit - architecture dependent initialization routine
*
* This routine initialize global function pointers that are architecture
* specific.
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgArchInit (void)
{
_dbgDsmInstRtn = (FUNCPTR) dsmInst;
}
/*******************************************************************************
*
* _dbgInstSizeGet - set up breakpoint instruction
*
* RETURNS: size of the instruction at specified location.
*
* NOMANUAL
*/
int _dbgInstSizeGet
(
INSTR * pBrkInst /* pointer to hold breakpoint instruction */
)
{
return (dsmNbytes(pBrkInst));
}
/*******************************************************************************
*
* _dbgRetAdrsGet - get return address for current routine
*
* RETURNS: return address for current routine.
*
* NOMANUAL
*/
INSTR * _dbgRetAdrsGet
(
REG_SET * pRegSet /* pointer to register set */
)
{
INSTR *returnAddress;
#if FALSE
if (DSM(pRegSet->pc, PUSH_EBP, PUSH_EBP_MASK) &&
DSM(pRegSet->pc+1, MOV_ESP0, MOV_ESP0_MASK) &&
DSM(pRegSet->pc+2, MOV_ESP1, MOV_ESP1_MASK))
{
returnAddress = *(INSTR **)pRegSet->spReg;
}
else if (DSM(pRegSet->pc-1, PUSH_EBP, PUSH_EBP_MASK) &&
DSM(pRegSet->pc, MOV_ESP0, MOV_ESP0_MASK) &&
DSM(pRegSet->pc+1, MOV_ESP1, MOV_ESP1_MASK))
{
returnAddress = *((INSTR **)pRegSet->spReg + 1);
}
else if (DSM(pRegSet->pc, ENTER, ENTER_MASK))
{
returnAddress = *(INSTR **)pRegSet->spReg;
}
else if ((DSM(pRegSet->pc, RET, RET_MASK)) ||
(DSM(pRegSet->pc, RETADD, RETADD_MASK)))
{
returnAddress = *(INSTR **)pRegSet->spReg;
}
else
{
returnAddress = *((INSTR **)pRegSet->fpReg + 1);
}
#endif
return (returnAddress);
}
/*******************************************************************************
*
* _dbgFuncCallCheck - check next instruction
*
* This routine checks to see if the next instruction is a JSR or BSR.
* If it is, it returns TRUE, otherwise, returns FALSE.
*
* RETURNS: TRUE if next instruction is JSR or BSR, or FALSE otherwise.
*
* NOMANUAL
*/
BOOL _dbgFuncCallCheck
(
INSTR * addr /* pointer to instruction */
)
{
#if FALSE
return (INST_CMP (addr, INST_CALL, INST_CALL_MASK) ||
INST_CMP (addr, JMPL_o7, JMPL_o7_MASK));
#else
return 0; /* XXX Change me!!! */
#endif
}
/*******************************************************************************
*
* _dbgTaskPCSet - set task's pc
*
* RETURNS: N/A
*
* NOMANUAL
*/
void _dbgTaskPCSet
(
int task, /* task id */
INSTR *pc, /* new PC */
INSTR *npc /* not supported on I80X86 */
)
{
REG_SET regSet;
if (taskRegsGet (task, &regSet) != OK)
return;
regSet.pc = pc;
(void)taskRegsSet (task, &regSet);
}
/*******************************************************************************
*
* _dbgTaskPCGet - get task's pc
*
* RETURNS: N/A
*
* NOMANUAL
*/
INSTR * _dbgTaskPCGet
(
int tid /* task's id */
)
{
REG_SET regSet;
taskRegsGet (tid, &regSet);
return ((INSTR *) regSet.pc);
}
/*******************************************************************************
*
* getOneReg - return the contents of one register
*
* Given a task's ID, this routine returns the contents of the register
* specified by the register code. This routine is used by eax, edx, etc.
* The register codes are defined in dbgI86Lib.h.
*
* RETURNS: register contents, or ERROR.
*/
LOCAL int getOneReg (taskId, regCode)
int taskId; /* task's id, 0 means default task */
int regCode; /* code for specifying register */
{
REG_SET regSet; /* get task's regs into here */
taskId = taskIdFigure (taskId); /* translate super name to id */
if (taskId == ERROR) /* couldn't figure out super name */
return (ERROR);
taskId = taskIdDefault (taskId); /* set the default id */
if (taskRegsGet (taskId, &regSet) != OK)
return (ERROR);
switch (regCode)
{
case EDI: return (regSet.edi);
case ESI: return (regSet.esi);
case EBP: return (regSet.ebp);
case ESP: return (regSet.esp);
case EBX: return (regSet.ebx);
case EDX: return (regSet.edx);
case ECX: return (regSet.ecx);
case EAX: return (regSet.eax);
case EFLAGS: return (regSet.eflags);
}
return (ERROR); /* unknown regCode */
}
/*******************************************************************************
*
* edi - return the contents of register `edi' (also `esi' - `eax') (x86/SimNT)
*
* This command extracts the contents of register `edi' from the TCB of a
* specified task. If <taskId> is omitted or zero, the last task
* referenced is assumed.
*
* Similar routines are provided for all address registers (`edi' - `eax'):
* edi() - eax().
*
* The stack pointer is accessed via eax().
*
* RETURNS: The contents of register `edi' (or the requested register).
*
* SEE ALSO:
* .pG "Debugging"
*/
int edi
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, EDI));
}
int esi (taskId) int taskId; { return (getOneReg (taskId, ESI)); }
int ebp (taskId) int taskId; { return (getOneReg (taskId, EBP)); }
int esp (taskId) int taskId; { return (getOneReg (taskId, ESP)); }
int ebx (taskId) int taskId; { return (getOneReg (taskId, EBX)); }
int edx (taskId) int taskId; { return (getOneReg (taskId, EDX)); }
int ecx (taskId) int taskId; { return (getOneReg (taskId, ECX)); }
int eax (taskId) int taskId; { return (getOneReg (taskId, EAX)); }
/*******************************************************************************
*
* eflags - return the contents of the status register (x86/SimNT)
*
* This command extracts the contents of the status register from the TCB of a
* specified task. If <taskId> is omitted or zero, the last task referenced is
* assumed.
*
* RETURNS: The contents of the status register.
*
* SEE ALSO:
* .pG "Debugging"
*/
int eflags
(
int taskId /* task ID, 0 means default task */
)
{
return (getOneReg (taskId, EFLAGS));
}