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immap_8260.h
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：8k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

immap_8260.h：源码内容
  1. /*
  2.  * BK Id: SCCS/s.immap_8260.h 1.8 07/18/01 15:46:50 trini
  3.  */
  5. /*
  6.  * MPC8260 Internal Memory Map
  7.  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
  8.  *
  9.  * The Internal Memory Map of the 8260.  I don't know how generic
  10.  * this will be, as I don't have any knowledge of the subsequent
  11.  * parts at this time.  I copied this from the 8xx_immap.h.
  12.  */
  13. #ifdef __KERNEL__
  14. #ifndef __IMMAP_82XX__
  15. #define __IMMAP_82XX__
  17. /* System configuration registers.
  18. */
  19. typedef struct sys_conf {
  20. uint sc_siumcr;
  21. uint sc_sypcr;
  22. char res1[6];
  23. ushort sc_swsr;
  24. char res2[20];
  25. uint sc_bcr;
  26. u_char sc_ppc_acr;
  27. char res3[3];
  28. uint sc_ppc_alrh;
  29. uint sc_ppc_alrl;
  30. u_char sc_lcl_acr;
  31. char res4[3];
  32. uint sc_lcl_alrh;
  33. uint sc_lcl_alrl;
  34. uint sc_tescr1;
  35. uint sc_tescr2;
  36. uint sc_ltescr1;
  37. uint sc_ltescr2;
  38. uint sc_pdtea;
  39. u_char sc_pdtem;
  40. char res5[3];
  41. uint sc_ldtea;
  42. u_char sc_ldtem;
  43. char res6[163];
  44. } sysconf8260_t;
  47. /* Memory controller registers.
  48. */
  49. typedef struct mem_ctlr {
  50. uint memc_br0;
  51. uint memc_or0;
  52. uint memc_br1;
  53. uint memc_or1;
  54. uint memc_br2;
  55. uint memc_or2;
  56. uint memc_br3;
  57. uint memc_or3;
  58. uint memc_br4;
  59. uint memc_or4;
  60. uint memc_br5;
  61. uint memc_or5;
  62. uint memc_br6;
  63. uint memc_or6;
  64. uint memc_br7;
  65. uint memc_or7;
  66. uint memc_br8;
  67. uint memc_or8;
  68. uint memc_br9;
  69. uint memc_or9;
  70. uint memc_br10;
  71. uint memc_or10;
  72. uint memc_br11;
  73. uint memc_or11;
  74. char res1[8];
  75. uint memc_mar;
  76. char res2[4];
  77. uint memc_mamr;
  78. uint memc_mbmr;
  79. uint memc_mcmr;
  80. char res3[8];
  81. ushort memc_mptpr;
  82. char res4[2];
  83. uint memc_mdr;
  84. char res5[4];
  85. uint memc_psdmr;
  86. uint memc_lsdmr;
  87. u_char memc_purt;
  88. char res6[3];
  89. u_char memc_psrt;
  90. char res7[3];
  91. u_char memc_lurt;
  92. char res8[3];
  93. u_char memc_lsrt;
  94. char res9[3];
  95. uint memc_immr;
  96. char res10[84];
  97. } memctl8260_t;
  99. /* System Integration Timers.
  100. */
  101. typedef struct sys_int_timers {
  102. char res1[32];
  103. ushort sit_tmcntsc;
  104. char res2[2];
  105. uint sit_tmcnt;
  106. char res3[4];
  107. uint sit_tmcntal;
  108. char res4[16];
  109. ushort sit_piscr;
  110. char res5[2];
  111. uint sit_pitc;
  112. uint sit_pitr;
  113. char res6[94];
  114. char res7[2390];
  115. } sit8260_t;
  117. #define PISCR_PIRQ_MASK ((ushort)0xff00)
  118. #define PISCR_PS ((ushort)0x0080)
  119. #define PISCR_PIE ((ushort)0x0004)
  120. #define PISCR_PTF ((ushort)0x0002)
  121. #define PISCR_PTE ((ushort)0x0001)
  123. /* Interrupt Controller.
  124. */
  125. typedef struct interrupt_controller {
  126. ushort ic_sicr;
  127. char res1[2];
  128. uint ic_sivec;
  129. uint ic_sipnrh;
  130. uint ic_sipnrl;
  131. uint ic_siprr;
  132. uint ic_scprrh;
  133. uint ic_scprrl;
  134. uint ic_simrh;
  135. uint ic_simrl;
  136. uint ic_siexr;
  137. char res2[88];
  138. } intctl8260_t;
  140. /* Clocks and Reset.
  141. */
  142. typedef struct clk_and_reset {
  143. uint car_sccr;
  144. char res1[4];
  145. uint car_scmr;
  146. char res2[4];
  147. uint car_rsr;
  148. uint car_rmr;
  149. char res[104];
  150. } car8260_t;
  152. /* Input/Output Port control/status registers.
  153.  * Names consistent with processor manual, although they are different
  154.  * from the original 8xx names.......
  155.  */
  156. typedef struct io_port {
  157. uint iop_pdira;
  158. uint iop_ppara;
  159. uint iop_psora;
  160. uint iop_podra;
  161. uint iop_pdata;
  162. char res1[12];
  163. uint iop_pdirb;
  164. uint iop_pparb;
  165. uint iop_psorb;
  166. uint iop_podrb;
  167. uint iop_pdatb;
  168. char res2[12];
  169. uint iop_pdirc;
  170. uint iop_pparc;
  171. uint iop_psorc;
  172. uint iop_podrc;
  173. uint iop_pdatc;
  174. char res3[12];
  175. uint iop_pdird;
  176. uint iop_ppard;
  177. uint iop_psord;
  178. uint iop_podrd;
  179. uint iop_pdatd;
  180. char res4[12];
  181. } iop8260_t;
  183. /* Communication Processor Module Timers
  184. */
  185. typedef struct cpm_timers {
  186. u_char cpmt_tgcr1;
  187. char res1[3];
  188. u_char cpmt_tgcr2;
  189. char res2[11];
  190. ushort cpmt_tmr1;
  191. ushort cpmt_tmr2;
  192. ushort cpmt_trr1;
  193. ushort cpmt_trr2;
  194. ushort cpmt_tcr1;
  195. ushort cpmt_tcr2;
  196. ushort cpmt_tcn1;
  197. ushort cpmt_tcn2;
  198. ushort cpmt_tmr3;
  199. ushort cpmt_tmr4;
  200. ushort cpmt_trr3;
  201. ushort cpmt_trr4;
  202. ushort cpmt_tcr3;
  203. ushort cpmt_tcr4;
  204. ushort cpmt_tcn3;
  205. ushort cpmt_tcn4;
  206. ushort cpmt_ter1;
  207. ushort cpmt_ter2;
  208. ushort cpmt_ter3;
  209. ushort cpmt_ter4;
  210. char res3[584];
  211. } cpmtimer8260_t;
  213. /* DMA control/status registers.
  214. */
  215. typedef struct sdma_csr {
  216. char res0[24];
  217. u_char sdma_sdsr;
  218. char res1[3];
  219. u_char sdma_sdmr;
  220. char res2[3];
  221. u_char sdma_idsr1;
  222. char res3[3];
  223. u_char sdma_idmr1;
  224. char res4[3];
  225. u_char sdma_idsr2;
  226. char res5[3];
  227. u_char sdma_idmr2;
  228. char res6[3];
  229. u_char sdma_idsr3;
  230. char res7[3];
  231. u_char sdma_idmr3;
  232. char res8[3];
  233. u_char sdma_idsr4;
  234. char res9[3];
  235. u_char sdma_idmr4;
  236. char res10[707];
  237. } sdma8260_t;
  239. /* Fast controllers
  240. */
  241. typedef struct fcc {
  242. uint fcc_gfmr;
  243. uint fcc_fpsmr;
  244. ushort fcc_ftodr;
  245. char res1[2];
  246. ushort fcc_fdsr;
  247. char res2[2];
  248. ushort fcc_fcce;
  249. char res3[2];
  250. ushort fcc_fccm;
  251. char res4[2];
  252. u_char fcc_fccs;
  253. char res5[3];
  254. u_char fcc_ftirr_phy[4];
  255. } fcc_t;
  257. /* I2C
  258. */
  259. typedef struct i2c {
  260. u_char i2c_i2mod;
  261. char res1[3];
  262. u_char i2c_i2add;
  263. char res2[3];
  264. u_char i2c_i2brg;
  265. char res3[3];
  266. u_char i2c_i2com;
  267. char res4[3];
  268. u_char i2c_i2cer;
  269. char res5[3];
  270. u_char i2c_i2cmr;
  271. char res6[331];
  272. } i2c8260_t;
  274. typedef struct scc { /* Serial communication channels */
  275. uint scc_gsmrl;
  276. uint scc_gsmrh;
  277. ushort scc_pmsr;
  278. char res1[2];
  279. ushort scc_todr;
  280. ushort scc_dsr;
  281. ushort scc_scce;
  282. char res2[2];
  283. ushort scc_sccm;
  284. char res3;
  285. u_char scc_sccs;
  286. char res4[8];
  287. } scc_t;
  289. typedef struct smc { /* Serial management channels */
  290. char res1[2];
  291. ushort smc_smcmr;
  292. char res2[2];
  293. u_char smc_smce;
  294. char res3[3];
  295. u_char smc_smcm;
  296. char res4[5];
  297. } smc_t;
  299. /* Serial Peripheral Interface.
  300. */
  301. typedef struct spi {
  302. ushort spi_spmode;
  303. char res1[4];
  304. u_char spi_spie;
  305. char res2[3];
  306. u_char spi_spim;
  307. char res3[2];
  308. u_char spi_spcom;
  309. char res4[82];
  310. } spi_t;
  312. /* CPM Mux.
  313. */
  314. typedef struct cpmux {
  315. u_char cmx_si1cr;
  316. char res1;
  317. u_char cmx_si2cr;
  318. char res2;
  319. uint cmx_fcr;
  320. uint cmx_scr;
  321. u_char cmx_smr;
  322. char res3;
  323. ushort cmx_uar;
  324. char res4[16];
  325. } cpmux_t;
  327. /* SIRAM control
  328. */
  329. typedef struct siram {
  330. ushort si_amr;
  331. ushort si_bmr;
  332. ushort si_cmr;
  333. ushort si_dmr;
  334. u_char si_gmr;
  335. char res1;
  336. u_char si_cmdr;
  337. char res2;
  338. u_char si_str;
  339. char res3;
  340. ushort si_rsr;
  341. } siramctl_t;
  343. typedef struct mcc {
  344. ushort mcc_mcce;
  345. char res1[2];
  346. ushort mcc_mccm;
  347. char res2[2];
  348. u_char mcc_mccf;
  349. char res3[7];
  350. } mcc_t;
  352. typedef struct comm_proc {
  353. uint cp_cpcr;
  354. uint cp_rccr;
  355. char res1[14];
  356. ushort cp_rter;
  357. char res2[2];
  358. ushort cp_rtmr;
  359. ushort cp_rtscr;
  360. char res3[2];
  361. uint cp_rtsr;
  362. char res4[12];
  363. } cpm8260_t;
  365. /* ...and the whole thing wrapped up....
  366. */
  367. typedef struct immap {
  368. /* Some references are into the unique and known dpram spaces,
  369.  * others are from the generic base.
  370.  */
  371. #define im_dprambase im_dpram1
  372. u_char im_dpram1[16*1024];
  373. char res1[16*1024];
  374. u_char im_dpram2[4*1024];
  375. char res2[8*1024];
  376. u_char im_dpram3[4*1024];
  377. char res3[16*1024];
  379. sysconf8260_t im_siu_conf; /* SIU Configuration */
  380. memctl8260_t im_memctl; /* Memory Controller */
  381. sit8260_t im_sit; /* System Integration Timers */
  382. intctl8260_t im_intctl; /* Interrupt Controller */
  383. car8260_t im_clkrst; /* Clocks and reset */
  384. iop8260_t im_ioport; /* IO Port control/status */
  385. cpmtimer8260_t im_cpmtimer; /* CPM timers */
  386. sdma8260_t im_sdma; /* SDMA control/status */
  388. fcc_t im_fcc[3]; /* Three FCCs */
  390. char res4[159];
  392. /* First set of baud rate generators.
  393. */
  394. char res4a[496];
  395. uint im_brgc5;
  396. uint im_brgc6;
  397. uint im_brgc7;
  398. uint im_brgc8;
  400. char res5[608];
  402. i2c8260_t im_i2c; /* I2C control/status */
  403. cpm8260_t im_cpm; /* Communication processor */
  405. /* Second set of baud rate generators.
  406. */
  407. uint im_brgc1;
  408. uint im_brgc2;
  409. uint im_brgc3;
  410. uint im_brgc4;
  412. scc_t im_scc[4]; /* Four SCCs */
  413. smc_t im_smc[2]; /* Couple of SMCs */
  414. spi_t im_spi; /* A SPI */
  415. cpmux_t im_cpmux; /* CPM clock route mux */
  416. siramctl_t im_siramctl1; /* First SI RAM Control */
  417. mcc_t im_mcc1; /* First MCC */
  418. siramctl_t im_siramctl2; /* Second SI RAM Control */
  419. mcc_t im_mcc2; /* Second MCC */
  421. char res6[1184];
  423. ushort im_si1txram[256];
  424. char res7[512];
  425. ushort im_si1rxram[256];
  426. char res8[512];
  427. ushort im_si2txram[256];
  428. char res9[512];
  429. ushort im_si2rxram[256];
  430. char res10[512];
  431. char res11[4096];
  432. } immap_t;
  434. extern immap_t *immr;
  436. #endif /* __IMMAP_82XX__ */
  437. #endif /* __KERNEL__ */