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ip27config.h
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：21k
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嵌入式Linux

开发平台：

Unix_Linux

ip27config.h：源码内容
  1. /* $Id$
  2.  *
  3.  * This file is subject to the terms and conditions of the GNU General Public
  4.  * License.  See the file "COPYING" in the main directory of this archive
  5.  * for more details.
  6.  *
  7.  * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
  8.  * Copyright (C) 2000 by Colin Ngam
  9.  */
  11. #ifndef _ASM_SN_SN1_IP27CONFIG_H
  12. #define _ASM_SN_SN1_IP27CONFIG_H
  15. /*
  16.  * Structure:  ip27config_s
  17.  * Typedef: ip27config_t
  18.  * Purpose:  Maps out the region of the boot prom used to define
  19.  * configuration information.
  20.  * Notes:       Corresponds to ip27config structure found in start.s.
  21.  * Fields are ulong where possible to facilitate IP27 PROM fetches.
  22.  */
  24. #define CONFIG_INFO_OFFSET 0x60
  26. #define IP27CONFIG_ADDR (LBOOT_BASE     + 
  27.  CONFIG_INFO_OFFSET)
  28. #define IP27CONFIG_ADDR_NODE(n) (NODE_RBOOT_BASE(n) + 
  29.  CONFIG_INFO_OFFSET)
  31. /* Offset to the config_type field within local ip27config structure */
  32. #define CONFIG_FLAGS_ADDR (IP27CONFIG_ADDR + 72)
  33. /* Offset to the config_type field in the ip27config structure on 
  34.  * node with nasid n
  35.  */
  36. #define CONFIG_FLAGS_ADDR_NODE(n) (IP27CONFIG_ADDR_NODE(n) + 72)
  38. /* Meaning of each valid bit in the config flags 
  39.  * None are currently defined
  40.  */
  42. /* Meaning of each mach_type value
  43.  */
  44. #define SN1_MACH_TYPE 0
  46. /*
  47.  * Since 800 ns works well with various HUB frequencies, (such as 360,
  48.  * 380, 390, and 400 MHZ), we now use 800ns rtc cycle time instead of
  49.  * 1 microsec.
  50.  */
  51. #define IP27_RTC_FREQ 1250 /* 800ns cycle time */
  53. #if _LANGUAGE_C
  55. typedef struct ip27config_s { /* KEEP IN SYNC w/ start.s & below  */
  56.     uint time_const; /* Time constant      */
  57.     uint r10k_mode; /* R10k boot mode bits      */
  59.     uint64_t magic; /* CONFIG_MAGIC     */
  61.     uint64_t freq_cpu; /* Hz      */
  62.     uint64_t freq_hub; /* Hz      */
  63.     uint64_t freq_rtc; /* Hz      */
  65.     uint ecc_enable; /* ECC enable flag     */
  66.     uint fprom_cyc; /* FPROM_CYC speed control       */
  68.     uint mach_type; /* Inidicate IP27 (0) or Sn00 (1)    */
  70.     uint check_sum_adj; /* Used after config hdr overlay    */
  71. /* to make the checksum 0 again     */
  72.     uint flash_count; /* Value incr'd on each PROM flash  */
  73.     uint fprom_wr; /* FPROM_WR speed control       */
  75.     uint pvers_vers; /* Prom version number     */
  76.     uint pvers_rev; /* Prom revision number     */
  77.     uint config_type; /* To support special configurations
  78.  * (none currently defined)
  79.  */
  80. } ip27config_t;
  82. typedef struct {
  83.     uint r10k_mode; /* R10k boot mode bits      */
  84.     uint freq_cpu; /* Hz      */
  85.     uint freq_hub; /* Hz      */
  86.     char fprom_cyc; /* FPROM_CYC speed control       */
  87.     char mach_type; /* IP35(0) is only type defined      */
  88.     char fprom_wr; /* FPROM_WR speed control       */
  89. } config_modifiable_t;
  91. #define IP27CONFIG (*(ip27config_t *) IP27CONFIG_ADDR)
  92. #define IP27CONFIG_NODE(n) (*(ip27config_t *) IP27CONFIG_ADDR_NODE(n))
  93. #define SN00 0 /* IP35 has no Speedo equivalent */
  95. /* Get the config flags from local ip27config */
  96. #define CONFIG_FLAGS (*(uint *) (CONFIG_FLAGS_ADDR))
  98. /* Get the config flags from ip27config on the node
  99.  * with nasid n
  100.  */
  101. #define CONFIG_FLAGS_NODE(n) (*(uint *) (CONFIG_FLAGS_ADDR_NODE(n)))
  103. /* Macro to check if the local ip27config indicates a config
  104.  * of 12 p 4io
  105.  */
  106. #define CONFIG_12P4I (0) /* IP35 has no 12p4i equivalent */
  108. /* Macro to check if the ip27config on node with nasid n
  109.  * indicates a config of 12 p 4io
  110.  */
  111. #define CONFIG_12P4I_NODE(n) (0)
  113. #endif /* _LANGUAGE_C */
  115. #if _LANGUAGE_ASSEMBLY
  116. .struct 0 /* KEEP IN SYNC WITH C structure */
  118. ip27c_time_const: .word 0
  119. ip27c_r10k_mode: .word 0
  121. ip27c_magic: .dword 0
  123. ip27c_freq_cpu: .dword 0
  124. ip27c_freq_hub: .dword 0
  125. ip27c_freq_rtc: .dword 0
  127. ip27c_ecc_enable: .word 1
  128. ip27c_fprom_cyc: .word 0
  130. ip27c_mach_type: .word 0
  131. ip27c_check_sum_adj: .word 0
  133. ip27c_flash_count: .word 0
  134. ip27c_fprom_wr: .word 0
  136. ip27c_pvers_vers: .word 0
  137. ip27c_pvers_rev: .word 0
  139. ip27c_config_type: .word  0 /* To recognize special configs */
  140. #endif /* _LANGUAGE_ASSEMBLY */
  142. /*
  143.  * R10000 Configuration Cycle - These define the SYSAD values used
  144.  * during the reset cycle.
  145.  */
  147. #define IP27C_R10000_KSEG0CA_SHFT 0
  148. #define IP27C_R10000_KSEG0CA_MASK (7 << IP27C_R10000_KSEG0CA_SHFT)
  149. #define IP27C_R10000_KSEG0CA(_B)  ((_B) << IP27C_R10000_KSEG0CA_SHFT)
  151. #define IP27C_R10000_DEVNUM_SHFT 3
  152. #define IP27C_R10000_DEVNUM_MASK (3 << IP27C_R10000_DEVNUM_SHFT)
  153. #define IP27C_R10000_DEVNUM(_B) ((_B) << IP27C_R10000_DEVNUM_SHFT)
  155. #define IP27C_R10000_CRPT_SHFT 5
  156. #define IP27C_R10000_CRPT_MASK (1 << IP27C_R10000_CRPT_SHFT)
  157. #define IP27C_R10000_CPRT(_B) ((_B)<<IP27C_R10000_CRPT_SHFT)
  159. #define IP27C_R10000_PER_SHFT 6
  160. #define IP27C_R10000_PER_MASK (1 << IP27C_R10000_PER_SHFT)
  161. #define IP27C_R10000_PER(_B) ((_B) << IP27C_R10000_PER_SHFT)
  163. #define IP27C_R10000_PRM_SHFT 7
  164. #define IP27C_R10000_PRM_MASK (3 << IP27C_R10000_PRM_SHFT)
  165. #define IP27C_R10000_PRM(_B) ((_B) << IP27C_R10000_PRM_SHFT)
  167. #define IP27C_R10000_SCD_SHFT 9
  168. #define IP27C_R10000_SCD_MASK (0xf << IP27C_R10000_SCD_MASK)
  169. #define IP27C_R10000_SCD(_B) ((_B) << IP27C_R10000_SCD_SHFT)
  171. #define IP27C_R10000_SCBS_SHFT 13
  172. #define IP27C_R10000_SCBS_MASK (1 << IP27C_R10000_SCBS_SHFT)
  173. #define IP27C_R10000_SCBS(_B) (((_B)) << IP27C_R10000_SCBS_SHFT)
  175. #define IP27C_R10000_SCCE_SHFT 14
  176. #define IP27C_R10000_SCCE_MASK (1 << IP27C_R10000_SCCE_SHFT)
  177. #define IP27C_R10000_SCCE(_B) ((_B) << IP27C_R10000_SCCE_SHFT)
  179. #define IP27C_R10000_ME_SHFT 15
  180. #define IP27C_R10000_ME_MASK (1 << IP27C_R10000_ME_SHFT)
  181. #define IP27C_R10000_ME(_B) ((_B) << IP27C_R10000_ME_SHFT)
  183. #define IP27C_R10000_SCS_SHFT 16
  184. #define IP27C_R10000_SCS_MASK (7 << IP27C_R10000_SCS_SHFT)
  185. #define IP27C_R10000_SCS(_B) ((_B) << IP27C_R10000_SCS_SHFT)
  187. #define IP27C_R10000_SCCD_SHFT 19
  188. #define IP27C_R10000_SCCD_MASK (7 << IP27C_R10000_SCCD_SHFT)
  189. #define IP27C_R10000_SCCD(_B) ((_B) << IP27C_R10000_SCCD_SHFT)
  191. #define IP27C_R10000_DDR_SHFT 23
  192. #define IP27C_R10000_DDR_MASK (1 << IP27C_R10000_DDR_SHFT)
  193. #define IP27C_R10000_DDR(_B) ((_B) << IP27C_R10000_DDR_SHFT)
  195. #define IP27C_R10000_SCCT_SHFT 25
  196. #define IP27C_R10000_SCCT_MASK (0xf << IP27C_R10000_SCCT_SHFT)
  197. #define IP27C_R10000_SCCT(_B) ((_B) << IP27C_R10000_SCCT_SHFT)
  199. #define IP27C_R10000_ODSC_SHFT 29
  200. #define IP27C_R10000_ODSC_MASK (1 << IP27C_R10000_ODSC_SHFT)
  201. #define IP27C_R10000_ODSC(_B) ((_B) << IP27C_R10000_ODSC_SHFT)
  203. #define IP27C_R10000_ODSYS_SHFT 30
  204. #define IP27C_R10000_ODSYS_MASK (1 << IP27C_R10000_ODSYS_SHFT)
  205. #define IP27C_R10000_ODSYS(_B) ((_B) << IP27C_R10000_ODSYS_SHFT)
  207. #define IP27C_R10000_CTM_SHFT 31
  208. #define IP27C_R10000_CTM_MASK (1 << IP27C_R10000_CTM_SHFT)
  209. #define IP27C_R10000_CTM(_B) ((_B) << IP27C_R10000_CTM_SHFT)
  211. #define IP27C_MHZ(x) (1000000 * (x))
  212. #define IP27C_KHZ(x) (1000 * (x))
  213. #define IP27C_MB(x) ((x) << 20)
  215. /*
  216.  * PROM Configurations
  217.  */
  219. #define CONFIG_MAGIC 0x69703237636f6e66
  221. /* The high 32 bits of the "mode bits".  Bits 7..0 contain one more
  222.  * than the number of 5ms clocks in the 100ms "long delay" intervals
  223.  * of the TRex reset sequence.  Bit 8 is the "synergy mode" bit.
  224.  */
  225. #define CONFIG_TIME_CONST 0x15
  227. #define CONFIG_ECC_ENABLE 1
  228. #define CONFIG_CHECK_SUM_ADJ 0
  229. #define CONFIG_DEFAULT_FLASH_COUNT    0
  231. /*
  232.  * Some promICEs have trouble if CONFIG_FPROM_SETUP is too low.
  233.  * The nominal value for 100 MHz hub is 5, for 200MHz bedrock is 16.
  234.  * any update to the below should also reflected in the logic in
  235.  *   IO7prom/flashprom.c function _verify_config_info and _fill_in_config_info
  236.  */
  238. /* default junk bus timing values to use */
  239. #define CONFIG_SYNERGY_ENABLE 0xff
  240. #define CONFIG_SYNERGY_SETUP 0xff
  241. #define CONFIG_UART_ENABLE 0x0c
  242. #define CONFIG_UART_SETUP 0x02
  243. #define CONFIG_FPROM_ENABLE 0x10
  244. #define CONFIG_FPROM_SETUP 0x10
  246. #define CONFIG_FREQ_RTC IP27C_KHZ(IP27_RTC_FREQ)
  248. #if _LANGUAGE_C
  250. /* we are going to define all the known configs is a table
  251.  * for building hex images we will pull out the particular
  252.  * slice we care about by using the IP27_CONFIG_XX_XX as
  253.  * entries into the table
  254.  * to keep the table of reasonable size we only include the
  255.  * values that differ across configurations
  256.  * please note then that this makes assumptions about what
  257.  * will and will not change across configurations
  258.  */
  260. /* these numbers are as the are ordered in the table below */
  261. #define IP27_CONFIG_UNKNOWN -1
  262. #define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0
  263. #define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1
  264. #define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2
  265. #define IP27_CONFIG_SN1_8MB_200_500_250_TABLE 3
  266. #define IP27_CONFIG_SN1_8MB_200_400_267_TABLE 4
  267. #define IP27_CONFIG_SN1_4MB_180_360_240_TABLE 5
  268. #define NUMB_IP_CONFIGS 6
  270. #ifdef DEF_IP_CONFIG_TABLE
  271. /*
  272.  * N.B.: A new entry needs to be added here everytime a new config is added
  273.  * The table is indexed by the PIMM PSC value
  274.  */
  276. static int psc_to_flash_config[] = {
  277.         IP27_CONFIG_SN1_4MB_200_400_267_TABLE, /* 0x0 */
  278.         IP27_CONFIG_SN1_8MB_200_500_250_TABLE, /* 0x1 */
  279.         IP27_CONFIG_SN1_8MB_200_400_267_TABLE, /* 0x2 */
  280.         IP27_CONFIG_UNKNOWN, /* 0x3 */
  281.         IP27_CONFIG_UNKNOWN, /* 0x4 */
  282.         IP27_CONFIG_UNKNOWN, /* 0x5 */
  283.         IP27_CONFIG_UNKNOWN, /* 0x6 */
  284.         IP27_CONFIG_UNKNOWN, /* 0x7 */
  285.         IP27_CONFIG_SN1_4MB_180_360_240_TABLE, /* 0x8 */
  286.         IP27_CONFIG_UNKNOWN, /* 0x9 */
  287.         IP27_CONFIG_UNKNOWN, /* 0xa */
  288.         IP27_CONFIG_UNKNOWN, /* 0xb */
  289.         IP27_CONFIG_UNKNOWN, /* 0xc */
  290.         IP27_CONFIG_UNKNOWN, /* 0xd */
  291.         IP27_CONFIG_SN00_4MB_100_200_133_TABLE, /* 0xe  O200 PIMM for bringup */
  292.         IP27_CONFIG_UNKNOWN /* 0xf == PIMM not installed */
  293. };
  295. static config_modifiable_t ip_config_table[NUMB_IP_CONFIGS] = {
  296. /* the 1MB_200_400_200 values (Generic settings, will work for any config.) */
  297. {
  298. (IP27C_R10000_KSEG0CA(5) + 
  299.  IP27C_R10000_DEVNUM(0)  + 
  300.  IP27C_R10000_CPRT(0)  + 
  301.  IP27C_R10000_PER(0)  + 
  302.  IP27C_R10000_PRM(3)  + 
  303.  IP27C_R10000_SCD(3)  + 
  304.  IP27C_R10000_SCBS(1)  + 
  305.  IP27C_R10000_SCCE(0)  + 
  306.  IP27C_R10000_ME(1)  + 
  307.  IP27C_R10000_SCS(1)  + 
  308.  IP27C_R10000_SCCD(3)  + 
  309.  IP27C_R10000_SCCT(9)  + 
  310.  IP27C_R10000_ODSC(0)  + 
  311.  IP27C_R10000_ODSYS(1)  + 
  312.  IP27C_R10000_CTM(0)),
  313. IP27C_MHZ(400),
  314. IP27C_MHZ(200),
  315. CONFIG_FPROM_SETUP,
  316. SN1_MACH_TYPE,
  317. CONFIG_FPROM_ENABLE
  318. },
  320. /* the 4MB_100_200_133 values (O200 PIMM w/translation board, PSC 0xe)
  321.  * (SysAD at 100MHz (SCD=3), and bedrock core at 200 MHz) */
  322. {
  323.  /* ODSYS == 0 means HSTL1 on SysAD bus; other PIMMs use HSTL2 */
  324. (IP27C_R10000_KSEG0CA(5) + 
  325.  IP27C_R10000_DEVNUM(0)  + 
  326.  IP27C_R10000_CPRT(0)  + 
  327.  IP27C_R10000_PER(0)  + 
  328.  IP27C_R10000_PRM(3)  + 
  329.  IP27C_R10000_SCD(3)  + 
  330.  IP27C_R10000_SCBS(1)  + 
  331.  IP27C_R10000_SCCE(0)  + 
  332.  IP27C_R10000_ME(1)  + 
  333.  IP27C_R10000_SCS(3)  + 
  334.  IP27C_R10000_SCCD(2)  + 
  335.  IP27C_R10000_SCCT(9)  + 
  336.  IP27C_R10000_ODSC(0)  + 
  337.  IP27C_R10000_ODSYS(0)  + 
  338.  IP27C_R10000_CTM(0)),
  339. IP27C_MHZ(200),
  340. IP27C_MHZ(200),
  341. CONFIG_FPROM_SETUP,
  342. SN1_MACH_TYPE,
  343. CONFIG_FPROM_ENABLE
  344. },
  346. /* 4MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1602-001, PSC 0x0) */
  347. {
  348. (IP27C_R10000_KSEG0CA(5) + 
  349.  IP27C_R10000_DEVNUM(0)  + 
  350.  IP27C_R10000_CPRT(0)  + 
  351.  IP27C_R10000_PER(0)  + 
  352.  IP27C_R10000_PRM(3)  + 
  353.  IP27C_R10000_SCD(3)  + 
  354.  IP27C_R10000_SCBS(1)  + 
  355.  IP27C_R10000_SCCE(0)  + 
  356.  IP27C_R10000_ME(1)  + 
  357.  IP27C_R10000_SCS(3)  + 
  358.  IP27C_R10000_SCCD(2)  + 
  359.  IP27C_R10000_SCCT(0xa)  + 
  360.  IP27C_R10000_ODSC(0)  + 
  361.  IP27C_R10000_ODSYS(1)  + 
  362.  IP27C_R10000_CTM(0)),
  363. IP27C_MHZ(400),
  364. IP27C_MHZ(200),
  365. CONFIG_FPROM_SETUP,
  366. SN1_MACH_TYPE,
  367. CONFIG_FPROM_ENABLE
  368. },
  370. /* 8MB_200_500_250 values (R14K, 4.0ns, DDR1, 030-1520-001, PSC 0x1) */
  371. {
  372. (IP27C_R10000_KSEG0CA(5) + 
  373.  IP27C_R10000_DEVNUM(0)  + 
  374.  IP27C_R10000_CPRT(0)  + 
  375.  IP27C_R10000_PER(0)  + 
  376.  IP27C_R10000_PRM(3)  + 
  377.  IP27C_R10000_SCD(4)  + 
  378.  IP27C_R10000_SCBS(1)  + 
  379.  IP27C_R10000_SCCE(0)  + 
  380.  IP27C_R10000_ME(1)  + 
  381.  IP27C_R10000_SCS(4)  + 
  382.  IP27C_R10000_DDR(1)     + 
  383.  IP27C_R10000_SCCD(3)  + 
  384.  IP27C_R10000_SCCT(0xa)  + 
  385.  IP27C_R10000_ODSC(0)  + 
  386.  IP27C_R10000_ODSYS(1)  + 
  387.  IP27C_R10000_CTM(0)),
  388. IP27C_MHZ(500),
  389. IP27C_MHZ(200),
  390. CONFIG_FPROM_SETUP,
  391. SN1_MACH_TYPE,
  392. CONFIG_FPROM_ENABLE
  393. },
  395. /* 8MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1616-001, PSC 0x2) */
  396. {
  397. (IP27C_R10000_KSEG0CA(5) + 
  398.  IP27C_R10000_DEVNUM(0)  + 
  399.  IP27C_R10000_CPRT(0)  + 
  400.  IP27C_R10000_PER(0)  + 
  401.  IP27C_R10000_PRM(3)  + 
  402.  IP27C_R10000_SCD(3)  + 
  403.  IP27C_R10000_SCBS(1)  + 
  404.  IP27C_R10000_SCCE(0)  + 
  405.  IP27C_R10000_ME(1)  + 
  406.  IP27C_R10000_SCS(4)  + 
  407.  IP27C_R10000_SCCD(2)  + 
  408.  IP27C_R10000_SCCT(0xa)  + 
  409.  IP27C_R10000_ODSC(0)  + 
  410.  IP27C_R10000_ODSYS(1)  + 
  411.  IP27C_R10000_CTM(0)),
  412. IP27C_MHZ(400),
  413. IP27C_MHZ(200),
  414. CONFIG_FPROM_SETUP,
  415. SN1_MACH_TYPE,
  416. CONFIG_FPROM_ENABLE
  417. },
  419. /* 4MB_180_360_240 values (R12KS, 3.7ns, LWR, 030-1627-001, PSC 0x8)
  420.  * (SysAD at 180 MHz (SCD=3, the fastest possible), bedrock core at 200MHz) */
  421. {
  422. (IP27C_R10000_KSEG0CA(5) + 
  423.  IP27C_R10000_DEVNUM(0)  + 
  424.  IP27C_R10000_CPRT(0)  + 
  425.  IP27C_R10000_PER(0)  + 
  426.  IP27C_R10000_PRM(3)  + 
  427.  IP27C_R10000_SCD(3)  + 
  428.  IP27C_R10000_SCBS(1)  + 
  429.  IP27C_R10000_SCCE(0)  + 
  430.  IP27C_R10000_ME(1)  + 
  431.  IP27C_R10000_SCS(3)  + 
  432.  IP27C_R10000_SCCD(2)  + 
  433.  IP27C_R10000_SCCT(9)  + 
  434.  IP27C_R10000_ODSC(0)  + 
  435.  IP27C_R10000_ODSYS(1)  + 
  436.  IP27C_R10000_CTM(0)),
  437. IP27C_MHZ(360),
  438. IP27C_MHZ(200),
  439. CONFIG_FPROM_SETUP,
  440. SN1_MACH_TYPE,
  441. CONFIG_FPROM_ENABLE
  442. },
  444. };
  445. #else
  446. extern config_modifiable_t ip_config_table[];
  447. #endif /* DEF_IP27_CONFIG_TABLE */
  449. #ifdef IP27_CONFIG_SN00_4MB_100_200_133
  450. #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].r10k_mode
  451. #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_cpu
  452. #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_hub
  453. #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_cyc
  454. #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].mach_type
  455. #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_wr
  456. #endif /* IP27_CONFIG_SN00_4MB_100_200_133 */
  458. #ifdef IP27_CONFIG_SN1_1MB_200_400_200
  459. #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].r10k_mode
  460. #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_cpu
  461. #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_hub
  462. #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_cyc
  463. #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].mach_type
  464. #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_wr
  465. #endif /* IP27_CONFIG_SN1_1MB_200_400_200 */
  467. #ifdef IP27_CONFIG_SN1_4MB_200_400_267
  468. #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].r10k_mode
  469. #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_cpu
  470. #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_hub
  471. #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_cyc
  472. #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].mach_type
  473. #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_wr
  474. #endif /* IP27_CONFIG_SN1_4MB_200_400_267 */
  476. #ifdef IP27_CONFIG_SN1_8MB_200_500_250
  477. #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].r10k_mode
  478. #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_cpu
  479. #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_hub
  480. #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_cyc
  481. #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].mach_type
  482. #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_wr
  483. #endif /* IP27_CONFIG_SN1_8MB_200_500_250 */
  485. #ifdef IP27_CONFIG_SN1_8MB_200_400_267
  486. #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].r10k_mode
  487. #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_cpu
  488. #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_hub
  489. #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_cyc
  490. #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].mach_type
  491. #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_wr
  492. #endif /* IP27_CONFIG_SN1_8MB_200_400_267 */
  494. #ifdef IP27_CONFIG_SN1_4MB_180_360_240
  495. #define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].r10k_mode
  496. #define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_cpu
  497. #define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_hub
  498. #define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_cyc
  499. #define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].mach_type
  500. #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr
  501. #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
  503. #endif /* _LANGUAGE_C */
  505. #if _LANGUAGE_ASSEMBLY
  507. /* these need to be in here since we need assembly definitions
  508.  * for building hex images (as required by start.s)
  509.  */
  510. #ifdef IP27_CONFIG_SN00_4MB_100_200_133
  511. #define BRINGUP_PRM_VAL 3
  512. #define CONFIG_CPU_MODE 
  513. (IP27C_R10000_KSEG0CA(5) + 
  514.  IP27C_R10000_DEVNUM(0)  + 
  515.  IP27C_R10000_CPRT(0)  + 
  516.  IP27C_R10000_PER(0)  + 
  517.  IP27C_R10000_PRM(BRINGUP_PRM_VAL)  + 
  518.  IP27C_R10000_SCD(3)  + 
  519.  IP27C_R10000_SCBS(1)  + 
  520.  IP27C_R10000_SCCE(0)  + 
  521.  IP27C_R10000_ME(1)  + 
  522.  IP27C_R10000_SCS(3)  + 
  523.  IP27C_R10000_SCCD(2)  + 
  524.  IP27C_R10000_SCCT(9)  + 
  525.  IP27C_R10000_ODSC(0)  + 
  526.  IP27C_R10000_ODSYS(0)  + 
  527.  IP27C_R10000_CTM(0))
  528. #define CONFIG_FREQ_CPU IP27C_MHZ(200)
  529. #define CONFIG_FREQ_HUB IP27C_MHZ(200)
  530. #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
  531. #define CONFIG_MACH_TYPE SN1_MACH_TYPE
  532. #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
  533. #endif /* IP27_CONFIG_SN00_4MB_100_200_133 */
  535. #ifdef IP27_CONFIG_SN1_1MB_200_400_200
  536. #define CONFIG_CPU_MODE 
  537. (IP27C_R10000_KSEG0CA(5) + 
  538.  IP27C_R10000_DEVNUM(0)  + 
  539.  IP27C_R10000_CPRT(0)  + 
  540.  IP27C_R10000_PER(0)  + 
  541.  IP27C_R10000_PRM(3)  + 
  542.  IP27C_R10000_SCD(3)  + 
  543.  IP27C_R10000_SCBS(1)  + 
  544.  IP27C_R10000_SCCE(0)  + 
  545.  IP27C_R10000_ME(1)  + 
  546.  IP27C_R10000_SCS(1)  + 
  547.  IP27C_R10000_SCCD(3)  + 
  548.  IP27C_R10000_SCCT(9)  + 
  549.  IP27C_R10000_ODSC(0)  + 
  550.  IP27C_R10000_ODSYS(1)  + 
  551.  IP27C_R10000_CTM(0))
  552. #define CONFIG_FREQ_CPU IP27C_MHZ(400)
  553. #define CONFIG_FREQ_HUB IP27C_MHZ(200)
  554. #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
  555. #define CONFIG_MACH_TYPE SN1_MACH_TYPE
  556. #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
  557. #endif /* IP27_CONFIG_SN1_1MB_200_400_200 */
  559. #ifdef IP27_CONFIG_SN1_4MB_200_400_267
  560. #define CONFIG_CPU_MODE 
  561. (IP27C_R10000_KSEG0CA(5) + 
  562.  IP27C_R10000_DEVNUM(0)  + 
  563.  IP27C_R10000_CPRT(0)  + 
  564.  IP27C_R10000_PER(0)  + 
  565.  IP27C_R10000_PRM(3)  + 
  566.  IP27C_R10000_SCD(3)  + 
  567.  IP27C_R10000_SCBS(1)  + 
  568.  IP27C_R10000_SCCE(0)  + 
  569.  IP27C_R10000_ME(1)  + 
  570.  IP27C_R10000_SCS(3)  + 
  571.  IP27C_R10000_SCCD(2)  + 
  572.  IP27C_R10000_SCCT(0xa)  + 
  573.  IP27C_R10000_ODSC(0)  + 
  574.  IP27C_R10000_ODSYS(1)  + 
  575.  IP27C_R10000_CTM(0))
  576. #define CONFIG_FREQ_CPU IP27C_MHZ(400)
  577. #define CONFIG_FREQ_HUB IP27C_MHZ(200)
  578. #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
  579. #define CONFIG_MACH_TYPE SN1_MACH_TYPE
  580. #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
  581. #endif /* IP27_CONFIG_SN1_4MB_200_400_267 */
  583. #ifdef IP27_CONFIG_SN1_8MB_200_500_250
  584. #define CONFIG_CPU_MODE 
  585. (IP27C_R10000_KSEG0CA(5) + 
  586.  IP27C_R10000_DEVNUM(0)  + 
  587.  IP27C_R10000_CPRT(0)  + 
  588.  IP27C_R10000_PER(0)  + 
  589.  IP27C_R10000_PRM(3)  + 
  590.  IP27C_R10000_SCD(4)  + 
  591.  IP27C_R10000_SCBS(1)  + 
  592.  IP27C_R10000_SCCE(0)  + 
  593.  IP27C_R10000_ME(1)  + 
  594.  IP27C_R10000_SCS(4)  + 
  595.  IP27C_R10000_SCCD(3)  + 
  596.          IP27C_R10000_DDR(1)     + 
  597.  IP27C_R10000_SCCT(0xa)  + 
  598.  IP27C_R10000_ODSC(0)  + 
  599.  IP27C_R10000_ODSYS(1)  + 
  600.  IP27C_R10000_CTM(0))
  601. #define CONFIG_FREQ_CPU IP27C_MHZ(500)
  602. #define CONFIG_FREQ_HUB IP27C_MHZ(200)
  603. #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
  604. #define CONFIG_MACH_TYPE SN1_MACH_TYPE
  605. #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
  606. #endif /* IP27_CONFIG_SN1_8MB_200_500_250 */
  608. #ifdef IP27_CONFIG_SN1_8MB_200_400_267
  609. #define CONFIG_CPU_MODE 
  610. (IP27C_R10000_KSEG0CA(5) + 
  611.  IP27C_R10000_DEVNUM(0)  + 
  612.  IP27C_R10000_CPRT(0)  + 
  613.  IP27C_R10000_PER(0)  + 
  614.  IP27C_R10000_PRM(3)  + 
  615.  IP27C_R10000_SCD(3)  + 
  616.  IP27C_R10000_SCBS(1)  + 
  617.  IP27C_R10000_SCCE(0)  + 
  618.  IP27C_R10000_ME(1)  + 
  619.  IP27C_R10000_SCS(4)  + 
  620.  IP27C_R10000_SCCD(2)  + 
  621.  IP27C_R10000_SCCT(0xa)  + 
  622.  IP27C_R10000_ODSC(0)  + 
  623.  IP27C_R10000_ODSYS(1)  + 
  624.  IP27C_R10000_CTM(0))
  625. #define CONFIG_FREQ_CPU IP27C_MHZ(400)
  626. #define CONFIG_FREQ_HUB IP27C_MHZ(200)
  627. #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
  628. #define CONFIG_MACH_TYPE SN1_MACH_TYPE
  629. #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
  630. #endif /* IP27_CONFIG_SN1_8MB_200_400_267 */
  632. #ifdef IP27_CONFIG_SN1_4MB_180_360_240
  633. #define CONFIG_CPU_MODE 
  634. (IP27C_R10000_KSEG0CA(5) + 
  635.  IP27C_R10000_DEVNUM(0)  + 
  636.  IP27C_R10000_CPRT(0)  + 
  637.  IP27C_R10000_PER(0)  + 
  638.  IP27C_R10000_PRM(3)  + 
  639.  IP27C_R10000_SCD(3)  + 
  640.  IP27C_R10000_SCBS(1)  + 
  641.  IP27C_R10000_SCCE(0)  + 
  642.  IP27C_R10000_ME(1)  + 
  643.  IP27C_R10000_SCS(3)  + 
  644.  IP27C_R10000_SCCD(2)  + 
  645.  IP27C_R10000_SCCT(9)  + 
  646.  IP27C_R10000_ODSC(0)  + 
  647.  IP27C_R10000_ODSYS(1)  + 
  648.  IP27C_R10000_CTM(0))
  649. #define CONFIG_FREQ_CPU IP27C_MHZ(360)
  650. #define CONFIG_FREQ_HUB IP27C_MHZ(200)
  651. #define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP
  652. #define CONFIG_MACH_TYPE SN1_MACH_TYPE
  653. #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
  654. #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
  656. #endif /* _LANGUAGE_C */
  658. #endif /* _ASM_SN_SN1_IP27CONFIG_H */