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hubxb.h
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：43k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

hubxb.h：源码内容
  1. /* $Id$
  2.  *
  3.  * This file is subject to the terms and conditions of the GNU General Public
  4.  * License.  See the file "COPYING" in the main directory of this archive
  5.  * for more details.
  6.  *
  7.  * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
  8.  * Copyright (C) 2000 by Colin Ngam
  9.  */
  10. #ifndef _ASM_SN_SN1_HUBXB_H
  11. #define _ASM_SN_SN1_HUBXB_H
  13. /************************************************************************
  14.  *                                                                      *
  15.  *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
  16.  *                                                                      *
  17.  * This file is created by an automated script. Any (minimal) changes   *
  18.  * made manually to this  file should be made with care.                *
  19.  *                                                                      *
  20.  *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
  21.  *                                                                      *
  22.  ************************************************************************/
  25. #define    XB_PARMS                  0x00700000    /*
  26.                                                     * Controls
  27.                                                     * crossbar-wide
  28.                                                     * parameters.
  29.                                                     */
  33. #define    XB_SLOW_GNT               0x00700008    /*
  34.                                                     * Controls wavefront
  35.                                                     * arbiter grant
  36.                                                     * frequency, used to
  37.                                                     * slow XB grants
  38.                                                     */
  42. #define    XB_SPEW_CONTROL           0x00700010    /*
  43.                                                     * Controls spew
  44.                                                     * settings (debug
  45.                                                     * only).
  46.                                                     */
  50. #define    XB_IOQ_ARB_TRIGGER        0x00700018    /*
  51.                                                     * Controls IOQ
  52.                                                     * trigger level
  53.                                                     */
  57. #define    XB_FIRST_ERROR            0x00700090    /*
  58.                                                     * Records the first
  59.                                                     * crossbar error
  60.                                                     * seen.
  61.                                                     */
  65. #define    XB_POQ0_ERROR             0x00700020    /*
  66.                                                     * POQ0 error
  67.                                                     * register.
  68.                                                     */
  72. #define    XB_PIQ0_ERROR             0x00700028    /*
  73.                                                     * PIQ0 error
  74.                                                     * register.
  75.                                                     */
  79. #define    XB_POQ1_ERROR             0x00700030    /*
  80.                                                     * POQ1 error
  81.                                                     * register.
  82.                                                     */
  86. #define    XB_PIQ1_ERROR             0x00700038    /*
  87.                                                     * PIQ1 error
  88.                                                     * register.
  89.                                                     */
  93. #define    XB_MP0_ERROR              0x00700040    /*
  94.                                                     * MOQ for PI0 error
  95.                                                     * register.
  96.                                                     */
  100. #define    XB_MP1_ERROR              0x00700048    /*
  101.                                                     * MOQ for PI1 error
  102.                                                     * register.
  103.                                                     */
  107. #define    XB_MMQ_ERROR              0x00700050    /*
  108.                                                     * MOQ for misc. (LB,
  109.                                                     * NI, II) error
  110.                                                     * register.
  111.                                                     */
  115. #define    XB_MIQ_ERROR              0x00700058    /*
  116.                                                     * MIQ error register,
  117.                                                     * addtional MIQ
  118.                                                     * errors are logged
  119.                                                     * in MD "Input
  120.                                                     * Error
  121.                                                     * Registers".
  122.                                                     */
  126. #define    XB_NOQ_ERROR              0x00700060    /* NOQ error register.    */
  130. #define    XB_NIQ_ERROR              0x00700068    /* NIQ error register.    */
  134. #define    XB_IOQ_ERROR              0x00700070    /* IOQ error register.    */
  138. #define    XB_IIQ_ERROR              0x00700078    /* IIQ error register.    */
  142. #define    XB_LOQ_ERROR              0x00700080    /* LOQ error register.    */
  146. #define    XB_LIQ_ERROR              0x00700088    /* LIQ error register.    */
  150. #define    XB_DEBUG_DATA_CTL         0x00700098    /*
  151.                                                     * Debug Datapath
  152.                                                     * Select
  153.                                                     */
  157. #define    XB_DEBUG_ARB_CTL          0x007000A0    /*
  158.                                                     * XB master debug
  159.                                                     * control
  160.                                                     */
  164. #define    XB_POQ0_ERROR_CLEAR       0x00700120    /*
  165.                                                     * Clears
  166.                                                     * XB_POQ0_ERROR
  167.                                                     * register.
  168.                                                     */
  172. #define    XB_PIQ0_ERROR_CLEAR       0x00700128    /*
  173.                                                     * Clears
  174.                                                     * XB_PIQ0_ERROR
  175.                                                     * register.
  176.                                                     */
  180. #define    XB_POQ1_ERROR_CLEAR       0x00700130    /*
  181.                                                     * Clears
  182.                                                     * XB_POQ1_ERROR
  183.                                                     * register.
  184.                                                     */
  188. #define    XB_PIQ1_ERROR_CLEAR       0x00700138    /*
  189.                                                     * Clears
  190.                                                     * XB_PIQ1_ERROR
  191.                                                     * register.
  192.                                                     */
  196. #define    XB_MP0_ERROR_CLEAR        0x00700140    /*
  197.                                                     * Clears XB_MP0_ERROR
  198.                                                     * register.
  199.                                                     */
  203. #define    XB_MP1_ERROR_CLEAR        0x00700148    /*
  204.                                                     * Clears XB_MP1_ERROR
  205.                                                     * register.
  206.                                                     */
  210. #define    XB_MMQ_ERROR_CLEAR        0x00700150    /*
  211.                                                     * Clears XB_MMQ_ERROR
  212.                                                     * register.
  213.                                                     */
  217. #define    XB_XM_MIQ_ERROR_CLEAR     0x00700158    /*
  218.                                                     * Clears XB_MIQ_ERROR
  219.                                                     * register
  220.                                                     */
  224. #define    XB_NOQ_ERROR_CLEAR        0x00700160    /*
  225.                                                     * Clears XB_NOQ_ERROR
  226.                                                     * register.
  227.                                                     */
  231. #define    XB_NIQ_ERROR_CLEAR        0x00700168    /*
  232.                                                     * Clears XB_NIQ_ERROR
  233.                                                     * register.
  234.                                                     */
  238. #define    XB_IOQ_ERROR_CLEAR        0x00700170    /*
  239.                                                     * Clears XB_IOQ
  240.                                                     * _ERROR register.
  241.                                                     */
  245. #define    XB_IIQ_ERROR_CLEAR        0x00700178    /*
  246.                                                     * Clears XB_IIQ
  247.                                                     * _ERROR register.
  248.                                                     */
  252. #define    XB_LOQ_ERROR_CLEAR        0x00700180    /*
  253.                                                     * Clears XB_LOQ_ERROR
  254.                                                     * register.
  255.                                                     */
  259. #define    XB_LIQ_ERROR_CLEAR        0x00700188    /*
  260.                                                     * Clears XB_LIQ_ERROR
  261.                                                     * register.
  262.                                                     */
  266. #define    XB_FIRST_ERROR_CLEAR      0x00700190    /*
  267.                                                     * Clears
  268.                                                     * XB_FIRST_ERROR
  269.                                                     * register
  270.                                                     */
  276. #ifdef _LANGUAGE_C
  278. /************************************************************************
  279.  *                                                                      *
  280.  *  Access to parameters which control various aspects of the           *
  281.  * crossbar's operation.                                                *
  282.  *                                                                      *
  283.  ************************************************************************/
  288. #ifdef LITTLE_ENDIAN
  290. typedef union xb_parms_u {
  291. bdrkreg_t xb_parms_regval;
  292. struct  {
  293. bdrkreg_t p_byp_en                  :  1;
  294.                 bdrkreg_t       p_rsrvd_1                 :      3;
  295.                 bdrkreg_t       p_age_wrap                :      8;
  296.                 bdrkreg_t       p_deadlock_to_wrap        :     20;
  297.                 bdrkreg_t       p_tail_to_wrap            :     20;
  298.                 bdrkreg_t       p_rsrvd                   :     12;
  299. } xb_parms_fld_s;
  300. } xb_parms_u_t;
  302. #else
  304. typedef union xb_parms_u {
  305. bdrkreg_t xb_parms_regval;
  306. struct {
  307. bdrkreg_t p_rsrvd   : 12;
  308. bdrkreg_t p_tail_to_wrap   : 20;
  309. bdrkreg_t p_deadlock_to_wrap   : 20;
  310. bdrkreg_t p_age_wrap   :  8;
  311. bdrkreg_t p_rsrvd_1   :  3;
  312. bdrkreg_t p_byp_en   :  1;
  313. } xb_parms_fld_s;
  314. } xb_parms_u_t;
  316. #endif
  321. /************************************************************************
  322.  *                                                                      *
  323.  *  Sets the period of wavefront grants given to each unit. The         *
  324.  * register's value corresponds to the number of cycles between each    *
  325.  * wavefront grant opportunity given to the requesting unit. If set     *
  326.  * to 0xF, no grants are given to this unit. If set to 0xE, the unit    *
  327.  * is granted at the slowest rate (sometimes called "molasses mode").   *
  328.  * This feature can be used to apply backpressure to a unit's output    *
  329.  * queue(s). The setting does not affect bypass grants.                 *
  330.  *                                                                      *
  331.  ************************************************************************/
  336. #ifdef LITTLE_ENDIAN
  338. typedef union xb_slow_gnt_u {
  339. bdrkreg_t xb_slow_gnt_regval;
  340. struct  {
  341. bdrkreg_t sg_lb_slow_gnt            :  4;
  342.                 bdrkreg_t       sg_ii_slow_gnt            :      4;
  343.                 bdrkreg_t       sg_ni_slow_gnt            :      4;
  344.                 bdrkreg_t       sg_mmq_slow_gnt           :      4;
  345.                 bdrkreg_t       sg_mp1_slow_gnt           :      4;
  346.                 bdrkreg_t       sg_mp0_slow_gnt           :      4;
  347.                 bdrkreg_t       sg_pi1_slow_gnt           :      4;
  348.                 bdrkreg_t       sg_pi0_slow_gnt           :      4;
  349.                 bdrkreg_t       sg_rsrvd                  :     32;
  350. } xb_slow_gnt_fld_s;
  351. } xb_slow_gnt_u_t;
  353. #else
  355. typedef union xb_slow_gnt_u {
  356. bdrkreg_t xb_slow_gnt_regval;
  357. struct {
  358. bdrkreg_t sg_rsrvd   : 32;
  359. bdrkreg_t sg_pi0_slow_gnt   :  4;
  360. bdrkreg_t sg_pi1_slow_gnt   :  4;
  361. bdrkreg_t sg_mp0_slow_gnt   :  4;
  362. bdrkreg_t sg_mp1_slow_gnt   :  4;
  363. bdrkreg_t sg_mmq_slow_gnt   :  4;
  364. bdrkreg_t sg_ni_slow_gnt   :  4;
  365. bdrkreg_t sg_ii_slow_gnt   :  4;
  366. bdrkreg_t sg_lb_slow_gnt   :  4;
  367. } xb_slow_gnt_fld_s;
  368. } xb_slow_gnt_u_t;
  370. #endif
  375. /************************************************************************
  376.  *                                                                      *
  377.  *  Enables snooping of internal crossbar traffic by spewing all        *
  378.  * traffic across a selected crossbar point to the PI1 port. Only one   *
  379.  * bit should be set at any one time, and any bit set will preclude     *
  380.  * using the P1 for anything but a debug connection.                    *
  381.  *                                                                      *
  382.  ************************************************************************/
  387. #ifdef LITTLE_ENDIAN
  389. typedef union xb_spew_control_u {
  390. bdrkreg_t xb_spew_control_regval;
  391. struct  {
  392. bdrkreg_t sc_snoop_liq              :  1;
  393.                 bdrkreg_t       sc_snoop_iiq              :      1;
  394.                 bdrkreg_t       sc_snoop_niq              :      1;
  395.                 bdrkreg_t       sc_snoop_miq              :      1;
  396.                 bdrkreg_t       sc_snoop_piq0             :      1;
  397.                 bdrkreg_t       sc_snoop_loq              :      1;
  398.                 bdrkreg_t       sc_snoop_ioq              :      1;
  399.                 bdrkreg_t       sc_snoop_noq              :      1;
  400.                 bdrkreg_t       sc_snoop_mmq              :      1;
  401.                 bdrkreg_t       sc_snoop_mp0              :      1;
  402.                 bdrkreg_t       sc_snoop_poq0             :      1;
  403.                 bdrkreg_t       sc_rsrvd                  :     53;
  404. } xb_spew_control_fld_s;
  405. } xb_spew_control_u_t;
  407. #else
  409. typedef union xb_spew_control_u {
  410. bdrkreg_t xb_spew_control_regval;
  411. struct {
  412. bdrkreg_t sc_rsrvd   : 53;
  413. bdrkreg_t sc_snoop_poq0   :  1;
  414. bdrkreg_t sc_snoop_mp0   :  1;
  415. bdrkreg_t sc_snoop_mmq   :  1;
  416. bdrkreg_t sc_snoop_noq   :  1;
  417. bdrkreg_t sc_snoop_ioq   :  1;
  418. bdrkreg_t sc_snoop_loq   :  1;
  419. bdrkreg_t sc_snoop_piq0   :  1;
  420. bdrkreg_t sc_snoop_miq   :  1;
  421. bdrkreg_t sc_snoop_niq   :  1;
  422. bdrkreg_t sc_snoop_iiq   :  1;
  423. bdrkreg_t sc_snoop_liq   :  1;
  424. } xb_spew_control_fld_s;
  425. } xb_spew_control_u_t;
  427. #endif
  432. /************************************************************************
  433.  *                                                                      *
  434.  *  Number of clocks the IOQ will wait before beginning XB              *
  435.  * arbitration. This is set so that the slower IOQ data rate can        *
  436.  * catch up up with the XB data rate in the IOQ buffer.                 *
  437.  *                                                                      *
  438.  ************************************************************************/
  443. #ifdef LITTLE_ENDIAN
  445. typedef union xb_ioq_arb_trigger_u {
  446. bdrkreg_t xb_ioq_arb_trigger_regval;
  447. struct  {
  448. bdrkreg_t iat_ioq_arb_trigger       :  4;
  449.         bdrkreg_t       iat_rsrvd                 :     60;
  450. } xb_ioq_arb_trigger_fld_s;
  451. } xb_ioq_arb_trigger_u_t;
  453. #else
  455. typedef union xb_ioq_arb_trigger_u {
  456. bdrkreg_t xb_ioq_arb_trigger_regval;
  457. struct {
  458. bdrkreg_t iat_rsrvd   : 60;
  459. bdrkreg_t iat_ioq_arb_trigger   :  4;
  460. } xb_ioq_arb_trigger_fld_s;
  461. } xb_ioq_arb_trigger_u_t;
  463. #endif
  468. /************************************************************************
  469.  *                                                                      *
  470.  *  Records errors seen by POQ0.Can be written to test software, will   *
  471.  * cause an interrupt.                                                  *
  472.  *                                                                      *
  473.  ************************************************************************/
  478. #ifdef LITTLE_ENDIAN
  480. typedef union xb_poq0_error_u {
  481. bdrkreg_t xb_poq0_error_regval;
  482. struct  {
  483. bdrkreg_t pe_invalid_xsel           :  2;
  484.                 bdrkreg_t       pe_rsrvd_3                :      2;
  485.                 bdrkreg_t       pe_overflow               :      2;
  486.                 bdrkreg_t       pe_rsrvd_2                :      2;
  487.                 bdrkreg_t       pe_underflow              :      2;
  488.                 bdrkreg_t       pe_rsrvd_1                :      2;
  489.                 bdrkreg_t       pe_tail_timeout           :      2;
  490.                 bdrkreg_t       pe_unused                 :      6;
  491.                 bdrkreg_t       pe_rsrvd                  :     44;
  492. } xb_poq0_error_fld_s;
  493. } xb_poq0_error_u_t;
  495. #else
  497. typedef union xb_poq0_error_u {
  498. bdrkreg_t xb_poq0_error_regval;
  499. struct {
  500. bdrkreg_t pe_rsrvd   : 44;
  501. bdrkreg_t pe_unused   :  6;
  502. bdrkreg_t pe_tail_timeout   :  2;
  503. bdrkreg_t pe_rsrvd_1   :  2;
  504. bdrkreg_t pe_underflow   :  2;
  505. bdrkreg_t pe_rsrvd_2   :  2;
  506. bdrkreg_t pe_overflow   :  2;
  507. bdrkreg_t pe_rsrvd_3   :  2;
  508. bdrkreg_t pe_invalid_xsel   :  2;
  509. } xb_poq0_error_fld_s;
  510. } xb_poq0_error_u_t;
  512. #endif
  517. /************************************************************************
  518.  *                                                                      *
  519.  *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
  520.  * precludes PIQ underflow.                                             *
  521.  *                                                                      *
  522.  ************************************************************************/
  527. #ifdef LITTLE_ENDIAN
  529. typedef union xb_piq0_error_u {
  530. bdrkreg_t xb_piq0_error_regval;
  531. struct  {
  532. bdrkreg_t pe_overflow               :  2;
  533.                 bdrkreg_t       pe_rsrvd_1                :      2;
  534.                 bdrkreg_t       pe_deadlock_timeout       :      2;
  535.                 bdrkreg_t       pe_rsrvd                  :     58;
  536. } xb_piq0_error_fld_s;
  537. } xb_piq0_error_u_t;
  539. #else
  541. typedef union xb_piq0_error_u {
  542. bdrkreg_t xb_piq0_error_regval;
  543. struct {
  544. bdrkreg_t pe_rsrvd   : 58;
  545. bdrkreg_t pe_deadlock_timeout   :  2;
  546. bdrkreg_t pe_rsrvd_1   :  2;
  547. bdrkreg_t pe_overflow   :  2;
  548. } xb_piq0_error_fld_s;
  549. } xb_piq0_error_u_t;
  551. #endif
  556. /************************************************************************
  557.  *                                                                      *
  558.  *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
  559.  * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
  560.  * errors are possible.                                                 *
  561.  *                                                                      *
  562.  ************************************************************************/
  567. #ifdef LITTLE_ENDIAN
  569. typedef union xb_mp0_error_u {
  570. bdrkreg_t xb_mp0_error_regval;
  571. struct  {
  572. bdrkreg_t me_rsrvd_3                :  4;
  573.                 bdrkreg_t       me_overflow               :      2;
  574.                 bdrkreg_t       me_rsrvd_2                :      2;
  575.                 bdrkreg_t       me_underflow              :      2;
  576.                 bdrkreg_t       me_rsrvd_1                :      2;
  577.                 bdrkreg_t       me_tail_timeout           :      2;
  578.                 bdrkreg_t       me_rsrvd                  :     50;
  579. } xb_mp0_error_fld_s;
  580. } xb_mp0_error_u_t;
  582. #else
  584. typedef union xb_mp0_error_u {
  585. bdrkreg_t xb_mp0_error_regval;
  586. struct {
  587. bdrkreg_t me_rsrvd   : 50;
  588. bdrkreg_t me_tail_timeout   :  2;
  589. bdrkreg_t me_rsrvd_1   :  2;
  590. bdrkreg_t me_underflow   :  2;
  591. bdrkreg_t me_rsrvd_2   :  2;
  592. bdrkreg_t me_overflow   :  2;
  593. bdrkreg_t me_rsrvd_3   :  4;
  594. } xb_mp0_error_fld_s;
  595. } xb_mp0_error_u_t;
  597. #endif
  602. /************************************************************************
  603.  *                                                                      *
  604.  *  Records errors seen by MIQ.                                         *
  605.  *                                                                      *
  606.  ************************************************************************/
  610. #ifdef LITTLE_ENDIAN
  612. typedef union xb_miq_error_u {
  613. bdrkreg_t xb_miq_error_regval;
  614. struct  {
  615. bdrkreg_t me_rsrvd_1                :  4;
  616.                 bdrkreg_t       me_deadlock_timeout       :      4;
  617.                 bdrkreg_t       me_rsrvd                  :     56;
  618. } xb_miq_error_fld_s;
  619. } xb_miq_error_u_t;
  621. #else
  623. typedef union xb_miq_error_u {
  624. bdrkreg_t xb_miq_error_regval;
  625. struct {
  626. bdrkreg_t me_rsrvd   : 56;
  627. bdrkreg_t me_deadlock_timeout   :  4;
  628. bdrkreg_t me_rsrvd_1   :  4;
  629. } xb_miq_error_fld_s;
  630. } xb_miq_error_u_t;
  632. #endif
  637. /************************************************************************
  638.  *                                                                      *
  639.  *  Records errors seen by NOQ.                                         *
  640.  *                                                                      *
  641.  ************************************************************************/
  646. #ifdef LITTLE_ENDIAN
  648. typedef union xb_noq_error_u {
  649. bdrkreg_t xb_noq_error_regval;
  650. struct  {
  651. bdrkreg_t ne_rsvd                   :  4;
  652.                 bdrkreg_t       ne_overflow               :      4;
  653.                 bdrkreg_t       ne_underflow              :      4;
  654.                 bdrkreg_t       ne_tail_timeout           :      4;
  655.                 bdrkreg_t       ne_rsrvd                  :     48;
  656. } xb_noq_error_fld_s;
  657. } xb_noq_error_u_t;
  659. #else
  661. typedef union xb_noq_error_u {
  662. bdrkreg_t xb_noq_error_regval;
  663. struct {
  664. bdrkreg_t ne_rsrvd   : 48;
  665. bdrkreg_t ne_tail_timeout   :  4;
  666. bdrkreg_t ne_underflow   :  4;
  667. bdrkreg_t ne_overflow   :  4;
  668. bdrkreg_t ne_rsvd   :  4;
  669. } xb_noq_error_fld_s;
  670. } xb_noq_error_u_t;
  672. #endif
  677. /************************************************************************
  678.  *                                                                      *
  679.  *  Records errors seen by LOQ.                                         *
  680.  *                                                                      *
  681.  ************************************************************************/
  686. #ifdef LITTLE_ENDIAN
  688. typedef union xb_loq_error_u {
  689. bdrkreg_t xb_loq_error_regval;
  690. struct  {
  691. bdrkreg_t le_invalid_xsel           :  2;
  692.                 bdrkreg_t       le_rsrvd_1                :      6;
  693.                 bdrkreg_t       le_underflow              :      2;
  694.                 bdrkreg_t       le_rsvd                   :      2;
  695.                 bdrkreg_t       le_tail_timeout           :      2;
  696.                 bdrkreg_t       le_rsrvd                  :     50;
  697. } xb_loq_error_fld_s;
  698. } xb_loq_error_u_t;
  700. #else
  702. typedef union xb_loq_error_u {
  703. bdrkreg_t xb_loq_error_regval;
  704. struct {
  705. bdrkreg_t le_rsrvd   : 50;
  706. bdrkreg_t le_tail_timeout   :  2;
  707. bdrkreg_t le_rsvd   :  2;
  708. bdrkreg_t le_underflow   :  2;
  709. bdrkreg_t le_rsrvd_1   :  6;
  710. bdrkreg_t le_invalid_xsel   :  2;
  711. } xb_loq_error_fld_s;
  712. } xb_loq_error_u_t;
  714. #endif
  719. /************************************************************************
  720.  *                                                                      *
  721.  *  Records errors seen by LIQ. Note that the LIQ only records errors   *
  722.  * for the request channel. The reply channel can never deadlock or     *
  723.  * overflow because it does not have hardware flow control.             *
  724.  *                                                                      *
  725.  ************************************************************************/
  730. #ifdef LITTLE_ENDIAN
  732. typedef union xb_liq_error_u {
  733. bdrkreg_t xb_liq_error_regval;
  734. struct  {
  735. bdrkreg_t le_overflow               :  1;
  736.                 bdrkreg_t       le_rsrvd_1                :      3;
  737.                 bdrkreg_t       le_deadlock_timeout       :      1;
  738.                 bdrkreg_t       le_rsrvd                  :     59;
  739. } xb_liq_error_fld_s;
  740. } xb_liq_error_u_t;
  742. #else
  744. typedef union xb_liq_error_u {
  745. bdrkreg_t xb_liq_error_regval;
  746. struct {
  747. bdrkreg_t le_rsrvd   : 59;
  748. bdrkreg_t le_deadlock_timeout   :  1;
  749. bdrkreg_t le_rsrvd_1   :  3;
  750. bdrkreg_t le_overflow   :  1;
  751. } xb_liq_error_fld_s;
  752. } xb_liq_error_u_t;
  754. #endif
  759. /************************************************************************
  760.  *                                                                      *
  761.  *  First error is latched whenever the Valid bit is clear and an       *
  762.  * error occurs. Any valid bit on in this register causes an            *
  763.  * interrupt to PI0 and PI1. This interrupt bit will persist until      *
  764.  * the specific error register to capture the error is cleared, then    *
  765.  * the FIRST_ERROR register is cleared (in that oder.) The              *
  766.  * FIRST_ERROR register is not writable, but will be set when any of    *
  767.  * the corresponding error registers are written by software.           *
  768.  *                                                                      *
  769.  ************************************************************************/
  774. #ifdef LITTLE_ENDIAN
  776. typedef union xb_first_error_u {
  777. bdrkreg_t xb_first_error_regval;
  778. struct  {
  779. bdrkreg_t fe_type                   :  4;
  780.                 bdrkreg_t       fe_channel                :      4;
  781.                 bdrkreg_t       fe_source                 :      4;
  782.                 bdrkreg_t       fe_valid                  :      1;
  783.                 bdrkreg_t       fe_rsrvd                  :     51;
  784. } xb_first_error_fld_s;
  785. } xb_first_error_u_t;
  787. #else
  789. typedef union xb_first_error_u {
  790. bdrkreg_t xb_first_error_regval;
  791. struct {
  792. bdrkreg_t fe_rsrvd   : 51;
  793. bdrkreg_t fe_valid   :  1;
  794. bdrkreg_t fe_source   :  4;
  795. bdrkreg_t fe_channel   :  4;
  796. bdrkreg_t fe_type   :  4;
  797. } xb_first_error_fld_s;
  798. } xb_first_error_u_t;
  800. #endif
  805. /************************************************************************
  806.  *                                                                      *
  807.  *  Controls DEBUG_DATA mux setting. Allows user to watch the output    *
  808.  * of any OQ or input of any IQ on the DEBUG port. Note that bits       *
  809.  * 13:0 are one-hot. If more than one bit is set in [13:0], the debug   *
  810.  * output is undefined. Details on the debug output lines can be        *
  811.  * found in the XB chapter of the Bedrock Interface Specification.      *
  812.  *                                                                      *
  813.  ************************************************************************/
  818. #ifdef LITTLE_ENDIAN
  820. typedef union xb_debug_data_ctl_u {
  821. bdrkreg_t xb_debug_data_ctl_regval;
  822. struct  {
  823. bdrkreg_t ddc_observe_liq_traffic   :  1;
  824.                 bdrkreg_t       ddc_observe_iiq_traffic   :      1;
  825.                 bdrkreg_t       ddc_observe_niq_traffic   :      1;
  826.                 bdrkreg_t       ddc_observe_miq_traffic   :      1;
  827.                 bdrkreg_t       ddc_observe_piq1_traffic  :      1;
  828.                 bdrkreg_t       ddc_observe_piq0_traffic  :      1;
  829.                 bdrkreg_t       ddc_observe_loq_traffic   :      1;
  830.                 bdrkreg_t       ddc_observe_ioq_traffic   :      1;
  831.                 bdrkreg_t       ddc_observe_noq_traffic   :      1;
  832.                 bdrkreg_t       ddc_observe_mp1_traffic   :      1;
  833.                 bdrkreg_t       ddc_observe_mp0_traffic   :      1;
  834.                 bdrkreg_t       ddc_observe_mmq_traffic   :      1;
  835.                 bdrkreg_t       ddc_observe_poq1_traffic  :      1;
  836.                 bdrkreg_t       ddc_observe_poq0_traffic  :      1;
  837.                 bdrkreg_t       ddc_observe_source_field  :      1;
  838.                 bdrkreg_t       ddc_observe_lodata        :      1;
  839.                 bdrkreg_t       ddc_rsrvd                 :     48;
  840. } xb_debug_data_ctl_fld_s;
  841. } xb_debug_data_ctl_u_t;
  843. #else
  845. typedef union xb_debug_data_ctl_u {
  846. bdrkreg_t xb_debug_data_ctl_regval;
  847. struct {
  848. bdrkreg_t ddc_rsrvd   : 48;
  849. bdrkreg_t ddc_observe_lodata   :  1;
  850. bdrkreg_t ddc_observe_source_field  :  1;
  851. bdrkreg_t ddc_observe_poq0_traffic  :  1;
  852. bdrkreg_t ddc_observe_poq1_traffic  :  1;
  853. bdrkreg_t ddc_observe_mmq_traffic   :  1;
  854. bdrkreg_t ddc_observe_mp0_traffic   :  1;
  855. bdrkreg_t ddc_observe_mp1_traffic   :  1;
  856. bdrkreg_t ddc_observe_noq_traffic   :  1;
  857. bdrkreg_t ddc_observe_ioq_traffic   :  1;
  858. bdrkreg_t ddc_observe_loq_traffic   :  1;
  859. bdrkreg_t ddc_observe_piq0_traffic  :  1;
  860. bdrkreg_t ddc_observe_piq1_traffic  :  1;
  861. bdrkreg_t ddc_observe_miq_traffic   :  1;
  862. bdrkreg_t ddc_observe_niq_traffic   :  1;
  863. bdrkreg_t ddc_observe_iiq_traffic   :  1;
  864. bdrkreg_t ddc_observe_liq_traffic   :  1;
  865. } xb_debug_data_ctl_fld_s;
  866. } xb_debug_data_ctl_u_t;
  868. #endif
  873. /************************************************************************
  874.  *                                                                      *
  875.  *  Controls debug mux setting for XB Input/Output Queues and           *
  876.  * Arbiter. Can select one of the following values. Details on the      *
  877.  * debug output lines can be found in the XB chapter of the Bedrock     *
  878.  * Interface Specification.                                             *
  879.  *                                                                      *
  880.  ************************************************************************/
  885. #ifdef LITTLE_ENDIAN
  887. typedef union xb_debug_arb_ctl_u {
  888. bdrkreg_t xb_debug_arb_ctl_regval;
  889. struct  {
  890. bdrkreg_t dac_xb_debug_select       :  3;
  891. bdrkreg_t       dac_rsrvd                 :     61;
  892. } xb_debug_arb_ctl_fld_s;
  893. } xb_debug_arb_ctl_u_t;
  895. #else
  897. typedef union xb_debug_arb_ctl_u {
  898.         bdrkreg_t       xb_debug_arb_ctl_regval;
  899.         struct  {
  900.                 bdrkreg_t       dac_rsrvd                 :     61;
  901.                 bdrkreg_t       dac_xb_debug_select       :      3;
  902.         } xb_debug_arb_ctl_fld_s;
  903. } xb_debug_arb_ctl_u_t;
  905. #endif
  910. /************************************************************************
  911.  *                                                                      *
  912.  *  Records errors seen by POQ0.Can be written to test software, will   *
  913.  * cause an interrupt.                                                  *
  914.  *                                                                      *
  915.  ************************************************************************/
  920. #ifdef LITTLE_ENDIAN
  922. typedef union xb_poq0_error_clear_u {
  923. bdrkreg_t xb_poq0_error_clear_regval;
  924. struct  {
  925. bdrkreg_t pec_invalid_xsel          :  2;
  926.                 bdrkreg_t       pec_rsrvd_3               :      2;
  927.                 bdrkreg_t       pec_overflow              :      2;
  928.                 bdrkreg_t       pec_rsrvd_2               :      2;
  929.                 bdrkreg_t       pec_underflow             :      2;
  930.                 bdrkreg_t       pec_rsrvd_1               :      2;
  931.                 bdrkreg_t       pec_tail_timeout          :      2;
  932.                 bdrkreg_t       pec_unused                :      6;
  933.                 bdrkreg_t       pec_rsrvd                 :     44;
  934. } xb_poq0_error_clear_fld_s;
  935. } xb_poq0_error_clear_u_t;
  937. #else
  939. typedef union xb_poq0_error_clear_u {
  940. bdrkreg_t xb_poq0_error_clear_regval;
  941. struct {
  942. bdrkreg_t pec_rsrvd   : 44;
  943. bdrkreg_t pec_unused   :  6;
  944. bdrkreg_t pec_tail_timeout   :  2;
  945. bdrkreg_t pec_rsrvd_1   :  2;
  946. bdrkreg_t pec_underflow   :  2;
  947. bdrkreg_t pec_rsrvd_2   :  2;
  948. bdrkreg_t pec_overflow   :  2;
  949. bdrkreg_t pec_rsrvd_3   :  2;
  950. bdrkreg_t pec_invalid_xsel   :  2;
  951. } xb_poq0_error_clear_fld_s;
  952. } xb_poq0_error_clear_u_t;
  954. #endif
  959. /************************************************************************
  960.  *                                                                      *
  961.  *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
  962.  * precludes PIQ underflow.                                             *
  963.  *                                                                      *
  964.  ************************************************************************/
  969. #ifdef LITTLE_ENDIAN
  971. typedef union xb_piq0_error_clear_u {
  972. bdrkreg_t xb_piq0_error_clear_regval;
  973. struct  {
  974. bdrkreg_t pec_overflow              :  2;
  975.                 bdrkreg_t       pec_rsrvd_1               :      2;
  976.                 bdrkreg_t       pec_deadlock_timeout      :      2;
  977.                 bdrkreg_t       pec_rsrvd                 :     58;
  978. } xb_piq0_error_clear_fld_s;
  979. } xb_piq0_error_clear_u_t;
  981. #else
  983. typedef union xb_piq0_error_clear_u {
  984. bdrkreg_t xb_piq0_error_clear_regval;
  985. struct {
  986. bdrkreg_t pec_rsrvd   : 58;
  987. bdrkreg_t pec_deadlock_timeout   :  2;
  988. bdrkreg_t pec_rsrvd_1   :  2;
  989. bdrkreg_t pec_overflow   :  2;
  990. } xb_piq0_error_clear_fld_s;
  991. } xb_piq0_error_clear_u_t;
  993. #endif
  998. /************************************************************************
  999.  *                                                                      *
  1000.  *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
  1001.  * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
  1002.  * errors are possible.                                                 *
  1003.  *                                                                      *
  1004.  ************************************************************************/
  1009. #ifdef LITTLE_ENDIAN
  1011. typedef union xb_mp0_error_clear_u {
  1012. bdrkreg_t xb_mp0_error_clear_regval;
  1013. struct  {
  1014. bdrkreg_t mec_rsrvd_3               :  4;
  1015.                 bdrkreg_t       mec_overflow              :      2;
  1016.                 bdrkreg_t       mec_rsrvd_2               :      2;
  1017.                 bdrkreg_t       mec_underflow             :      2;
  1018.                 bdrkreg_t       mec_rsrvd_1               :      2;
  1019.                 bdrkreg_t       mec_tail_timeout          :      2;
  1020.                 bdrkreg_t       mec_rsrvd                 :     50;
  1021. } xb_mp0_error_clear_fld_s;
  1022. } xb_mp0_error_clear_u_t;
  1024. #else
  1026. typedef union xb_mp0_error_clear_u {
  1027. bdrkreg_t xb_mp0_error_clear_regval;
  1028. struct {
  1029. bdrkreg_t mec_rsrvd   : 50;
  1030. bdrkreg_t mec_tail_timeout   :  2;
  1031. bdrkreg_t mec_rsrvd_1   :  2;
  1032. bdrkreg_t mec_underflow   :  2;
  1033. bdrkreg_t mec_rsrvd_2   :  2;
  1034. bdrkreg_t mec_overflow   :  2;
  1035. bdrkreg_t mec_rsrvd_3   :  4;
  1036. } xb_mp0_error_clear_fld_s;
  1037. } xb_mp0_error_clear_u_t;
  1039. #endif
  1044. /************************************************************************
  1045.  *                                                                      *
  1046.  *  Records errors seen by MIQ.                                         *
  1047.  *                                                                      *
  1048.  ************************************************************************/
  1053. #ifdef LITTLE_ENDIAN
  1055. typedef union xb_xm_miq_error_clear_u {
  1056. bdrkreg_t xb_xm_miq_error_clear_regval;
  1057. struct  {
  1058. bdrkreg_t xmec_rsrvd_1              :  4;
  1059.                 bdrkreg_t       xmec_deadlock_timeout     :      4;
  1060.                 bdrkreg_t       xmec_rsrvd                :     56;
  1061. } xb_xm_miq_error_clear_fld_s;
  1062. } xb_xm_miq_error_clear_u_t;
  1064. #else
  1066. typedef union xb_xm_miq_error_clear_u {
  1067. bdrkreg_t xb_xm_miq_error_clear_regval;
  1068. struct {
  1069. bdrkreg_t xmec_rsrvd   : 56;
  1070. bdrkreg_t xmec_deadlock_timeout   :  4;
  1071. bdrkreg_t xmec_rsrvd_1   :  4;
  1072. } xb_xm_miq_error_clear_fld_s;
  1073. } xb_xm_miq_error_clear_u_t;
  1075. #endif
  1080. /************************************************************************
  1081.  *                                                                      *
  1082.  *  Records errors seen by NOQ.                                         *
  1083.  *                                                                      *
  1084.  ************************************************************************/
  1089. #ifdef LITTLE_ENDIAN
  1091. typedef union xb_noq_error_clear_u {
  1092. bdrkreg_t xb_noq_error_clear_regval;
  1093. struct  {
  1094. bdrkreg_t nec_rsvd                  :  4;
  1095.                 bdrkreg_t       nec_overflow              :      4;
  1096.                 bdrkreg_t       nec_underflow             :      4;
  1097.                 bdrkreg_t       nec_tail_timeout          :      4;
  1098.                 bdrkreg_t       nec_rsrvd                 :     48;
  1099. } xb_noq_error_clear_fld_s;
  1100. } xb_noq_error_clear_u_t;
  1102. #else
  1104. typedef union xb_noq_error_clear_u {
  1105. bdrkreg_t xb_noq_error_clear_regval;
  1106. struct {
  1107. bdrkreg_t nec_rsrvd   : 48;
  1108. bdrkreg_t nec_tail_timeout   :  4;
  1109. bdrkreg_t nec_underflow   :  4;
  1110. bdrkreg_t nec_overflow   :  4;
  1111. bdrkreg_t nec_rsvd   :  4;
  1112. } xb_noq_error_clear_fld_s;
  1113. } xb_noq_error_clear_u_t;
  1115. #endif
  1120. /************************************************************************
  1121.  *                                                                      *
  1122.  *  Records errors seen by LOQ.                                         *
  1123.  *                                                                      *
  1124.  ************************************************************************/
  1129. #ifdef LITTLE_ENDIAN
  1131. typedef union xb_loq_error_clear_u {
  1132. bdrkreg_t xb_loq_error_clear_regval;
  1133. struct  {
  1134. bdrkreg_t lec_invalid_xsel          :  2;
  1135.                 bdrkreg_t       lec_rsrvd_1               :      6;
  1136.                 bdrkreg_t       lec_underflow             :      2;
  1137.                 bdrkreg_t       lec_rsvd                  :      2;
  1138.                 bdrkreg_t       lec_tail_timeout          :      2;
  1139.                 bdrkreg_t       lec_rsrvd                 :     50;
  1140. } xb_loq_error_clear_fld_s;
  1141. } xb_loq_error_clear_u_t;
  1143. #else
  1145. typedef union xb_loq_error_clear_u {
  1146. bdrkreg_t xb_loq_error_clear_regval;
  1147. struct {
  1148. bdrkreg_t lec_rsrvd   : 50;
  1149. bdrkreg_t lec_tail_timeout   :  2;
  1150. bdrkreg_t lec_rsvd   :  2;
  1151. bdrkreg_t lec_underflow   :  2;
  1152. bdrkreg_t lec_rsrvd_1   :  6;
  1153. bdrkreg_t lec_invalid_xsel   :  2;
  1154. } xb_loq_error_clear_fld_s;
  1155. } xb_loq_error_clear_u_t;
  1157. #endif
  1162. /************************************************************************
  1163.  *                                                                      *
  1164.  *  Records errors seen by LIQ. Note that the LIQ only records errors   *
  1165.  * for the request channel. The reply channel can never deadlock or     *
  1166.  * overflow because it does not have hardware flow control.             *
  1167.  *                                                                      *
  1168.  ************************************************************************/
  1173. #ifdef LITTLE_ENDIAN
  1175. typedef union xb_liq_error_clear_u {
  1176. bdrkreg_t xb_liq_error_clear_regval;
  1177. struct  {
  1178. bdrkreg_t lec_overflow              :  1;
  1179.                 bdrkreg_t       lec_rsrvd_1               :      3;
  1180.                 bdrkreg_t       lec_deadlock_timeout      :      1;
  1181.                 bdrkreg_t       lec_rsrvd                 :     59;
  1182. } xb_liq_error_clear_fld_s;
  1183. } xb_liq_error_clear_u_t;
  1185. #else
  1187. typedef union xb_liq_error_clear_u {
  1188.         bdrkreg_t       xb_liq_error_clear_regval;
  1189.         struct  {
  1190.                 bdrkreg_t       lec_rsrvd                 :     59;
  1191.                 bdrkreg_t       lec_deadlock_timeout      :      1;
  1192.                 bdrkreg_t       lec_rsrvd_1               :      3;
  1193.                 bdrkreg_t       lec_overflow              :      1;
  1194.         } xb_liq_error_clear_fld_s;
  1195. } xb_liq_error_clear_u_t;
  1197. #endif
  1202. /************************************************************************
  1203.  *                                                                      *
  1204.  *  First error is latched whenever the Valid bit is clear and an       *
  1205.  * error occurs. Any valid bit on in this register causes an            *
  1206.  * interrupt to PI0 and PI1. This interrupt bit will persist until      *
  1207.  * the specific error register to capture the error is cleared, then    *
  1208.  * the FIRST_ERROR register is cleared (in that oder.) The              *
  1209.  * FIRST_ERROR register is not writable, but will be set when any of    *
  1210.  * the corresponding error registers are written by software.           *
  1211.  *                                                                      *
  1212.  ************************************************************************/
  1217. #ifdef LITTLE_ENDIAN
  1219. typedef union xb_first_error_clear_u {
  1220. bdrkreg_t xb_first_error_clear_regval;
  1221. struct  {
  1222. bdrkreg_t fec_type                  :  4;
  1223.                 bdrkreg_t       fec_channel               :      4;
  1224.                 bdrkreg_t       fec_source                :      4;
  1225.                 bdrkreg_t       fec_valid                 :      1;
  1226.                 bdrkreg_t       fec_rsrvd                 :     51;
  1227. } xb_first_error_clear_fld_s;
  1228. } xb_first_error_clear_u_t;
  1230. #else
  1232. typedef union xb_first_error_clear_u {
  1233. bdrkreg_t xb_first_error_clear_regval;
  1234. struct {
  1235. bdrkreg_t fec_rsrvd   : 51;
  1236. bdrkreg_t fec_valid   :  1;
  1237. bdrkreg_t fec_source   :  4;
  1238. bdrkreg_t fec_channel   :  4;
  1239. bdrkreg_t fec_type   :  4;
  1240. } xb_first_error_clear_fld_s;
  1241. } xb_first_error_clear_u_t;
  1243. #endif
  1250. #endif /* _LANGUAGE_C */
  1252. /************************************************************************
  1253.  *                                                                      *
  1254.  * The following defines were not formed into structures                *
  1255.  *                                                                      *
  1256.  * This could be because the document did not contain details of the    *
  1257.  * register, or because the automated script did not recognize the      *
  1258.  * register details in the documentation. If these register need        *
  1259.  * structure definition, please create them manually                    *
  1260.  *                                                                      *
  1261.  *           XB_POQ1_ERROR            0x700030                          *
  1262.  *           XB_PIQ1_ERROR            0x700038                          *
  1263.  *           XB_MP1_ERROR             0x700048                          *
  1264.  *           XB_MMQ_ERROR             0x700050                          *
  1265.  *           XB_NIQ_ERROR             0x700068                          *
  1266.  *           XB_IOQ_ERROR             0x700070                          *
  1267.  *           XB_IIQ_ERROR             0x700078                          *
  1268.  *           XB_POQ1_ERROR_CLEAR      0x700130                          *
  1269.  *           XB_PIQ1_ERROR_CLEAR      0x700138                          *
  1270.  *           XB_MP1_ERROR_CLEAR       0x700148                          *
  1271.  *           XB_MMQ_ERROR_CLEAR       0x700150                          *
  1272.  *           XB_NIQ_ERROR_CLEAR       0x700168                          *
  1273.  *           XB_IOQ_ERROR_CLEAR       0x700170                          *
  1274.  *           XB_IIQ_ERROR_CLEAR       0x700178                          *
  1275.  *                                                                      *
  1276.  ************************************************************************/
  1279. /************************************************************************
  1280.  *                                                                      *
  1281.  *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
  1282.  *                                                                      *
  1283.  ************************************************************************/
  1289. #endif /* _ASM_SN_SN1_HUBXB_H */