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bridge.h
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：72k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

bridge.h：源码内容
  1. /* $Id$
  2.  *
  3.  * This file is subject to the terms and conditions of the GNU General Public
  4.  * License.  See the file "COPYING" in the main directory of this archive
  5.  * for more details.
  6.  *
  7.  * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
  8.  * Copyright (C) 2000 by Colin Ngam
  9.  */
  10. #ifndef _ASM_SN_PCI_BRIDGE_H
  11. #define _ASM_SN_PCI_BRIDGE_H
  14. /*
  15.  * bridge.h - header file for bridge chip and bridge portion of xbridge chip
  16.  */
  18. #include <asm/sn/xtalk/xwidget.h>
  20. /* I/O page size */
  22. #if _PAGESZ == 4096
  23. #define IOPFNSHIFT 12 /* 4K per mapped page */
  24. #else
  25. #define IOPFNSHIFT 14 /* 16K per mapped page */
  26. #endif /* _PAGESZ */
  28. #define IOPGSIZE (1 << IOPFNSHIFT)
  29. #define IOPG(x) ((x) >> IOPFNSHIFT)
  30. #define IOPGOFF(x) ((x) & (IOPGSIZE-1))
  32. /* Bridge RAM sizes */
  34. #define BRIDGE_INTERNAL_ATES 128
  35. #define XBRIDGE_INTERNAL_ATES 1024
  37. #define BRIDGE_ATE_RAM_SIZE     (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */
  38. #define XBRIDGE_ATE_RAM_SIZE    (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */
  40. #define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */
  41. /* map to each device's */
  42. /* config space */
  43. #define BRIDGE_CONFIG1_BASE 0x28000 /* type 1 device config space */
  44. #define BRIDGE_CONFIG_END 0x30000
  45. #define BRIDGE_CONFIG_SLOT_SIZE 0x1000 /* each map == 4k */
  47. #define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
  48. #define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
  49. #define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
  50. #define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
  52. /* ========================================================================
  53.  *    Bridge address map
  54.  */
  56. #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
  58. #ifdef __cplusplus
  59. extern "C" {
  60. #endif
  62. /*
  63.  * All accesses to bridge hardware registers must be done
  64.  * using 32-bit loads and stores.
  65.  */
  66. typedef uint32_t bridgereg_t;
  68. typedef uint64_t bridge_ate_t;
  70. /* pointers to bridge ATEs
  71.  * are always "pointer to volatile"
  72.  */
  73. typedef volatile bridge_ate_t  *bridge_ate_p;
  75. /*
  76.  * It is generally preferred that hardware registers on the bridge
  77.  * are located from C code via this structure.
  78.  *
  79.  * Generated from Bridge spec dated 04oct95
  80.  */
  82. #ifdef LITTLE_ENDIAN
  84. typedef volatile struct bridge_s {
  86.     /* Local Registers        0x000000-0x00FFFF */
  88.     /* standard widget configuration        0x000000-0x000057 */
  89.     widget_cfg_t     b_widget;     /* 0x000000 */
  91.     /* helper fieldnames for accessing bridge widget */
  93. #define b_wid_id b_widget.w_id
  94. #define b_wid_stat b_widget.w_status
  95. #define b_wid_err_upper b_widget.w_err_upper_addr
  96. #define b_wid_err_lower b_widget.w_err_lower_addr
  97. #define b_wid_control b_widget.w_control
  98. #define b_wid_req_timeout b_widget.w_req_timeout
  99. #define b_wid_int_upper b_widget.w_intdest_upper_addr
  100. #define b_wid_int_lower b_widget.w_intdest_lower_addr
  101. #define b_wid_err_cmdword b_widget.w_err_cmd_word
  102. #define b_wid_llp b_widget.w_llp_cfg
  103. #define b_wid_tflush b_widget.w_tflush
  105.     /*
  106.      * we access these through synergy unswizzled space, so the address
  107.      * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
  108.      * That's why we put the register first and filler second.
  109.      */
  110.     /* bridge-specific widget configuration        0x000058-0x00007F */
  111.     bridgereg_t             b_wid_aux_err;          /* 0x00005C */
  112.     bridgereg_t     _pad_000058;
  114.     bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
  115.     bridgereg_t             _pad_000060;
  117.     bridgereg_t             b_wid_resp_lower;       /* 0x00006C */
  118.     bridgereg_t             _pad_000068;
  120.     bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
  121.     bridgereg_t             _pad_000070;
  123.     bridgereg_t     _pad_000078[2];
  125.     /* PMU & Map        0x000080-0x00008F */
  126.     bridgereg_t             b_dir_map;              /* 0x000084 */
  127.     bridgereg_t             _pad_000080;
  128.     bridgereg_t     _pad_000088[2];
  130.     /* SSRAM        0x000090-0x00009F */
  131.     bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
  132.     bridgereg_t             _pad_000090;
  133. #define b_ram_perr  b_ram_perr_or_map_fault /* Bridge */
  134. #define b_map_fault b_ram_perr_or_map_fault /* Xbridge */
  135.     bridgereg_t     _pad_000098[2];
  137.     /* Arbitration        0x0000A0-0x0000AF */
  138.     bridgereg_t             b_arb;                  /* 0x0000A4 */
  139.     bridgereg_t             _pad_0000A0;
  140.     bridgereg_t     _pad_0000A8[2];
  142.     /* Number In A Can        0x0000B0-0x0000BF */
  143.     bridgereg_t             b_nic;                  /* 0x0000B4 */
  144.     bridgereg_t             _pad_0000B0;
  145.     bridgereg_t     _pad_0000B8[2];
  147.     /* PCI/GIO        0x0000C0-0x0000FF */
  148.     bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
  149.     bridgereg_t             _pad_0000C0;
  150. #define b_pci_bus_timeout b_bus_timeout
  152.     bridgereg_t             b_pci_cfg;              /* 0x0000CC */
  153.     bridgereg_t             _pad_0000C8;
  155.     bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
  156.     bridgereg_t             _pad_0000D0;
  158.     bridgereg_t             b_pci_err_lower;        /* 0x0000DC */
  159.     bridgereg_t             _pad_0000D8;
  160.     bridgereg_t     _pad_0000E0[8];
  161. #define b_gio_err_lower b_pci_err_lower
  162. #define b_gio_err_upper b_pci_err_upper
  164.     /* Interrupt        0x000100-0x0001FF */
  165.     bridgereg_t             b_int_status;           /* 0x000104 */
  166.     bridgereg_t             _pad_000100;
  168.     bridgereg_t             b_int_enable;           /* 0x00010C */
  169.     bridgereg_t             _pad_000108;
  171.     bridgereg_t             b_int_rst_stat;         /* 0x000114 */
  172.     bridgereg_t             _pad_000110;
  174.     bridgereg_t             b_int_mode;             /* 0x00011C */
  175.     bridgereg_t             _pad_000118;
  177.     bridgereg_t             b_int_device;           /* 0x000124 */
  178.     bridgereg_t             _pad_000120;
  180.     bridgereg_t             b_int_host_err;         /* 0x00012C */
  181.     bridgereg_t             _pad_000128;
  183.     struct {
  184.         bridgereg_t             addr;               /* 0x0001{34,,,6C} */
  185.         bridgereg_t             __pad;              /* 0x0001{30,,,68} */
  186.     } b_int_addr[8];     /* 0x000130 */
  188.     bridgereg_t             b_err_int_view;         /* 0x000174 */
  189.     bridgereg_t             _pad_000170;
  191.     bridgereg_t             b_mult_int;             /* 0x00017c */
  192.     bridgereg_t             _pad_000178;
  194.     struct {
  195.         bridgereg_t             intr;               /* 0x0001{84,,,BC} */
  196.         bridgereg_t             __pad;              /* 0x0001{80,,,B8} */
  197.     } b_force_always[8];     /* 0x000180 */
  199.     struct {
  200.         bridgereg_t             intr;               /* 0x0001{C4,,,FC} */
  201.         bridgereg_t             __pad;              /* 0x0001{C0,,,F8} */
  202.     } b_force_pin[8];          /* 0x0001C0 */
  204.     /* Device        0x000200-0x0003FF */
  205.     struct {
  206.         bridgereg_t             reg;                /* 0x0002{04,,,3C} */
  207.         bridgereg_t             __pad;              /* 0x0002{00,,,38} */
  208.     } b_device[8];     /* 0x000200 */
  210.     struct {
  211.         bridgereg_t             reg;                /* 0x0002{44,,,7C} */
  212.         bridgereg_t             __pad;              /* 0x0002{40,,,78} */
  213.     } b_wr_req_buf[8];     /* 0x000240 */
  215.     struct {
  216.         bridgereg_t             reg;                /* 0x0002{84,,,8C} */
  217.         bridgereg_t             __pad;              /* 0x0002{80,,,88} */
  218.     } b_rrb_map[2];     /* 0x000280 */
  219. #define b_even_resp b_rrb_map[0].reg     /* 0x000284 */
  220. #define b_odd_resp b_rrb_map[1].reg     /* 0x00028C */
  222.     bridgereg_t             b_resp_status;          /* 0x000294 */
  223.     bridgereg_t             _pad_000290;
  225.     bridgereg_t             b_resp_clear;           /* 0x00029C */
  226.     bridgereg_t             _pad_000298;
  228.     bridgereg_t     _pad_0002A0[24];
  230.     /* Xbridge only */
  231.     struct {
  232. bridgereg_t         upper;              /* 0x0003{04,,,F4} */
  233. bridgereg_t             __pad1;     /* 0x0003{00,,,F0} */
  234. bridgereg_t             lower;              /* 0x0003{0C,,,FC} */
  235. bridgereg_t             __pad2;             /* 0x0003{08,,,F8} */
  236.     } b_buf_addr_match[16];
  238.     /* Performance Monitor Registers (even only) */
  239.     struct {
  240.         bridgereg_t             flush_w_touch;      /* 0x000404,,,5C4 */
  241.         bridgereg_t             __pad1;             /* 0x000400,,,5C0 */
  243.         bridgereg_t             flush_wo_touch;     /* 0x00040C,,,5CC */
  244.         bridgereg_t             __pad2;             /* 0x000408,,,5C8 */
  246.         bridgereg_t             inflight;           /* 0x000414,,,5D4 */
  247.         bridgereg_t             __pad3;             /* 0x000410,,,5D0 */
  249.         bridgereg_t             prefetch;           /* 0x00041C,,,5DC */
  250.         bridgereg_t             __pad4;             /* 0x000418,,,5D8 */
  252.         bridgereg_t             total_pci_retry;    /* 0x000424,,,5E4 */
  253.         bridgereg_t             __pad5;             /* 0x000420,,,5E0 */
  255.         bridgereg_t             max_pci_retry;      /* 0x00042C,,,5EC */
  256.         bridgereg_t             __pad6;             /* 0x000428,,,5E8 */
  258.         bridgereg_t             max_latency;        /* 0x000434,,,5F4 */
  259.         bridgereg_t             __pad7;             /* 0x000430,,,5F0 */
  261.         bridgereg_t             clear_all;          /* 0x00043C,,,5FC */
  262.         bridgereg_t             __pad8;             /* 0x000438,,,5F8 */
  263.     } b_buf_count[8];
  265.     char                    _pad_000600[0x010000 - 0x000600];
  267.     /*
  268.      * The Xbridge has 1024 internal ATE's and the Bridge has 128.
  269.      * Make enough room for the Xbridge ATE's and depend on runtime
  270.      * checks to limit access to bridge ATE's.
  271.      */
  273.     /* Internal Address Translation Entry RAM        0x010000-0x011fff */
  274.     union {
  275. bridge_ate_t wr; /* write-only */
  276. struct {
  277.     bridgereg_t             rd;         /* read-only */
  278.             bridgereg_t             _p_pad;
  279. } hi;
  280.     }     b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
  282. #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
  284.     /* the xbridge read path for internal ates starts at 0x12000.
  285.      * I don't believe we ever try to read the ates.
  286.      */
  287.     /* Internal Address Translation Entry RAM LOW       0x012000-0x013fff */
  288.     struct {
  289. bridgereg_t             rd; 
  290.         bridgereg_t             _p_pad;
  291.     }     xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
  293.     char     _pad_014000[0x20000 - 0x014000];
  295.     /* PCI Device Configuration Spaces        0x020000-0x027FFF */
  296.     union { /* make all access sizes available. */
  297. uchar_t c[0x1000 / 1];
  298. uint16_t s[0x1000 / 2];
  299. uint32_t l[0x1000 / 4];
  300. uint64_t d[0x1000 / 8];
  301. union {
  302.     uchar_t c[0x100 / 1];
  303.     uint16_t s[0x100 / 2];
  304.     uint32_t l[0x100 / 4];
  305.     uint64_t d[0x100 / 8];
  306. } f[8];
  307.     } b_type0_cfg_dev[8];     /* 0x020000 */
  309.     /* PCI Type 1 Configuration Space        0x028000-0x028FFF */
  310.     union { /* make all access sizes available. */
  311. uchar_t c[0x1000 / 1];
  312. uint16_t s[0x1000 / 2];
  313. uint32_t l[0x1000 / 4];
  314. uint64_t d[0x1000 / 8];
  315.     } b_type1_cfg;     /* 0x028000-0x029000 */
  317.     char     _pad_029000[0x007000];  /* 0x029000-0x030000 */
  319.     /* PCI Interrupt Acknowledge Cycle        0x030000 */
  320.     union {
  321. uchar_t c[8 / 1];
  322. uint16_t s[8 / 2];
  323. uint32_t l[8 / 4];
  324. uint64_t d[8 / 8];
  325.     } b_pci_iack;     /* 0x030000 */
  327.     uchar_t     _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */
  329.     /* External Address Translation Entry RAM        0x080000-0x0FFFFF */
  330.     bridge_ate_t     b_ext_ate_ram[0x10000];
  332.     /* Reserved        0x100000-0x1FFFFF */
  333.     char     _pad_100000[0x200000-0x100000];
  335.     /* PCI/GIO Device Spaces        0x200000-0xBFFFFF */
  336.     union { /* make all access sizes available. */
  337. uchar_t c[0x100000 / 1];
  338. uint16_t s[0x100000 / 2];
  339. uint32_t l[0x100000 / 4];
  340. uint64_t d[0x100000 / 8];
  341.     } b_devio_raw[10]; /* 0x200000 */
  343.     /* b_devio macro is a bit strange; it reflects the
  344.      * fact that the Bridge ASIC provides 2M for the
  345.      * first two DevIO windows and 1M for the other six.
  346.      */
  347. #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
  349.     /* External Flash Proms 1,0        0xC00000-0xFFFFFF */
  350.     union { /* make all access sizes available. */
  351. uchar_t c[0x400000 / 1]; /* read-only */
  352. uint16_t s[0x400000 / 2]; /* read-write */
  353. uint32_t l[0x400000 / 4]; /* read-only */
  354. uint64_t d[0x400000 / 8]; /* read-only */
  355.     } b_external_flash; /* 0xC00000 */
  356. } bridge_t;
  358. #else
  360. /*
  361.  * Field formats for Error Command Word and Auxillary Error Command Word
  362.  * of bridge.
  363.  */
  364. typedef struct bridge_err_cmdword_s {
  365.     union {
  366. uint32_t cmd_word;
  367. struct {
  368.     uint32_t     didn:4, /* Destination ID */
  369.     sidn:4, /* SOurce ID   */
  370.     pactyp:4, /* Packet type   */
  371.     tnum:5, /* Trans Number   */
  372.     coh:1, /* Coh Transacti  */
  373.     ds:2, /* Data size   */
  374.     gbr:1, /* GBR enable   */
  375.     vbpm:1, /* VBPM message   */
  376.     error:1, /* Error occurred  */
  377.     barr:1, /* Barrier op   */
  378.     rsvd:8;
  379. } berr_st;
  380.     } berr_un;
  381. } bridge_err_cmdword_t;
  383. typedef volatile struct bridge_s {
  385.     /* Local Registers                                 0x000000-0x00FFFF */
  387.     /* standard widget configuration                   0x000000-0x000057 */
  388.     widget_cfg_t            b_widget;               /* 0x000000 */
  390.     /* helper fieldnames for accessing bridge widget */
  392. #define b_wid_id                        b_widget.w_id
  393. #define b_wid_stat                      b_widget.w_status
  394. #define b_wid_err_upper                 b_widget.w_err_upper_addr
  395. #define b_wid_err_lower                 b_widget.w_err_lower_addr
  396. #define b_wid_control                   b_widget.w_control
  397. #define b_wid_req_timeout               b_widget.w_req_timeout
  398. #define b_wid_int_upper                 b_widget.w_intdest_upper_addr
  399. #define b_wid_int_lower                 b_widget.w_intdest_lower_addr
  400. #define b_wid_err_cmdword               b_widget.w_err_cmd_word
  401. #define b_wid_llp                       b_widget.w_llp_cfg
  402. #define b_wid_tflush                    b_widget.w_tflush
  404.     /* bridge-specific widget configuration            0x000058-0x00007F */
  405.     bridgereg_t             _pad_000058;
  406.     bridgereg_t             b_wid_aux_err;          /* 0x00005C */
  407.     bridgereg_t             _pad_000060;
  408.     bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
  409.     bridgereg_t             _pad_000068;
  410.     bridgereg_t             b_wid_resp_lower;       /* 0x00006C */
  411.     bridgereg_t             _pad_000070;
  412.     bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
  413.     bridgereg_t             _pad_000078[2];
  415.     /* PMU & Map                                       0x000080-0x00008F */
  416.     bridgereg_t             _pad_000080;
  417.     bridgereg_t             b_dir_map;              /* 0x000084 */
  418.     bridgereg_t             _pad_000088[2];
  420.     /* SSRAM                                           0x000090-0x00009F */
  421.     bridgereg_t             _pad_000090;
  422.     bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
  423. #define b_ram_perr  b_ram_perr_or_map_fault     /* Bridge */
  424. #define b_map_fault b_ram_perr_or_map_fault     /* Xbridge */
  425.     bridgereg_t             _pad_000098[2];
  427.     /* Arbitration                                     0x0000A0-0x0000AF */
  428.     bridgereg_t             _pad_0000A0;
  429.     bridgereg_t             b_arb;                  /* 0x0000A4 */
  430.     bridgereg_t             _pad_0000A8[2];
  432.     /* Number In A Can                                 0x0000B0-0x0000BF */
  433.     bridgereg_t             _pad_0000B0;
  434.     bridgereg_t             b_nic;                  /* 0x0000B4 */
  435.     bridgereg_t             _pad_0000B8[2];
  437.     /* PCI/GIO                                         0x0000C0-0x0000FF */
  438.     bridgereg_t             _pad_0000C0;
  439.     bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
  440. #define b_pci_bus_timeout b_bus_timeout
  442.     bridgereg_t             _pad_0000C8;
  443.     bridgereg_t             b_pci_cfg;              /* 0x0000CC */
  444.     bridgereg_t             _pad_0000D0;
  445.     bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
  446.     bridgereg_t             _pad_0000D8;
  447.     bridgereg_t             b_pci_err_lower;        /* 0x0000DC */
  448.     bridgereg_t             _pad_0000E0[8];
  449. #define b_gio_err_lower b_pci_err_lower
  450. #define b_gio_err_upper b_pci_err_upper
  452.     /* Interrupt                                       0x000100-0x0001FF */
  453.     bridgereg_t             _pad_000100;
  454.     bridgereg_t             b_int_status;           /* 0x000104 */
  455.     bridgereg_t             _pad_000108;
  456.     bridgereg_t             b_int_enable;           /* 0x00010C */
  457.     bridgereg_t             _pad_000110;
  458.     bridgereg_t             b_int_rst_stat;         /* 0x000114 */
  459.     bridgereg_t             _pad_000118;
  460.     bridgereg_t             b_int_mode;             /* 0x00011C */
  461.     bridgereg_t             _pad_000120;
  462.     bridgereg_t             b_int_device;           /* 0x000124 */
  463.     bridgereg_t             _pad_000128;
  464.     bridgereg_t             b_int_host_err;         /* 0x00012C */
  466.     struct {
  467.         bridgereg_t             __pad;              /* 0x0001{30,,,68} */
  468.         bridgereg_t             addr;               /* 0x0001{34,,,6C} */
  469.     } b_int_addr[8];                                /* 0x000130 */
  471.     bridgereg_t             _pad_000170;
  472.     bridgereg_t             b_err_int_view;         /* 0x000174 */
  473.     bridgereg_t             _pad_000178;
  474.     bridgereg_t             b_mult_int;             /* 0x00017c */
  476.     struct {
  477.         bridgereg_t             __pad;              /* 0x0001{80,,,B8} */
  478.         bridgereg_t             intr;               /* 0x0001{84,,,BC} */
  479.     } b_force_always[8];                            /* 0x000180 */
  481.     struct {
  482.         bridgereg_t             __pad;              /* 0x0001{C0,,,F8} */
  483.         bridgereg_t             intr;               /* 0x0001{C4,,,FC} */
  484.     } b_force_pin[8];                               /* 0x0001C0 */
  486.     /* Device                                          0x000200-0x0003FF */
  487.     struct {
  488.         bridgereg_t             __pad;              /* 0x0002{00,,,38} */
  489.         bridgereg_t             reg;                /* 0x0002{04,,,3C} */
  490.     } b_device[8];                                  /* 0x000200 */
  492.     struct {
  493.         bridgereg_t             __pad;              /* 0x0002{40,,,78} */
  494.         bridgereg_t             reg;                /* 0x0002{44,,,7C} */
  495.     } b_wr_req_buf[8];                              /* 0x000240 */
  497.     struct {
  498.         bridgereg_t             __pad;              /* 0x0002{80,,,88} */
  499.         bridgereg_t             reg;                /* 0x0002{84,,,8C} */
  500.     } b_rrb_map[2];                                 /* 0x000280 */
  501. #define b_even_resp     b_rrb_map[0].reg            /* 0x000284 */
  502. #define b_odd_resp      b_rrb_map[1].reg            /* 0x00028C */
  504.     bridgereg_t             _pad_000290;
  505.     bridgereg_t             b_resp_status;          /* 0x000294 */
  506.     bridgereg_t             _pad_000298;
  507.     bridgereg_t             b_resp_clear;           /* 0x00029C */
  509.     bridgereg_t             _pad_0002A0[24];
  511.     /* Xbridge only */
  512.     struct {
  513.         bridgereg_t             __pad1;             /* 0x0003{00,,,F0} */
  514.         bridgereg_t             upper;              /* 0x0003{04,,,F4} */
  515.         bridgereg_t             __pad2;             /* 0x0003{08,,,F8} */
  516.         bridgereg_t             lower;              /* 0x0003{0C,,,FC} */
  517.     } b_buf_addr_match[16];
  519.     /* Performance Monitor Registers (even only) */
  520.     struct {
  521.         bridgereg_t             __pad1;             /* 0x000400,,,5C0 */
  522.         bridgereg_t             flush_w_touch;      /* 0x000404,,,5C4 */
  523.         bridgereg_t             __pad2;             /* 0x000408,,,5C8 */
  524.         bridgereg_t             flush_wo_touch;     /* 0x00040C,,,5CC */
  525.         bridgereg_t             __pad3;             /* 0x000410,,,5D0 */
  526.         bridgereg_t             inflight;           /* 0x000414,,,5D4 */
  527.         bridgereg_t             __pad4;             /* 0x000418,,,5D8 */
  528.         bridgereg_t             prefetch;           /* 0x00041C,,,5DC */
  529.         bridgereg_t             __pad5;             /* 0x000420,,,5E0 */
  530.         bridgereg_t             total_pci_retry;    /* 0x000424,,,5E4 */
  531.         bridgereg_t             __pad6;             /* 0x000428,,,5E8 */
  532.         bridgereg_t             max_pci_retry;      /* 0x00042C,,,5EC */
  533.         bridgereg_t             __pad7;             /* 0x000430,,,5F0 */
  534.         bridgereg_t             max_latency;        /* 0x000434,,,5F4 */
  535.         bridgereg_t             __pad8;             /* 0x000438,,,5F8 */
  536.         bridgereg_t             clear_all;          /* 0x00043C,,,5FC */
  537.     } b_buf_count[8];
  539.     char                    _pad_000600[0x010000 - 0x000600];
  541.     /*
  542.      * The Xbridge has 1024 internal ATE's and the Bridge has 128.
  543.      * Make enough room for the Xbridge ATE's and depend on runtime
  544.      * checks to limit access to bridge ATE's.
  545.      */
  547.     /* Internal Address Translation Entry RAM          0x010000-0x011fff */
  548.     union {
  549.         bridge_ate_t            wr;             /* write-only */
  550.         struct {
  551.             bridgereg_t             _p_pad;
  552.             bridgereg_t             rd;         /* read-only */
  553.         }                       hi;
  554.     }                       b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
  556. #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
  558.     /* the xbridge read path for internal ates starts at 0x12000.
  559.      * I don't believe we ever try to read the ates.
  560.      */
  561.     /* Internal Address Translation Entry RAM LOW       0x012000-0x013fff */
  562.     struct {
  563.         bridgereg_t             _p_pad;
  564.         bridgereg_t             rd;             /* read-only */
  565.     }                       xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
  567.     char                    _pad_014000[0x20000 - 0x014000];
  569.     /* PCI Device Configuration Spaces                 0x020000-0x027FFF */
  570.     union {                             /* make all access sizes available. */
  571.         uchar_t                 c[0x1000 / 1];
  572.         uint16_t                s[0x1000 / 2];
  573.         uint32_t              l[0x1000 / 4];
  574.         uint64_t              d[0x1000 / 8];
  575.         union {
  576.             uchar_t             c[0x100 / 1];
  577.             uint16_t            s[0x100 / 2];
  578.             uint32_t          l[0x100 / 4];
  579.             uint64_t          d[0x100 / 8];
  580.         }                       f[8];
  581.     } b_type0_cfg_dev[8];                           /* 0x020000 */
  584.     /* PCI Type 1 Configuration Space                  0x028000-0x028FFF */
  585.     union {                             /* make all access sizes available. */
  586.         uchar_t                 c[0x1000 / 1];
  587.         uint16_t                s[0x1000 / 2];
  588.         uint32_t              l[0x1000 / 4];
  589.         uint64_t              d[0x1000 / 8];
  590.     } b_type1_cfg;                                  /* 0x028000-0x029000 */
  592.     char                    _pad_029000[0x007000];  /* 0x029000-0x030000 */
  594.     /* PCI Interrupt Acknowledge Cycle                 0x030000 */
  595.     union {
  596.         uchar_t                 c[8 / 1];
  597.         uint16_t                s[8 / 2];
  598.         uint32_t              l[8 / 4];
  599.         uint64_t              d[8 / 8];
  600.     } b_pci_iack;                                   /* 0x030000 */
  602.     uchar_t                 _pad_030007[0x04fff8];  /* 0x030008-0x07FFFF */
  604.     /* External Address Translation Entry RAM          0x080000-0x0FFFFF */
  605.     bridge_ate_t            b_ext_ate_ram[0x10000];
  607.     /* Reserved                                        0x100000-0x1FFFFF */
  608.     char                    _pad_100000[0x200000-0x100000];
  610.     /* PCI/GIO Device Spaces                           0x200000-0xBFFFFF */
  611.     union {                             /* make all access sizes available. */
  612.         uchar_t                 c[0x100000 / 1];
  613.         uint16_t                s[0x100000 / 2];
  614.         uint32_t              l[0x100000 / 4];
  615.         uint64_t              d[0x100000 / 8];
  616.     } b_devio_raw[10];                  /* 0x200000 */
  618.     /* b_devio macro is a bit strange; it reflects the
  619.      * fact that the Bridge ASIC provides 2M for the
  620.      * first two DevIO windows and 1M for the other six.
  621.      */
  622. #define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
  624.     /* External Flash Proms 1,0                        0xC00000-0xFFFFFF */
  625.     union {                             /* make all access sizes available. */
  626.         uchar_t                 c[0x400000 / 1];        /* read-only */
  627.         uint16_t                s[0x400000 / 2];        /* read-write */
  628.         uint32_t              l[0x400000 / 4];        /* read-only */
  629.         uint64_t              d[0x400000 / 8];        /* read-only */
  630.     } b_external_flash;                 /* 0xC00000 */
  631. } bridge_t;
  633. #endif
  640. #define berr_field berr_un.berr_st
  641. #endif /* LANGUAGE_C */
  643. /*
  644.  * The values of these macros can and should be crosschecked
  645.  * regularly against the offsets of the like-named fields
  646.  * within the "bridge_t" structure above.
  647.  */
  649. /* Byte offset macros for Bridge internal registers */
  651. #define BRIDGE_WID_ID WIDGET_ID
  652. #define BRIDGE_WID_STAT WIDGET_STATUS
  653. #define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
  654. #define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
  655. #define BRIDGE_WID_CONTROL WIDGET_CONTROL
  656. #define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
  657. #define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
  658. #define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
  659. #define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
  660. #define BRIDGE_WID_LLP WIDGET_LLP_CFG
  661. #define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
  663. #define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */
  664. #define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */
  665. #define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */
  666. #define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */
  668. #define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */
  670. /* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */
  671. #define BRIDGE_RAM_PERR  0x000094 /* SSRAM Parity Error */
  672. #define BRIDGE_MAP_FAULT 0x000094 /* Map Fault */
  674. #define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */
  676. #define BRIDGE_NIC 0x0000B4 /* Number In A Can */
  678. #define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */
  679. #define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
  680. #define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */
  681. #define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */
  682. #define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */
  684. #define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */
  685. #define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */
  686. #define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */
  687. #define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */
  688. #define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */
  689. #define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */
  691. #define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */
  692. #define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */
  693. #define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
  695. #define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */
  696. #define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */
  698. #define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/
  699. #define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */
  700. #define BRIDGE_FORCE_ALWAYS(x)  (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF)
  702. #define BRIDGE_FORCE_PIN0 0x0001c4 /* Force an interrupt */
  703. #define BRIDGE_FORCE_PIN_OFF  0x000008 /* Force Pin offset */
  704. #define BRIDGE_FORCE_PIN(x)  (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF)
  706. #define BRIDGE_DEVICE0 0x000204 /* Device 0 */
  707. #define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */
  708. #define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
  710. #define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */
  711. #define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */
  712. #define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
  714. #define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */
  715. #define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */
  717. #define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */
  718. #define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */
  720. #define BRIDGE_BUF_ADDR_UPPER0 0x000304
  721. #define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010 /* PCI Buffer Upper Offset */
  722. #define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF)
  724. #define BRIDGE_BUF_ADDR_LOWER0 0x00030c
  725. #define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010 /* PCI Buffer Upper Offset */
  726. #define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF)
  728. /* 
  729.  * Performance Monitor Registers.
  730.  *
  731.  * The Performance registers are those registers which are associated with
  732.  * monitoring the performance of PCI generated reads to the host environ
  733.  * ment. Because of the size of the register file only the even registers
  734.  * were instrumented.
  735.  */
  737. #define BRIDGE_BUF_OFF 0x40
  738. #define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF))
  740. /*
  741.  * Buffer (x) Flush Count with Data Touch Register.
  742.  *
  743.  * This counter is incremented each time the corresponding response buffer
  744.  * is flushed after at least a single data element in the buffer is used.
  745.  * A word write to this address clears the count.
  746.  */
  748. #define BRIDGE_BUF_0_FLUSH_TOUCH  0x000404
  749. #define BRIDGE_BUF_2_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1)
  750. #define BRIDGE_BUF_4_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2)
  751. #define BRIDGE_BUF_6_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3)
  752. #define BRIDGE_BUF_8_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4)
  753. #define BRIDGE_BUF_10_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5)
  754. #define BRIDGE_BUF_12_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6)
  755. #define BRIDGE_BUF_14_FLUSH_TOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7)
  757. /*
  758.  * Buffer (x) Flush Count w/o Data Touch Register
  759.  *
  760.  * This counter is incremented each time the corresponding response buffer
  761.  * is flushed without any data element in the buffer being used. A word
  762.  * write to this address clears the count.
  763.  */
  766. #define BRIDGE_BUF_0_FLUSH_NOTOUCH  0x00040c
  767. #define BRIDGE_BUF_2_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1)
  768. #define BRIDGE_BUF_4_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2)
  769. #define BRIDGE_BUF_6_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3)
  770. #define BRIDGE_BUF_8_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4)
  771. #define BRIDGE_BUF_10_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5)
  772. #define BRIDGE_BUF_12_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6)
  773. #define BRIDGE_BUF_14_FLUSH_NOTOUCH  BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7)
  775. /*
  776.  * Buffer (x) Request in Flight Count Register
  777.  *
  778.  * This counter is incremented on each bus clock while the request is in
  779.  * flight. A word write to this address clears the count.
  780.  */
  782. #define BRIDGE_BUF_0_INFLIGHT  0x000414
  783. #define BRIDGE_BUF_2_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1)
  784. #define BRIDGE_BUF_4_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2)
  785. #define BRIDGE_BUF_6_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3)
  786. #define BRIDGE_BUF_8_INFLIGHT    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4)
  787. #define BRIDGE_BUF_10_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5)
  788. #define BRIDGE_BUF_12_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6)
  789. #define BRIDGE_BUF_14_INFLIGHT   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7)
  791. /*
  792.  * Buffer (x) Prefetch Request Count Register
  793.  *
  794.  * This counter is incremented each time the request using this buffer was
  795.  * generated from the prefetcher. A word write to this address clears the
  796.  * count.
  797.  */
  799. #define BRIDGE_BUF_0_PREFETCH  0x00041C
  800. #define BRIDGE_BUF_2_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1)
  801. #define BRIDGE_BUF_4_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2)
  802. #define BRIDGE_BUF_6_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3)
  803. #define BRIDGE_BUF_8_PREFETCH    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4)
  804. #define BRIDGE_BUF_10_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5)
  805. #define BRIDGE_BUF_12_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6)
  806. #define BRIDGE_BUF_14_PREFETCH   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7)
  808. /*
  809.  * Buffer (x) Total PCI Retry Count Register
  810.  *
  811.  * This counter is incremented each time a PCI bus retry occurs and the ad
  812.  * dress matches the tag for the selected buffer. The buffer must also has
  813.  * this request in-flight. A word write to this address clears the count.
  814.  */
  816. #define BRIDGE_BUF_0_PCI_RETRY  0x000424
  817. #define BRIDGE_BUF_2_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1)
  818. #define BRIDGE_BUF_4_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2)
  819. #define BRIDGE_BUF_6_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3)
  820. #define BRIDGE_BUF_8_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4)
  821. #define BRIDGE_BUF_10_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5)
  822. #define BRIDGE_BUF_12_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6)
  823. #define BRIDGE_BUF_14_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7)
  825. /*
  826.  * Buffer (x) Max PCI Retry Count Register
  827.  *
  828.  * This counter is contains the maximum retry count for a single request
  829.  * which was in-flight for this buffer. A word write to this address
  830.  * clears the count.
  831.  */
  833. #define BRIDGE_BUF_0_MAX_PCI_RETRY  0x00042C
  834. #define BRIDGE_BUF_2_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1)
  835. #define BRIDGE_BUF_4_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2)
  836. #define BRIDGE_BUF_6_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3)
  837. #define BRIDGE_BUF_8_MAX_PCI_RETRY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4)
  838. #define BRIDGE_BUF_10_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5)
  839. #define BRIDGE_BUF_12_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6)
  840. #define BRIDGE_BUF_14_MAX_PCI_RETRY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7)
  842. /*
  843.  * Buffer (x) Max Latency Count Register
  844.  *
  845.  * This counter is contains the maximum count (in bus clocks) for a single
  846.  * request which was in-flight for this buffer. A word write to this
  847.  * address clears the count.
  848.  */
  850. #define BRIDGE_BUF_0_MAX_LATENCY  0x000434
  851. #define BRIDGE_BUF_2_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1)
  852. #define BRIDGE_BUF_4_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2)
  853. #define BRIDGE_BUF_6_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3)
  854. #define BRIDGE_BUF_8_MAX_LATENCY    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4)
  855. #define BRIDGE_BUF_10_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5)
  856. #define BRIDGE_BUF_12_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6)
  857. #define BRIDGE_BUF_14_MAX_LATENCY   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7)
  859. /*
  860.  * Buffer (x) Clear All Register
  861.  *
  862.  * Any access to this register clears all the count values for the (x)
  863.  * registers.
  864.  */
  866. #define BRIDGE_BUF_0_CLEAR_ALL  0x00043C
  867. #define BRIDGE_BUF_2_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1)
  868. #define BRIDGE_BUF_4_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2)
  869. #define BRIDGE_BUF_6_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3)
  870. #define BRIDGE_BUF_8_CLEAR_ALL    BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4)
  871. #define BRIDGE_BUF_10_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5)
  872. #define BRIDGE_BUF_12_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6)
  873. #define BRIDGE_BUF_14_CLEAR_ALL   BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7)
  875. /* end of Performance Monitor Registers */
  877. /* Byte offset macros for Bridge I/O space */
  879. #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */
  881. #define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */
  882. #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */
  883. #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */
  884. #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+
  885.  (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
  886. #define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+
  887.  (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+
  888.  (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
  890. #define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */
  892. #define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */
  893. #define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */
  895. /* Byte offset macros for Bridge device IO spaces */
  897. #define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */
  898. #define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */
  899. #define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */
  900. #define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */
  901. #define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */
  903. #define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */
  904. #define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */
  906. #if LANGUAGE_C
  908. #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
  909. #endif /* LANGUAGE_C */
  911. #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */
  913. /* ========================================================================
  914.  *    Bridge register bit field definitions
  915.  */
  917. /* Widget part number of bridge */
  918. #define BRIDGE_WIDGET_PART_NUM 0xc002
  919. #define XBRIDGE_WIDGET_PART_NUM 0xd002
  921. /* Manufacturer of bridge */
  922. #define BRIDGE_WIDGET_MFGR_NUM 0x036
  923. #define XBRIDGE_WIDGET_MFGR_NUM 0x024
  925. /* Revision numbers for known [X]Bridge revisions */
  926. #define BRIDGE_REV_A 0x1
  927. #define BRIDGE_REV_B 0x2
  928. #define BRIDGE_REV_C 0x3
  929. #define BRIDGE_REV_D 0x4
  930. #define XBRIDGE_REV_A 0x1
  931. #define XBRIDGE_REV_B 0x2
  933. /* Part + Rev numbers allows distinction and acscending sequence */
  934. #define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A)
  935. #define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B)
  936. #define BRIDGE_PART_REV_C (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C)
  937. #define BRIDGE_PART_REV_D (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D)
  938. #define XBRIDGE_PART_REV_A (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A)
  939. #define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B)
  941. /* Bridge widget status register bits definition */
  943. #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
  944. #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
  945. #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
  946. #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
  947. #define BRIDGE_STAT_PENDING (0x1F << 0)
  949. /* Bridge widget control register bits definition */
  950. #define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
  951. #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
  952. #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
  953. #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
  954. #define BRIDGE_CTRL_RST(n) ((n) << 24)
  955. #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
  956. #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
  957. #define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
  958. #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
  959. #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
  960. #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
  961. #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
  962. #define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
  963. #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
  964. #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
  965. #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
  966. #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
  967. #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
  968. #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
  969. #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
  970. #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
  971. #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
  972. #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
  973. #define BRIDGE_CTRL_SYS_END (0x1 << 9)
  974. #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
  975. #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
  976. #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
  977. #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
  979. /* Bridge Response buffer Error Upper Register bit fields definition */
  980. #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
  981. #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
  982. #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
  983. #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
  984. #define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
  986. #define BRIDGE_RESP_ERRUPPR_BUFNUM(x)
  987. (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> 
  988. BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
  990. #define BRIDGE_RESP_ERRUPPR_DEVICE(x)
  991. (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> 
  992.  BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
  994. /* Bridge direct mapping register bits definition */
  995. #define BRIDGE_DIRMAP_W_ID_SHFT 20
  996. #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
  997. #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
  998. #define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
  999. #define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
  1000. #define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
  1002. /* Bridge Arbitration register bits definition */
  1003. #define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
  1004. #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
  1005. #define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
  1006. #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
  1007. #define BRIDGE_ARB_FREEZE_GNT (1 << 6)
  1008. #define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
  1009. #define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
  1010. #define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
  1011. #define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
  1012. #define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
  1013. #define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
  1015. /* Bridge Bus time-out register bits definition */
  1016. #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
  1017. #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
  1018. #define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
  1019. #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
  1020. #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
  1022. /* Bridge interrupt status register bits definition */
  1023. #define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */
  1024. #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */
  1025. #define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */
  1026. #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
  1027. #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
  1028. #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
  1029. #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
  1030. #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
  1031. #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
  1032. #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
  1033. #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
  1034. #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
  1035. #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
  1036. #define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
  1037. #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
  1038. #define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
  1039. #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
  1040. #define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
  1041. #define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
  1042. #define BRIDGE_ISR_PCI_SERR (0x1 << 13)
  1043. #define BRIDGE_ISR_PCI_PERR (0x1 << 12)
  1044. #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
  1045. #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
  1046. #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
  1047. #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
  1048. #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
  1049. #define BRIDGE_ISR_INT_MSK (0xff << 0)
  1050. #define BRIDGE_ISR_INT(x) (0x1 << (x))
  1052. #define BRIDGE_ISR_LINK_ERROR
  1053. (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|
  1054.  BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|
  1055.  BRIDGE_ISR_LLP_TCTY)
  1057. #define BRIDGE_ISR_PCIBUS_PIOERR
  1058. (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
  1060. #define BRIDGE_ISR_PCIBUS_ERROR
  1061. (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|
  1062.  BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|
  1063.  BRIDGE_ISR_PCI_PARITY)
  1065. #define BRIDGE_ISR_XTALK_ERROR
  1066. (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|
  1067.  BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|
  1068.  BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|
  1069.  BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|
  1070.  BRIDGE_ISR_UNEXP_RESP)
  1072. #define BRIDGE_ISR_ERRORS
  1073. (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|
  1074.  BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|
  1075.  BRIDGE_ISR_PMU_ESIZE_FAULT)
  1077. /*
  1078.  * List of Errors which are fatal and kill the sytem
  1079.  */
  1080. #define BRIDGE_ISR_ERROR_FATAL
  1081. ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|
  1082.  BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
  1084. #define BRIDGE_ISR_ERROR_DUMP
  1085. (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|
  1086.  BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
  1088. /* Bridge interrupt enable register bits definition */
  1089. #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
  1090. #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
  1091. #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
  1092. #define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
  1093. #define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
  1094. #define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
  1095. #define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
  1096. #define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
  1097. #define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
  1098. #define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
  1099. #define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
  1100. #define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
  1101. #define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
  1102. #define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
  1103. #define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
  1104. #define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
  1105. #define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
  1106. #define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
  1107. #define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
  1108. #define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
  1109. #define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
  1110. #define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
  1111. #define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
  1112. #define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
  1113. #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
  1114. #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
  1116. /* Bridge interrupt reset register bits definition */
  1117. #define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
  1118. #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
  1119. #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
  1120. #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
  1121. #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
  1122. #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
  1123. #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
  1124. #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
  1125. #define BRIDGE_IRR_ALL_CLR 0x7f
  1127. #define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | 
  1128.  BRIDGE_ISR_XREQ_FIFO_OFLOW)
  1129. #define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | 
  1130.  BRIDGE_ISR_RESP_XTLK_ERR | 
  1131.  BRIDGE_ISR_XREAD_REQ_TIMEOUT)
  1132. #define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | 
  1133.  BRIDGE_ISR_BAD_XREQ_PKT | 
  1134.  BRIDGE_ISR_REQ_XTLK_ERR | 
  1135.  BRIDGE_ISR_INVLD_ADDR)
  1136. #define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | 
  1137.  BRIDGE_ISR_LLP_REC_CBERR | 
  1138.  BRIDGE_ISR_LLP_RCTY | 
  1139.  BRIDGE_ISR_LLP_TX_RETRY | 
  1140.  BRIDGE_ISR_LLP_TCTY)
  1141. #define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | 
  1142.  BRIDGE_ISR_PMU_ESIZE_FAULT)
  1143. #define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | 
  1144.  BRIDGE_ISR_PCI_PARITY | 
  1145.  BRIDGE_ISR_PCI_SERR | 
  1146.  BRIDGE_ISR_PCI_PERR | 
  1147.  BRIDGE_ISR_PCI_MST_TIMEOUT | 
  1148.  BRIDGE_ISR_PCI_RETRY_CNT)
  1150. #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | 
  1151.  BRIDGE_ISR_GIO_MST_TIMEOUT)
  1153. /* Bridge INT_DEV register bits definition */
  1154. #define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
  1155. #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
  1156. #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
  1158. /* Bridge interrupt(x) register bits definition */
  1159. #define BRIDGE_INT_ADDR_HOST 0x0003FF00
  1160. #define BRIDGE_INT_ADDR_FLD 0x000000FF
  1162. #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
  1163. #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
  1164. #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
  1166. #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
  1168. #ifdef SN0
  1169. /*
  1170.  * The NASID should be shifted by this amount and stored into the
  1171.  * interrupt(x) register.
  1172.  */
  1173. #define BRIDGE_INT_ADDR_NASID_SHFT 8
  1175. /*
  1176.  * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
  1177.  * memory.
  1178.  */
  1179. #define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
  1180. #define BRIDGE_INT_ADDR_DEST_MEM 0
  1181. #define BRIDGE_INT_ADDR_MASK (1 << 17)
  1182. #endif
  1184. /* Bridge device(x) register bits definition */
  1185. #define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28)
  1186. #define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27)
  1187. #define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26)
  1188. #define BRIDGE_DEV_VIRTUAL_EN (1ull << 25)
  1189. #define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24)
  1190. #define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23)
  1191. #define BRIDGE_DEV_DEV_SIZE (1ull << 22)
  1192. #define BRIDGE_DEV_RT (1ull << 21)
  1193. #define BRIDGE_DEV_SWAP_PMU (1ull << 20)
  1194. #define BRIDGE_DEV_SWAP_DIR (1ull << 19)
  1195. #define BRIDGE_DEV_PREF (1ull << 18)
  1196. #define BRIDGE_DEV_PRECISE (1ull << 17)
  1197. #define BRIDGE_DEV_COH (1ull << 16)
  1198. #define BRIDGE_DEV_BARRIER (1ull << 15)
  1199. #define BRIDGE_DEV_GBR (1ull << 14)
  1200. #define BRIDGE_DEV_DEV_SWAP (1ull << 13)
  1201. #define BRIDGE_DEV_DEV_IO_MEM (1ull << 12)
  1202. #define BRIDGE_DEV_OFF_MASK 0x00000fff
  1203. #define BRIDGE_DEV_OFF_ADDR_SHFT 20
  1205. #define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN
  1206. #define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | 
  1207.  BRIDGE_DEV_SWAP_PMU)
  1208. #define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | 
  1209.  BRIDGE_DEV_SWAP_DIR | 
  1210.  BRIDGE_DEV_PREF | 
  1211.  BRIDGE_DEV_PRECISE | 
  1212.  BRIDGE_DEV_COH | 
  1213.  BRIDGE_DEV_BARRIER)
  1214. #define XBRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | 
  1215.  BRIDGE_DEV_COH | 
  1216.  BRIDGE_DEV_BARRIER)
  1217. #define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | 
  1218.  BRIDGE_DEV_SWAP_DIR | 
  1219.  BRIDGE_DEV_COH | 
  1220.  BRIDGE_DEV_BARRIER)
  1222. /* Bridge Error Upper register bit field definition */
  1223. #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */
  1224. #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */
  1225. #define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
  1226. #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
  1227. #define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
  1228. #define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
  1230. /* Bridge interrupt mode register bits definition */
  1231. #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
  1233. /* this should be written to the xbow's link_control(x) register */
  1234. #define BRIDGE_CREDIT 3
  1236. /* RRB assignment register */
  1237. #define BRIDGE_RRB_EN 0x8 /* after shifting down */
  1238. #define BRIDGE_RRB_DEV 0x7 /* after shifting down */
  1239. #define BRIDGE_RRB_VDEV 0x4 /* after shifting down */
  1240. #define BRIDGE_RRB_PDEV 0x3 /* after shifting down */
  1242. /* RRB status register */
  1243. #define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
  1244. #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
  1246. /* RRB clear register */
  1247. #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
  1249. /* xbox system controller declarations */
  1250. #define XBOX_BRIDGE_WID         8
  1251. #define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
  1252. #define XBOX_RPS_EXISTS 1 << 6  /* RPS bit in status register */
  1253. #define XBOX_RPS_FAIL 1 << 4  /* RPS status bit in register */
  1255. /* ========================================================================
  1256.  */
  1257. /*
  1258.  * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
  1259.  * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
  1260.  */
  1261. /* XTALK addresses that map into Bridge Bus addr space */
  1262. #define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
  1263. #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
  1264. #define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
  1265. #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
  1266. #define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
  1267. #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
  1269. /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
  1270. #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */
  1271. #define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
  1272. #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */
  1273. #define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
  1275. /* XTALK addresses that map into PCI addresses */
  1276. #define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
  1277. #define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
  1278. #define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
  1279. #define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
  1280. #define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
  1281. #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
  1283. /*
  1284.  * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
  1285.  */
  1286. /* Bridge Bus DMA addresses */
  1287. #define BRIDGE_LOCAL_BASE 0
  1288. #define BRIDGE_DMA_MAPPED_BASE 0x40000000
  1289. #define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */
  1290. #define BRIDGE_DMA_DIRECT_BASE 0x80000000
  1291. #define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */
  1293. #define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
  1295. /* PCI addresses of regions decoded by Bridge for DMA */
  1296. #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
  1297. #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
  1299. #if LANGUAGE_C
  1301. #define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE)
  1302. #define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && 
  1303. (uint64_t)(x) >= PCI32_MAPPED_BASE)
  1304. #define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE)
  1305. #define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE)
  1306. #endif /* LANGUAGE_C */
  1308. /*
  1309.  * The GIO address space.
  1310.  */
  1311. /* Xtalk to GIO PIO */
  1312. #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
  1313. #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
  1315. #define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
  1317. /* GIO addresses of regions decoded by Bridge for DMA */
  1318. #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
  1319. #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
  1321. #if LANGUAGE_C
  1323. #define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE)
  1324. #define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && 
  1325. (uint64_t)(x) >= GIO_MAPPED_BASE)
  1326. #define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE)
  1327. #endif /* LANGUAGE_C */
  1329. /* PCI to xtalk mapping */
  1331. /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
  1332.  * which xtalk address is accessed
  1333.  */
  1334. #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
  1335. #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)
  1336. ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +
  1337. ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
  1339. /* 64-bit address attribute masks */
  1340. #define PCI64_ATTR_TARG_MASK 0xf000000000000000
  1341. #define PCI64_ATTR_TARG_SHFT 60
  1342. #define PCI64_ATTR_PREF (1ull << 59)
  1343. #define PCI64_ATTR_PREC (1ull << 58)
  1344. #define PCI64_ATTR_VIRTUAL (1ull << 57)
  1345. #define PCI64_ATTR_BAR (1ull << 56)
  1346. #define PCI64_ATTR_SWAP (1ull << 55)
  1347. #define PCI64_ATTR_RMF_MASK 0x00ff000000000000
  1348. #define PCI64_ATTR_RMF_SHFT 48
  1350. #if LANGUAGE_C
  1351. /* Address translation entry for mapped pci32 accesses */
  1352. typedef union ate_u {
  1353.     uint64_t     ent;
  1354.     struct xb_ate_s { /* xbridge */
  1355. uint64_t :16;
  1356. uint64_t addr:36;
  1357. uint64_t targ:4;
  1358. uint64_t reserved:2;
  1359.         uint64_t swap:1;
  1360. uint64_t barrier:1;
  1361. uint64_t prefetch:1;
  1362. uint64_t precise:1;
  1363. uint64_t coherent:1;
  1364. uint64_t valid:1;
  1365.     } xb_field;
  1366.     struct ate_s { /* bridge */
  1367. uint64_t rmf:16;
  1368. uint64_t addr:36;
  1369. uint64_t targ:4;
  1370. uint64_t reserved:3;
  1371. uint64_t barrier:1;
  1372. uint64_t prefetch:1;
  1373. uint64_t precise:1;
  1374. uint64_t coherent:1;
  1375. uint64_t valid:1;
  1376.     } field;
  1377. } ate_t;
  1378. #endif /* LANGUAGE_C */
  1380. #define ATE_V (1 << 0)
  1381. #define ATE_CO (1 << 1)
  1382. #define ATE_PREC (1 << 2)
  1383. #define ATE_PREF (1 << 3)
  1384. #define ATE_BAR (1 << 4)
  1385. #define ATE_SWAP        (1 << 5)
  1387. #define ATE_PFNSHIFT 12
  1388. #define ATE_TIDSHIFT 8
  1389. #define ATE_RMFSHIFT 48
  1391. #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | 
  1392. ((xid)<<ATE_TIDSHIFT) | 
  1393. (attr)
  1395. /*
  1396.  * for xbridge, bit 29 of the pci address is the swap bit */
  1397. #define ATE_SWAPSHIFT 29
  1398. #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
  1399. #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
  1401. #define is_xbridge(bridge) 
  1402.         (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM)
  1404. #if LANGUAGE_C
  1406. /* ========================================================================
  1407.  */
  1409. #ifdef MACROFIELD_LINE
  1410. /*
  1411.  * This table forms a relation between the byte offset macros normally
  1412.  * used for ASM coding and the calculated byte offsets of the fields
  1413.  * in the C structure.
  1414.  *
  1415.  * See bridge_check.c and bridge_html.c for further details.
  1416.  */
  1417. #ifndef MACROFIELD_LINE_BITFIELD
  1418. #define MACROFIELD_LINE_BITFIELD(m) /* ignored */
  1419. #endif
  1421. struct macrofield_s bridge_macrofield[] =
  1422. {
  1424.     MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id)
  1425.     MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM)
  1426.     MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM)
  1427.     MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM)
  1428.     MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat)
  1429.     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT)
  1430.     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT)
  1431.     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT)
  1432.     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N)
  1433.     MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING)
  1434.     MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper)
  1435.     MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower)
  1436.     MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control)
  1437.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN)
  1438.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50)
  1439.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40)
  1440.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33)
  1441.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK)
  1442.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP)
  1443.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP)
  1444.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE)
  1445.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD)
  1446.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN)
  1447.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK)
  1448.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT)
  1449.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK)
  1450.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT)
  1451.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT)
  1452.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END)
  1453.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK)
  1454.     MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK)
  1455.     MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout)
  1456.     MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper)
  1457.     MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR)
  1458.     MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID)
  1459.     MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR)
  1460.     MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower)
  1461.     MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword)
  1462.     MACROFIELD_LINE_BITFIELD(WIDGET_DIDN)
  1463.     MACROFIELD_LINE_BITFIELD(WIDGET_SIDN)
  1464.     MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP)
  1465.     MACROFIELD_LINE_BITFIELD(WIDGET_TNUM)
  1466.     MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT)
  1467.     MACROFIELD_LINE_BITFIELD(WIDGET_DS)
  1468.     MACROFIELD_LINE_BITFIELD(WIDGET_GBR)
  1469.     MACROFIELD_LINE_BITFIELD(WIDGET_VBPM)
  1470.     MACROFIELD_LINE_BITFIELD(WIDGET_ERROR)
  1471.     MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER)
  1472.     MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp)
  1473.     MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY)
  1474.     MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT)
  1475.     MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST)
  1476.     MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush)
  1477.     MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err)
  1478.     MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper)
  1479.     MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower)
  1480.     MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl)
  1481.     MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map)
  1482.     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID)
  1483.     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64)
  1484.     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512)
  1485.     MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF)
  1486.     MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr)
  1487.     MACROFIELD_LINE(BRIDGE_ARB, b_arb)
  1488.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK)
  1489.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK)
  1490.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT)
  1491.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2)
  1492.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1)
  1493.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0)
  1494.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2)
  1495.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1)
  1496.     MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0)
  1497.     MACROFIELD_LINE(BRIDGE_NIC, b_nic)
  1498.     MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout)
  1499.     MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg)
  1500.     MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper)
  1501.     MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower)
  1502.     MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status)
  1503.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR)
  1504.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT)
  1505.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP)
  1506.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT)
  1507.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT)
  1508.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR)
  1509.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR)
  1510.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR)
  1511.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP)
  1512.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW)
  1513.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR)
  1514.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR)
  1515.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY)
  1516.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY)
  1517.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY)
  1518.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR)
  1519.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT)
  1520.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY)
  1521.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR)
  1522.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR)
  1523.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT)
  1524.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT)
  1525.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT)
  1526.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR)
  1527.     MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK)
  1528.     MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable)
  1529.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP)
  1530.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT)
  1531.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT)
  1532.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT)
  1533.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR)
  1534.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR)
  1535.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR)
  1536.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP)
  1537.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW)
  1538.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR)
  1539.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR)
  1540.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY)
  1541.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY)
  1542.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY)
  1543.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR)
  1544.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT)
  1545.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY)
  1546.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR)
  1547.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR)
  1548.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT)
  1549.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT)
  1550.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT)
  1551.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR)
  1552.     MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK)
  1553.     MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat)
  1554.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR)
  1555.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR)
  1556.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR)
  1557.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR)
  1558.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR)
  1559.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR)
  1560.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR)
  1561.     MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR)
  1562.     MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode)
  1563.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7))
  1564.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6))
  1565.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5))
  1566.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4))
  1567.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3))
  1568.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2))
  1569.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1))
  1570.     MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0))
  1571.     MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device)
  1572.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7))
  1573.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6))
  1574.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5))
  1575.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4))
  1576.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3))
  1577.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2))
  1578.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1))
  1579.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0))
  1580.     MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err)
  1581.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST)
  1582.     MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD)
  1583.     MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr)
  1584.     MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr)
  1585.     MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr)
  1586.     MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr)
  1587.     MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr)
  1588.     MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr)
  1589.     MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr)
  1590.     MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr)
  1591.     MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr)
  1592.     MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg)
  1593.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN)
  1594.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS)
  1595.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR)
  1596.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN)
  1597.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN)
  1598.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN)
  1599.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE)
  1600.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT)
  1601.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU)
  1602.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR)
  1603.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF)
  1604.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE)
  1605.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH)
  1606.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER)
  1607.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR)
  1608.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP)
  1609.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM)
  1610.     MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK)
  1611.     MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg)
  1612.     MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg)
  1613.     MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg)
  1614.     MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg)
  1615.     MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg)
  1616.     MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg)
  1617.     MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg)
  1618.     MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg)
  1619.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg)
  1620.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg)
  1621.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg)
  1622.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg)
  1623.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg)
  1624.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg)
  1625.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg)
  1626.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg)
  1627.     MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg)
  1628.     MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp)
  1629.     MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp)
  1630.     MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status)
  1631.     MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear)
  1632.     MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram)
  1633.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0])
  1635.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0])
  1636.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0])
  1637.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1])
  1638.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2])
  1639.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3])
  1640.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4])
  1641.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5])
  1642.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6])
  1643.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7])
  1644.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1])
  1645.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0])
  1646.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1])
  1647.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2])
  1648.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3])
  1649.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4])
  1650.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5])
  1651.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6])
  1652.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7])
  1653.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2])
  1654.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0])
  1655.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1])
  1656.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2])
  1657.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3])
  1658.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4])
  1659.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5])
  1660.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6])
  1661.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7])
  1662.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3])
  1663.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0])
  1664.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1])
  1665.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2])
  1666.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3])
  1667.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4])
  1668.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5])
  1669.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6])
  1670.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7])
  1671.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4])
  1672.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0])
  1673.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1])
  1674.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2])
  1675.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3])
  1676.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4])
  1677.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5])
  1678.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6])
  1679.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7])
  1680.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5])
  1681.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0])
  1682.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1])
  1683.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2])
  1684.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3])
  1685.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4])
  1686.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5])
  1687.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6])
  1688.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7])
  1689.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6])
  1690.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0])
  1691.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1])
  1692.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2])
  1693.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3])
  1694.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4])
  1695.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5])
  1696.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6])
  1697.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7])
  1698.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7])
  1699.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0])
  1700.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1])
  1701.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2])
  1702.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3])
  1703.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4])
  1704.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5])
  1705.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6])
  1706.     MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7])
  1708.     MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg)
  1709.     MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack)
  1710.     MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram)
  1711.     MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0))
  1712.     MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0))
  1713.     MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1))
  1714.     MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2))
  1715.     MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3))
  1716.     MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4))
  1717.     MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5))
  1718.     MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6))
  1719.     MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7))
  1720.     MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash)
  1721. };
  1722. #endif
  1724. #ifdef __cplusplus
  1725. };
  1726. #endif
  1727. #endif /* C or C++ */ 
  1729. #endif                          /* _ASM_SN_PCI_BRIDGE_H */