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open_pic.c
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：23k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

open_pic.c：源码内容
  1. /*
  2.  * BK Id: SCCS/s.open_pic.c 1.33 12/19/01 09:45:54 trini
  3.  */
  4. /*
  5.  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
  6.  *
  7.  *  Copyright (C) 1997 Geert Uytterhoeven
  8.  *
  9.  *  This file is subject to the terms and conditions of the GNU General Public
  10.  *  License.  See the file COPYING in the main directory of this archive
  11.  *  for more details.
  12.  */
  14. #include <linux/config.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/sched.h>
  18. #include <linux/init.h>
  19. #include <linux/irq.h>
  20. #include <linux/init.h>
  21. #include <asm/ptrace.h>
  22. #include <asm/signal.h>
  23. #include <asm/io.h>
  24. #include <asm/irq.h>
  25. #include <asm/prom.h>
  26. #include <asm/sections.h>
  28. #include "local_irq.h"
  29. #include "open_pic.h"
  30. #include "open_pic_defs.h"
  31. #include "i8259.h"
  33. void* OpenPIC_Addr;
  34. static volatile struct OpenPIC *OpenPIC = NULL;
  35. u_int OpenPIC_NumInitSenses __initdata = 0;
  36. u_char *OpenPIC_InitSenses __initdata = NULL;
  37. extern int use_of_interrupt_tree;
  39. void find_ISUs(void);
  41. static u_int NumProcessors;
  42. static u_int NumSources;
  43. #ifdef CONFIG_POWER3
  44. static int NumISUs;
  45. #endif
  46. static int open_pic_irq_offset;
  47. static volatile unsigned char* chrp_int_ack_special;
  49. OpenPIC_SourcePtr ISU[OPENPIC_MAX_ISU];
  51. /* Global Operations */
  52. static void openpic_disable_8259_pass_through(void);
  53. static void openpic_set_priority(u_int pri);
  54. static void openpic_set_spurious(u_int vector);
  56. #ifdef CONFIG_SMP
  57. /* Interprocessor Interrupts */
  58. static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  59. static void openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs);
  60. #endif
  62. /* Timer Interrupts */
  63. static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  64. static void openpic_maptimer(u_int timer, u_int cpumask);
  66. /* Interrupt Sources */
  67. static void openpic_enable_irq(u_int irq);
  68. static void openpic_disable_irq(u_int irq);
  69. static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  70.     int is_level);
  71. static void openpic_mapirq(u_int irq, u_int cpumask);
  73. /*
  74.  * These functions are not used but the code is kept here
  75.  * for completeness and future reference.
  76.  */
  77. static void openpic_reset(void);
  78. #ifdef notused
  79. static void openpic_enable_8259_pass_through(void);
  80. static u_int openpic_get_priority(void);
  81. static u_int openpic_get_spurious(void);
  82. static void openpic_set_sense(u_int irq, int sense);
  83. #endif /* notused */
  85. /*
  86.  * Description of the openpic for the higher-level irq code
  87.  */
  88. static void openpic_end_irq(unsigned int irq_nr);
  89. static void openpic_ack_irq(unsigned int irq_nr);
  90. static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask);
  92. struct hw_interrupt_type open_pic = {
  93. " OpenPIC  ",
  94. NULL,
  95. NULL,
  96. openpic_enable_irq,
  97. openpic_disable_irq,
  98. openpic_ack_irq,
  99. openpic_end_irq,
  100. openpic_set_affinity
  101. };
  103. #ifdef CONFIG_SMP
  104. static void openpic_end_ipi(unsigned int irq_nr);
  105. static void openpic_ack_ipi(unsigned int irq_nr);
  106. static void openpic_enable_ipi(unsigned int irq_nr);
  107. static void openpic_disable_ipi(unsigned int irq_nr);
  109. struct hw_interrupt_type open_pic_ipi = {
  110. " OpenPIC  ",
  111. NULL,
  112. NULL,
  113. openpic_enable_ipi,
  114. openpic_disable_ipi,
  115. openpic_ack_ipi,
  116. openpic_end_ipi,
  117. 0
  118. };
  119. #endif /* CONFIG_SMP */
  121. /*
  122.  *  Accesses to the current processor's openpic registers
  123.  */
  124. #ifdef CONFIG_SMP
  125. #define THIS_CPU Processor[cpu]
  126. #define DECL_THIS_CPU int cpu = smp_hw_index[smp_processor_id()]
  127. #define CHECK_THIS_CPU check_arg_cpu(cpu)
  128. #else
  129. #define THIS_CPU Processor[0]
  130. #define DECL_THIS_CPU
  131. #define CHECK_THIS_CPU
  132. #endif /* CONFIG_SMP */
  134. #if 1
  135. #define check_arg_ipi(ipi) 
  136.     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) 
  137. printk("open_pic.c:%d: illegal ipi %dn", __LINE__, ipi);
  138. #define check_arg_timer(timer) 
  139.     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) 
  140. printk("open_pic.c:%d: illegal timer %dn", __LINE__, timer);
  141. #define check_arg_vec(vec) 
  142.     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) 
  143. printk("open_pic.c:%d: illegal vector %dn", __LINE__, vec);
  144. #define check_arg_pri(pri) 
  145.     if (pri < 0 || pri >= OPENPIC_NUM_PRI) 
  146. printk("open_pic.c:%d: illegal priority %dn", __LINE__, pri);
  147. /*
  148.  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
  149.  * data has probably been corrupted and we're going to panic or deadlock later
  150.  * anyway --Troy
  151.  */
  152. extern unsigned long* _get_SP(void);
  153. #define check_arg_irq(irq) 
  154.     if (irq < open_pic_irq_offset || irq >= (NumSources+open_pic_irq_offset)){ 
  155.       printk("open_pic.c:%d: illegal irq %dn", __LINE__, irq); 
  156.       print_backtrace(_get_SP()); }
  157. #define check_arg_cpu(cpu) 
  158.     if (cpu < 0 || cpu >= NumProcessors){ 
  159. printk("open_pic.c:%d: illegal cpu %dn", __LINE__, cpu); 
  160. print_backtrace(_get_SP()); }
  161. #else
  162. #define check_arg_ipi(ipi) do {} while (0)
  163. #define check_arg_timer(timer) do {} while (0)
  164. #define check_arg_vec(vec) do {} while (0)
  165. #define check_arg_pri(pri) do {} while (0)
  166. #define check_arg_irq(irq) do {} while (0)
  167. #define check_arg_cpu(cpu) do {} while (0)
  168. #endif
  170. #ifdef CONFIG_POWER3
  171. #define GET_ISU(source) ISU[(source) >> 4][(source) & 0xf]
  172. #else
  173. #define GET_ISU(source) ISU[0][(source)]
  174. #endif
  176. u_int openpic_read(volatile u_int *addr)
  177. {
  178. u_int val;
  180. val = in_le32(addr);
  181. return val;
  182. }
  184. static inline void openpic_write(volatile u_int *addr, u_int val)
  185. {
  186. out_le32(addr, val);
  187. }
  189. static inline u_int openpic_readfield(volatile u_int *addr, u_int mask)
  190. {
  191. u_int val = openpic_read(addr);
  192. return val & mask;
  193. }
  195. inline void openpic_writefield(volatile u_int *addr, u_int mask,
  196.        u_int field)
  197. {
  198. u_int val = openpic_read(addr);
  199. openpic_write(addr, (val & ~mask) | (field & mask));
  200. }
  202. static inline void openpic_clearfield(volatile u_int *addr, u_int mask)
  203. {
  204. openpic_writefield(addr, mask, 0);
  205. }
  207. static inline void openpic_setfield(volatile u_int *addr, u_int mask)
  208. {
  209. openpic_writefield(addr, mask, mask);
  210. }
  212. static void openpic_safe_writefield(volatile u_int *addr, u_int mask,
  213.     u_int field)
  214. {
  215. openpic_setfield(addr, OPENPIC_MASK);
  216. while (openpic_read(addr) & OPENPIC_ACTIVITY);
  217. openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
  218. }
  220. #ifdef CONFIG_SMP
  221. /* yes this is right ... bug, feature, you decide! -- tgall */
  222. u_int openpic_read_IPI(volatile u_int* addr)
  223. {
  224.          u_int val = 0;
  225. #ifdef CONFIG_POWER3
  226.         val = in_be32(addr);
  227. #else
  228.         val = in_le32(addr);
  229. #endif
  230.         return val;
  231. }
  233. /* because of the power3 be / le above, this is needed */
  234. inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
  235. {
  236.         u_int  val = openpic_read_IPI(addr);
  237.         openpic_write(addr, (val & ~mask) | (field & mask));
  238. }
  240. static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
  241. {
  242.         openpic_writefield_IPI(addr, mask, 0);
  243. }
  245. static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
  246. {
  247.         openpic_writefield_IPI(addr, mask, mask);
  248. }
  250. static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
  251. {
  252.         openpic_setfield_IPI(addr, OPENPIC_MASK);
  254.         /* wait until it's not in use */
  255.         /* BenH: Is this code really enough ? I would rather check the result
  256.          *       and eventually retry ...
  257.          */
  258.         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
  260.         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
  261. }
  262. #endif /* CONFIG_SMP */
  264. void __init openpic_init(int main_pic, int offset, unsigned char* chrp_ack,
  265.  int programmer_switch_irq)
  266. {
  267. u_int t, i;
  268. u_int timerfreq;
  269. const char *version;
  271. if (!OpenPIC_Addr) {
  272. printk("No OpenPIC found !n");
  273. return;
  274. }
  275. OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
  277. if ( ppc_md.progress ) ppc_md.progress("openpic enter",0x122);
  279. t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
  280. switch (t & OPENPIC_FEATURE_VERSION_MASK) {
  281. case 1:
  282. version = "1.0";
  283. break;
  284. case 2:
  285. version = "1.2";
  286. break;
  287. case 3:
  288. version = "1.3";
  289. break;
  290. default:
  291. version = "?";
  292. break;
  293. }
  294. NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
  295.  OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
  296. NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
  297.       OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1;
  298. printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %pn",
  299.        version, NumProcessors, NumSources, OpenPIC);
  300. timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
  301. if (timerfreq)
  302. printk("OpenPIC timer frequency is %d.%06d MHzn",
  303.        timerfreq / 1000000, timerfreq % 1000000);
  305. if (!main_pic)
  306. return;
  308. open_pic_irq_offset = offset;
  309. chrp_int_ack_special = (volatile unsigned char*)chrp_ack;
  311. /* Initialize timer interrupts */
  312. if ( ppc_md.progress ) ppc_md.progress("openpic timer",0x3ba);
  313. for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
  314. /* Disabled, Priority 0 */
  315. openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
  316. /* No processor */
  317. openpic_maptimer(i, 0);
  318. }
  320. #ifdef CONFIG_SMP
  321. /* Initialize IPI interrupts */
  322. if ( ppc_md.progress ) ppc_md.progress("openpic ipi",0x3bb);
  323. for (i = 0; i < OPENPIC_NUM_IPI; i++) {
  324. /* Disabled, Priority 10..13 */
  325. openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
  326. /* IPIs are per-CPU */
  327. irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
  328. irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
  329. }
  330. #endif
  332. find_ISUs();
  334. /* Initialize external interrupts */
  335. if (ppc_md.progress) ppc_md.progress("openpic ext",0x3bc);
  337. openpic_set_priority(0xf);
  339. /* SIOint (8259 cascade) is special */
  340. if (offset) {
  341. openpic_initirq(0, 8, offset, 1, 1);
  342. openpic_mapirq(0, 1<<0);
  343. }
  345. /* Init all external sources */
  346. for (i = 1; i < NumSources; i++) {
  347. int pri, sense;
  349. /* the bootloader may have left it enabled (bad !) */
  350. openpic_disable_irq(i+offset);
  352. pri = (i == programmer_switch_irq)? 9: 8;
  353. sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: 1;
  354. if (sense)
  355. irq_desc[i+offset].status = IRQ_LEVEL;
  357. /* Enabled, Priority 8 or 9 */
  358. openpic_initirq(i, pri, i+offset, !sense, sense);
  359. /* Processor 0 */
  360. openpic_mapirq(i, 1<<0);
  361. }
  363. /* Init descriptors */
  364. for (i = offset; i < NumSources + offset; i++)
  365. irq_desc[i].handler = &open_pic;
  367. /* Initialize the spurious interrupt */
  368. if (ppc_md.progress) ppc_md.progress("openpic spurious",0x3bd);
  369. openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
  371. /* Initialize the cascade */
  372. if (offset) {
  373. if (request_irq(offset, no_action, SA_INTERRUPT,
  374. "82c59 cascade", NULL))
  375. printk("Unable to get OpenPIC IRQ 0 for cascaden");
  376. }
  377. openpic_set_priority(0);
  378. openpic_disable_8259_pass_through();
  380. if (ppc_md.progress) ppc_md.progress("openpic exit",0x222);
  381. }
  383. #ifdef CONFIG_POWER3
  384. void openpic_setup_ISU(int isu_num, unsigned long addr)
  385. {
  386. if (isu_num >= OPENPIC_MAX_ISU)
  387. return;
  388. ISU[isu_num] = (OpenPIC_SourcePtr) ioremap(addr, 0x400);
  389. if (isu_num >= NumISUs)
  390. NumISUs = isu_num + 1;
  391. }
  392. #endif
  394. void find_ISUs(void)
  395. {
  396. #ifdef CONFIG_POWER3
  397.         /* Use /interrupt-controller/reg and
  398.          * /interrupt-controller/interrupt-ranges from OF device tree
  399.  * the ISU array is setup in chrp_pci.c in ibm_add_bridges
  400.  * as a result
  401.  * -- tgall
  402.          */
  404. /* basically each ISU is a bus, and this assumes that
  405.  * open_pic_isu_count interrupts per bus are possible 
  406.  * ISU == Interrupt Source
  407.  */
  408. NumSources = NumISUs * 0x10;
  410. #else
  411. /* for non-distributed OpenPIC implementations it's in the IDU -- Cort */
  412. ISU[0] = (OpenPIC_Source *)OpenPIC->Source;
  413. #endif
  414. }
  416. static void openpic_reset(void)
  417. {
  418. openpic_setfield(&OpenPIC->Global.Global_Configuration0,
  419.  OPENPIC_CONFIG_RESET);
  420. while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
  421.  OPENPIC_CONFIG_RESET))
  422. mb();
  423. }
  425. #ifdef notused
  426. static void openpic_enable_8259_pass_through(void)
  427. {
  428. openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
  429.    OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
  430. }
  431. #endif /* notused */
  433. static void openpic_disable_8259_pass_through(void)
  434. {
  435. openpic_setfield(&OpenPIC->Global.Global_Configuration0,
  436.  OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
  437. }
  439. /*
  440.  *  Find out the current interrupt
  441.  */
  442. u_int openpic_irq(void)
  443. {
  444. u_int vec;
  445. DECL_THIS_CPU;
  447. CHECK_THIS_CPU;
  448. vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
  449. OPENPIC_VECTOR_MASK);
  450. return vec;
  451. }
  453. void openpic_eoi(void)
  454. {
  455. DECL_THIS_CPU;
  457. CHECK_THIS_CPU;
  458. openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
  459. /* Handle PCI write posting */
  460. (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
  461. }
  463. #ifdef notused
  464. static u_int openpic_get_priority(void)
  465. {
  466. DECL_THIS_CPU;
  468. CHECK_THIS_CPU;
  469. return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
  470.  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
  471. }
  472. #endif /* notused */
  474. static void openpic_set_priority(u_int pri)
  475. {
  476. DECL_THIS_CPU;
  478. CHECK_THIS_CPU;
  479. check_arg_pri(pri);
  480. openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
  481.    OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
  482. }
  484. /*
  485.  *  Get/set the spurious vector
  486.  */
  487. #ifdef notused
  488. static u_int openpic_get_spurious(void)
  489. {
  490. return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
  491.  OPENPIC_VECTOR_MASK);
  492. }
  493. #endif /* notused */
  495. static void openpic_set_spurious(u_int vec)
  496. {
  497. check_arg_vec(vec);
  498. openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
  499.    vec);
  500. }
  502. #ifdef CONFIG_SMP
  503. /*
  504.  * Convert a cpu mask from logical to physical cpu numbers.
  505.  */
  506. static inline u32 physmask(u32 cpumask)
  507. {
  508. int i;
  509. u32 mask = 0;
  511. for (i = 0; i < smp_num_cpus; ++i, cpumask >>= 1)
  512. mask |= (cpumask & 1) << smp_hw_index[i];
  513. return mask;
  514. }
  515. #else
  516. #define physmask(cpumask) (cpumask)
  517. #endif
  519. void openpic_reset_processor_phys(u_int mask)
  520. {
  521. openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
  522. }
  524. static spinlock_t openpic_setup_lock = SPIN_LOCK_UNLOCKED;
  526. #ifdef CONFIG_SMP
  527. /*
  528.  *  Initialize an interprocessor interrupt (and disable it)
  529.  *
  530.  *  ipi: OpenPIC interprocessor interrupt number
  531.  *  pri: interrupt source priority
  532.  *  vec: the vector it will produce
  533.  */
  534. static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
  535. {
  536. check_arg_ipi(ipi);
  537. check_arg_pri(pri);
  538. check_arg_vec(vec);
  539. openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
  540. OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
  541. (pri << OPENPIC_PRIORITY_SHIFT) | vec);
  542. }
  544. /*
  545.  *  Send an IPI to one or more CPUs
  546.  *  
  547.  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
  548.  *  and not a system-wide interrupt number
  549.  */
  550. void openpic_cause_IPI(u_int ipi, u_int cpumask)
  551. {
  552. DECL_THIS_CPU;
  554. CHECK_THIS_CPU;
  555. check_arg_ipi(ipi);
  556. openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
  557.       physmask(cpumask));
  558. }
  560. void openpic_request_IPIs(void)
  561. {
  562. int i;
  564. /*
  565.  * Make sure this matches what is defined in smp.c for 
  566.  * smp_message_{pass|recv}() or what shows up in 
  567.  * /proc/interrupts will be wrong!!! --Troy */
  569. if (OpenPIC == NULL)
  570. return;
  572. request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
  573.     openpic_ipi_action, 0, "IPI0 (call function)", 0);
  574. request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
  575.     openpic_ipi_action, 0, "IPI1 (reschedule)", 0);
  576. request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
  577.     openpic_ipi_action, 0, "IPI2 (invalidate tlb)", 0);
  578. request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
  579.     openpic_ipi_action, 0, "IPI3 (xmon break)", 0);
  581. for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
  582. openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
  583. }
  585. /*
  586.  * Do per-cpu setup for SMP systems.
  587.  *
  588.  * Get IPI's working and start taking interrupts.
  589.  *   -- Cort
  590.  */
  592. void __init do_openpic_setup_cpu(void)
  593. {
  594.   int i;
  595. u32 msk = 1 << smp_hw_index[smp_processor_id()];
  597. spin_lock(&openpic_setup_lock);
  599. #ifdef CONFIG_IRQ_ALL_CPUS
  600.   /* let the openpic know we want intrs. default affinity
  601.    * is 0xffffffff until changed via /proc
  602.    * That's how it's done on x86. If we want it differently, then
  603.    * we should make sure we also change the default values of irq_affinity
  604.    * in irq.c.
  605.    */
  606.   for (i = 0; i < NumSources ; i++)
  607. openpic_mapirq(i, openpic_read(&GET_ISU(i).Destination) | msk);
  608. #endif /* CONFIG_IRQ_ALL_CPUS */
  609.   openpic_set_priority(0);
  611. spin_unlock(&openpic_setup_lock);
  612. }
  613. #endif /* CONFIG_SMP */
  615. /*
  616.  *  Initialize a timer interrupt (and disable it)
  617.  *
  618.  *  timer: OpenPIC timer number
  619.  *  pri: interrupt source priority
  620.  *  vec: the vector it will produce
  621.  */
  622. static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
  623. {
  624. check_arg_timer(timer);
  625. check_arg_pri(pri);
  626. check_arg_vec(vec);
  627. openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
  628. OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
  629. (pri << OPENPIC_PRIORITY_SHIFT) | vec);
  630. }
  632. /*
  633.  *  Map a timer interrupt to one or more CPUs
  634.  */
  635. static void __init openpic_maptimer(u_int timer, u_int cpumask)
  636. {
  637. check_arg_timer(timer);
  638. openpic_write(&OpenPIC->Global.Timer[timer].Destination,
  639.       physmask(cpumask));
  640. }
  643. /*
  644.  *
  645.  * All functions below take an offset'ed irq argument
  646.  *
  647.  */
  650. /*
  651.  *  Enable/disable an external interrupt source
  652.  *
  653.  *  Externally called, irq is an offseted system-wide interrupt number
  654.  */
  655. static void openpic_enable_irq(u_int irq)
  656. {
  657. check_arg_irq(irq);
  658. openpic_clearfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority, OPENPIC_MASK);
  659. /* make sure mask gets to controller before we return to user */
  660. do {
  661. mb(); /* sync is probably useless here */
  662. } while(openpic_readfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority,
  663. OPENPIC_MASK));
  664. }
  666. static void openpic_disable_irq(u_int irq)
  667. {
  668. u32 vp;
  670. check_arg_irq(irq);
  671. openpic_setfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority, OPENPIC_MASK);
  672. /* make sure mask gets to controller before we return to user */
  673. do {
  674. mb();  /* sync is probably useless here */
  675. vp = openpic_readfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority,
  676.      OPENPIC_MASK | OPENPIC_ACTIVITY);
  677. } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
  678. }
  680. #ifdef CONFIG_SMP
  681. /*
  682.  *  Enable/disable an IPI interrupt source
  683.  *  
  684.  *  Externally called, irq is an offseted system-wide interrupt number
  685.  */
  686. void openpic_enable_ipi(u_int irq)
  687. {
  688. irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
  689. check_arg_ipi(irq);
  690. openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
  692. }
  694. void openpic_disable_ipi(u_int irq)
  695. {
  696. irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
  697. check_arg_ipi(irq);
  698. openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
  699. }
  700. #endif
  702. /*
  703.  *  Initialize an interrupt source (and disable it!)
  704.  *
  705.  *  irq: OpenPIC interrupt number
  706.  *  pri: interrupt source priority
  707.  *  vec: the vector it will produce
  708.  *  pol: polarity (1 for positive, 0 for negative)
  709.  *  sense: 1 for level, 0 for edge
  710.  */
  711. static void openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
  712. {
  713. openpic_safe_writefield(&GET_ISU(irq).Vector_Priority,
  714. OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
  715. OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
  716. (pri << OPENPIC_PRIORITY_SHIFT) | vec |
  717. (pol ? OPENPIC_POLARITY_POSITIVE :
  718.      OPENPIC_POLARITY_NEGATIVE) |
  719. (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
  720. }
  722. /*
  723.  *  Map an interrupt source to one or more CPUs
  724.  */
  725. static void openpic_mapirq(u_int irq, u_int physmask)
  726. {
  727. openpic_write(&GET_ISU(irq).Destination, physmask);
  728. }
  730. #ifdef notused
  731. /*
  732.  *  Set the sense for an interrupt source (and disable it!)
  733.  *
  734.  *  sense: 1 for level, 0 for edge
  735.  */
  736. static void openpic_set_sense(u_int irq, int sense)
  737. {
  738. openpic_safe_writefield(&GET_ISU(irq).Vector_Priority,
  739. OPENPIC_SENSE_LEVEL,
  740. (sense ? OPENPIC_SENSE_LEVEL : 0));
  741. }
  742. #endif /* notused */
  744. /* No spinlocks, should not be necessary with the OpenPIC
  745.  * (1 register = 1 interrupt and we have the desc lock).
  746.  */
  747. static void openpic_ack_irq(unsigned int irq_nr)
  748. {
  749. openpic_disable_irq(irq_nr);
  750. openpic_eoi();
  751. }
  753. static void openpic_end_irq(unsigned int irq_nr)
  754. {
  755. if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  756. openpic_enable_irq(irq_nr);
  757. }
  759. static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask)
  760. {
  761. openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask));
  762. }
  764. #ifdef CONFIG_SMP
  765. static void openpic_ack_ipi(unsigned int irq_nr)
  766. {
  767. openpic_eoi();
  768. }
  770. static void openpic_end_ipi(unsigned int irq_nr)
  771. {
  772. }
  774. static void openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
  775. {
  776. smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
  777. }
  779. #endif /* CONFIG_SMP */
  781. /* This one may be merged with PReP and CHRP */
  782. int
  783. openpic_get_irq(struct pt_regs *regs)
  784. {
  785. /*
  786.  * Clean up needed. -VAL
  787.  */
  788. int irq = openpic_irq();
  790. /* Management of the cascade should be moved out of here */
  792. /* Yep - because openpic !=> i8259, for one thing. -VAL */
  793.         if (open_pic_irq_offset && irq == open_pic_irq_offset)
  794.         {
  795.                 /*
  796.                  * This magic address generates a PCI IACK cycle.
  797.                  */
  798. if ( chrp_int_ack_special )
  799. irq = *chrp_int_ack_special;
  800. #ifndef CONFIG_GEMINI
  801. else
  802. irq = i8259_poll();
  803. #endif
  804. openpic_eoi();
  805.         }
  806. if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
  807. irq = -1;
  808. return irq;
  809. }
  811. #ifdef CONFIG_SMP
  812. void
  813. smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
  814. {
  815. /* make sure we're sending something that translates to an IPI */
  816. if (msg > 0x3) {
  817. printk("SMP %d: smp_message_pass: unknown msg %dn",
  818.        smp_processor_id(), msg);
  819. return;
  820. }
  821. switch (target) {
  822. case MSG_ALL:
  823. openpic_cause_IPI(msg, 0xffffffff);
  824. break;
  825. case MSG_ALL_BUT_SELF:
  826. openpic_cause_IPI(msg,
  827.   0xffffffff & ~(1 << smp_processor_id()));
  828. break;
  829. default:
  830. openpic_cause_IPI(msg, 1<<target);
  831. break;
  832. }
  833. }
  834. #endif /* CONFIG_SMP */
  836. #ifdef CONFIG_PMAC_PBOOK
  837. static u32 save_ipi_vp[OPENPIC_NUM_IPI];
  838. static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
  839. static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
  840. static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
  842. void __pmac
  843. openpic_sleep_save_intrs(void)
  844. {
  845. int i;
  846. unsigned long flags;
  848. spin_lock_irqsave(&openpic_setup_lock, flags);
  850. for (i=0; i<NumProcessors; i++) {
  851. save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
  852. openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
  853.    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
  854. }
  856. for (i=0; i<OPENPIC_NUM_IPI; i++)
  857. save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
  858. for (i=0; i<NumSources; i++) {
  859. save_irq_src_vp[i] = openpic_read(&OpenPIC->Source[i].Vector_Priority)
  860. & ~OPENPIC_ACTIVITY;
  861. save_irq_src_dest[i] = openpic_read(&OpenPIC->Source[i].Destination);
  862. }
  863. spin_unlock_irqrestore(&openpic_setup_lock, flags);
  864. }
  866. void __pmac
  867. openpic_sleep_restore_intrs(void)
  868. {
  869. int i;
  870. unsigned long flags;
  872. spin_lock_irqsave(&openpic_setup_lock, flags);
  874. openpic_reset();
  876. for (i=0; i<OPENPIC_NUM_IPI; i++)
  877. openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i), save_ipi_vp[i]);
  878. for (i=0; i<NumSources; i++) {
  879. openpic_write(&OpenPIC->Source[i].Vector_Priority, save_irq_src_vp[i]);
  880. openpic_write(&OpenPIC->Source[i].Destination, save_irq_src_dest[i]);
  881. }
  882. openpic_set_spurious(OPENPIC_VEC_SPURIOUS+open_pic_irq_offset);
  883. openpic_disable_8259_pass_through();
  884. for (i=0; i<NumProcessors; i++)
  885. openpic_write(&OpenPIC->Processor[i].Current_Task_Priority, save_cpu_task_pri[i]);
  887. spin_unlock_irqrestore(&openpic_setup_lock, flags);
  888. }
  889. #endif /* CONFIG_PMAC_PBOOK */