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mca_asm.S
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：20k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

mca_asm.S：源码内容
  1. //
  2. // assembly portion of the IA64 MCA handling
  3. //
  4. // Mods by cfleck to integrate into kernel build
  5. // 00/03/15 davidm Added various stop bits to get a clean compile
  6. //
  7. // 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
  8. //    kstack, switch modes, jump to C INIT handler
  9. //
  10. #include <linux/config.h>
  12. #include <asm/asmmacro.h>
  13. #include <asm/pgtable.h>
  14. #include <asm/processor.h>
  15. #include <asm/mca_asm.h>
  16. #include <asm/mca.h>
  18. /*
  19.  * When we get an machine check, the kernel stack pointer is no longer
  20.  * valid, so we need to set a new stack pointer.
  21.  */
  22. #define MINSTATE_PHYS /* Make sure stack access is physical for MINSTATE */
  24. #include "minstate.h"
  26. /*
  27.  *  SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
  28.  * 1. GR1 = OS GP
  29.  * 2. GR8 = PAL_PROC physical address
  30.  * 3. GR9 = SAL_PROC physical address
  31.  * 4. GR10 = SAL GP (physical)
  32.  * 5. GR11 = Rendez state
  33.  * 6. GR12 = Return address to location within SAL_CHECK
  34.  */
  35. #define SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(_tmp)
  36. movl _tmp=ia64_sal_to_os_handoff_state;;
  37. DATA_VA_TO_PA(_tmp);;
  38. st8 [_tmp]=r1,0x08;;
  39. st8 [_tmp]=r8,0x08;;
  40. st8 [_tmp]=r9,0x08;;
  41. st8 [_tmp]=r10,0x08;;
  42. st8 [_tmp]=r11,0x08;;
  43. st8 [_tmp]=r12,0x08;;
  45. /*
  46.  *  OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
  47.  *      1. GR8 = OS_MCA return status
  48.  * 2. GR9 = SAL GP (physical)
  49.  *      3. GR10 = 0/1 returning same/new context
  50.  *      4. GR22 = New min state save area pointer
  51.  *      returns ptr to SAL rtn save loc in _tmp
  52.  */
  53. #define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp)
  54. movl _tmp=ia64_os_to_sal_handoff_state;;
  55. DATA_VA_TO_PA(_tmp);;
  56. ld8 r8=[_tmp],0x08;;
  57. ld8 r9=[_tmp],0x08;;
  58. ld8     r10=[_tmp],0x08;;
  59. ld8     r22=[_tmp],0x08;;
  60. movl    _tmp=ia64_sal_to_os_handoff_state;;
  61. DATA_VA_TO_PA(_tmp);;
  62. add     _tmp=0x28,_tmp;;            // point to SAL rtn save location
  64. .global ia64_os_mca_dispatch
  65. .global ia64_os_mca_dispatch_end
  66. .global ia64_sal_to_os_handoff_state
  67. .global ia64_os_to_sal_handoff_state
  68. .global ia64_mca_proc_state_dump
  69. .global ia64_mca_stack
  70. .global ia64_mca_stackframe
  71. .global ia64_mca_bspstore
  72. .global ia64_init_stack
  74. .text
  75. .align 16
  77. ia64_os_mca_dispatch:
  79. #if defined(MCA_TEST)
  80. // Pretend that we are in interrupt context
  81. mov r2=psr
  82. dep r2=0, r2, PSR_IC, 2;
  83. mov psr.l = r2
  84. #endif /* #if defined(MCA_TEST) */
  86. // Save the SAL to OS MCA handoff state as defined
  87. // by SAL SPEC 3.0
  88. // NOTE : The order in which the state gets saved
  89. //   is dependent on the way the C-structure
  90. //   for ia64_mca_sal_to_os_state_t has been
  91. //   defined in include/asm/mca.h
  92. SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
  94. // LOG PROCESSOR STATE INFO FROM HERE ON..
  95. ;;
  96. begin_os_mca_dump:
  97. br ia64_os_mca_proc_state_dump;;
  99. ia64_os_mca_done_dump:
  101. // Setup new stack frame for OS_MCA handling
  102. movl    r2=ia64_mca_bspstore;;      // local bspstore area location in r2
  103. DATA_VA_TO_PA(r2);;
  104. movl    r3=ia64_mca_stackframe;;    // save stack frame to memory in r3
  105. DATA_VA_TO_PA(r3);;
  106. rse_switch_context(r6,r3,r2);;                  // RSC management in this new context
  107. movl        r12=ia64_mca_stack;;
  108. mov     r2=8*1024;;                 // stack size must be same as c array
  109. add     r12=r2,r12;;                // stack base @ bottom of array
  110. DATA_VA_TO_PA(r12);;
  112. // Enter virtual mode from physical mode
  113. VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
  114. ia64_os_mca_virtual_begin:
  116. // call our handler
  117. movl r2=ia64_mca_ucmc_handler;;
  118. mov b6=r2;;
  119. br.call.sptk.many    b0=b6;;
  120. .ret0:
  121. // Revert back to physical mode before going back to SAL
  122. PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
  123. ia64_os_mca_virtual_end:
  125. #if defined(MCA_TEST)
  126. // Pretend that we are in interrupt context
  127. mov r2=psr;;
  128. dep r2=0, r2, PSR_IC, 2;;
  129. mov psr.l = r2;;
  130. #endif /* #if defined(MCA_TEST) */
  132. // restore the original stack frame here
  133. movl    r2=ia64_mca_stackframe               // restore stack frame from memory at r2
  134. ;;
  135. DATA_VA_TO_PA(r2)
  136. movl    r4=IA64_PSR_MC
  137. ;;
  138. rse_return_context(r4,r3,r2)                 // switch from interrupt context for RSE
  140. // let us restore all the registers from our PSI structure
  141. mov r8=gp
  142. ;;
  143. begin_os_mca_restore:
  144. br ia64_os_mca_proc_state_restore;;
  146. ia64_os_mca_done_restore:
  147. ;;
  148. // branch back to SALE_CHECK
  149. OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2)
  150. ld8 r3=[r2];;
  151. mov b0=r3;;       // SAL_CHECK return address
  152. br b0
  153. ;;
  154. ia64_os_mca_dispatch_end:
  155. //EndMain//////////////////////////////////////////////////////////////////////
  158. //++
  159. // Name:
  160. //      ia64_os_mca_proc_state_dump()
  161. //
  162. // Stub Description:
  163. //
  164. //       This stub dumps the processor state during MCHK to a data area
  165. //
  166. //--
  168. ia64_os_mca_proc_state_dump:
  169. // Save bank 1 GRs 16-31 which will be used by c-language code when we switch
  170. //  to virtual addressing mode.
  171. movl r2=ia64_mca_proc_state_dump;;           // Os state dump area
  172.         DATA_VA_TO_PA(r2)                   // convert to to physical address
  174. // save ar.NaT
  175. mov r5=ar.unat                  // ar.unat
  177. // save banked GRs 16-31 along with NaT bits
  178. bsw.1;;
  179. st8.spill [r2]=r16,8;;
  180. st8.spill [r2]=r17,8;;
  181. st8.spill [r2]=r18,8;;
  182. st8.spill [r2]=r19,8;;
  183. st8.spill [r2]=r20,8;;
  184. st8.spill [r2]=r21,8;;
  185. st8.spill [r2]=r22,8;;
  186. st8.spill [r2]=r23,8;;
  187. st8.spill [r2]=r24,8;;
  188. st8.spill [r2]=r25,8;;
  189. st8.spill [r2]=r26,8;;
  190. st8.spill [r2]=r27,8;;
  191. st8.spill [r2]=r28,8;;
  192. st8.spill [r2]=r29,8;;
  193. st8.spill [r2]=r30,8;;
  194. st8.spill [r2]=r31,8;;
  196. mov r4=ar.unat;;
  197. st8 [r2]=r4,8                // save User NaT bits for r16-r31
  198. mov ar.unat=r5                  // restore original unat
  199. bsw.0;;
  201. //save BRs
  202. add r4=8,r2                  // duplicate r2 in r4
  203. add r6=2*8,r2                // duplicate r2 in r4
  205. mov r3=b0
  206. mov r5=b1
  207. mov r7=b2;;
  208. st8 [r2]=r3,3*8
  209. st8 [r4]=r5,3*8
  210. st8 [r6]=r7,3*8;;
  212. mov r3=b3
  213. mov r5=b4
  214. mov r7=b5;;
  215. st8 [r2]=r3,3*8
  216. st8 [r4]=r5,3*8
  217. st8 [r6]=r7,3*8;;
  219. mov r3=b6
  220. mov r5=b7;;
  221. st8 [r2]=r3,2*8
  222. st8 [r4]=r5,2*8;;
  224. cSaveCRs:
  225. // save CRs
  226. add r4=8,r2                  // duplicate r2 in r4
  227. add r6=2*8,r2                // duplicate r2 in r4
  229. mov r3=cr0                      // cr.dcr
  230. mov r5=cr1                      // cr.itm
  231. mov r7=cr2;;                    // cr.iva
  233. st8 [r2]=r3,8*8
  234. st8 [r4]=r5,3*8
  235. st8 [r6]=r7,3*8;;            // 48 byte rements
  237. mov r3=cr8;;                    // cr.pta
  238. st8 [r2]=r3,8*8;;            // 64 byte rements
  240. // if PSR.ic=0, reading interruption registers causes an illegal operation fault
  241. mov r3=psr;;
  242. tbit.nz.unc p6,p0=r3,PSR_IC;;           // PSI Valid Log bit pos. test
  243. (p6)    st8     [r2]=r0,9*8+160             // increment by 232 byte inc.
  244. begin_skip_intr_regs:
  245. (p6) br SkipIntrRegs;;
  247. add r4=8,r2                  // duplicate r2 in r4
  248. add r6=2*8,r2                // duplicate r2 in r6
  250. mov r3=cr16                     // cr.ipsr
  251. mov r5=cr17                     // cr.isr
  252.         mov     r7=r0;;                     // cr.ida => cr18 (reserved)
  253. st8 [r2]=r3,3*8
  254. st8 [r4]=r5,3*8
  255. st8 [r6]=r7,3*8;;
  257. mov r3=cr19                     // cr.iip
  258. mov r5=cr20                     // cr.idtr
  259. mov r7=cr21;;                   // cr.iitr
  260. st8 [r2]=r3,3*8
  261. st8 [r4]=r5,3*8
  262. st8 [r6]=r7,3*8;;
  264. mov r3=cr22                     // cr.iipa
  265. mov r5=cr23                     // cr.ifs
  266. mov r7=cr24;;                   // cr.iim
  267. st8 [r2]=r3,3*8
  268. st8 [r4]=r5,3*8
  269. st8 [r6]=r7,3*8;;
  271. mov r3=cr25;;                   // cr.iha
  272. st8 [r2]=r3,160;;               // 160 byte rement
  274. SkipIntrRegs:
  275. st8 [r2]=r0,168                 // another 168 byte .
  277. mov r3=cr66;;                   // cr.lid
  278. st8 [r2]=r3,40                  // 40 byte rement
  280. mov r3=cr71;;                   // cr.ivr
  281. st8 [r2]=r3,8
  283. mov r3=cr72;;                   // cr.tpr
  284. st8 [r2]=r3,24                  // 24 byte increment
  286. mov r3=r0;;                     // cr.eoi => cr75
  287. st8 [r2]=r3,168                 // 168 byte inc.
  289. mov r3=r0;;                     // cr.irr0 => cr96
  290. st8 [r2]=r3,16               // 16 byte inc.
  292. mov r3=r0;;                     // cr.irr1 => cr98
  293. st8 [r2]=r3,16               // 16 byte inc.
  295. mov r3=r0;;                     // cr.irr2 => cr100
  296. st8 [r2]=r3,16               // 16 byte inc
  298. mov r3=r0;;                     // cr.irr3 => cr100
  299. st8 [r2]=r3,16               // 16b inc.
  301. mov r3=r0;;                     // cr.itv => cr114
  302. st8 [r2]=r3,16               // 16 byte inc.
  304. mov r3=r0;;                     // cr.pmv => cr116
  305. st8 [r2]=r3,8
  307. mov r3=r0;;                     // cr.lrr0 => cr117
  308. st8 [r2]=r3,8
  310. mov r3=r0;;                     // cr.lrr1 => cr118
  311. st8 [r2]=r3,8
  313. mov r3=r0;;                     // cr.cmcv => cr119
  314. st8 [r2]=r3,8*10;;
  316. cSaveARs:
  317. // save ARs
  318. add r4=8,r2                  // duplicate r2 in r4
  319. add r6=2*8,r2                // duplicate r2 in r6
  321. mov r3=ar0                      // ar.kro
  322. mov r5=ar1                      // ar.kr1
  323. mov r7=ar2;;                    // ar.kr2
  324. st8 [r2]=r3,3*8
  325. st8 [r4]=r5,3*8
  326. st8 [r6]=r7,3*8;;
  328. mov r3=ar3                      // ar.kr3
  329. mov r5=ar4                      // ar.kr4
  330. mov r7=ar5;;                    // ar.kr5
  331. st8 [r2]=r3,3*8
  332. st8 [r4]=r5,3*8
  333. st8 [r6]=r7,3*8;;
  335. mov r3=ar6                      // ar.kr6
  336. mov r5=ar7                      // ar.kr7
  337. mov r7=r0;;                     // ar.kr8
  338. st8 [r2]=r3,10*8
  339. st8 [r4]=r5,10*8
  340. st8 [r6]=r7,10*8;;           // rement by 72 bytes
  342. mov r3=ar16                     // ar.rsc
  343. mov ar16=r0     // put RSE in enforced lazy mode
  344. mov r5=ar17                     // ar.bsp
  345. ;;
  346. mov r7=ar18;;                   // ar.bspstore
  347. st8 [r2]=r3,3*8
  348. st8 [r4]=r5,3*8
  349. st8 [r6]=r7,3*8;;
  351. mov r3=ar19;;                   // ar.rnat
  352. st8 [r2]=r3,8*13             // increment by 13x8 bytes
  354. mov r3=ar32;;                   // ar.ccv
  355. st8 [r2]=r3,8*4
  357. mov r3=ar36;;                   // ar.unat
  358. st8 [r2]=r3,8*4
  360. mov r3=ar40;;                   // ar.fpsr
  361. st8 [r2]=r3,8*4
  363. mov r3=ar44;;                   // ar.itc
  364. st8 [r2]=r3,160                 // 160
  366. mov r3=ar64;;                   // ar.pfs
  367. st8 [r2]=r3,8
  369. mov r3=ar65;;                   // ar.lc
  370. st8 [r2]=r3,8
  372. mov r3=ar66;;                   // ar.ec
  373. st8 [r2]=r3
  374. add r2=8*62,r2               //padding
  376. // save RRs
  377. mov ar.lc=0x08-1
  378. movl r4=0x00;;
  380. cStRR:
  381. mov r3=rr[r4];;
  382. st8 [r2]=r3,8
  383. add r4=1,r4
  384. br.cloop.sptk.few cStRR
  385. ;;
  386. end_os_mca_dump:
  387. br ia64_os_mca_done_dump;;
  389. //EndStub//////////////////////////////////////////////////////////////////////
  392. //++
  393. // Name:
  394. //       ia64_os_mca_proc_state_restore()
  395. //
  396. // Stub Description:
  397. //
  398. //       This is a stub to restore the saved processor state during MCHK
  399. //
  400. //--
  402. ia64_os_mca_proc_state_restore:
  404. // Restore bank1 GR16-31
  405. movl r2=ia64_mca_proc_state_dump // Convert virtual address
  406. ;; // of OS state dump area
  407. DATA_VA_TO_PA(r2) // to physical address
  408. ;;
  409. restore_GRs:                                    // restore bank-1 GRs 16-31
  410. bsw.1;;
  411. add r3=16*8,r2;;                // to get to NaT of GR 16-31
  412. ld8 r3=[r3];;
  413. mov ar.unat=r3;;                // first restore NaT
  415. ld8.fill r16=[r2],8;;
  416. ld8.fill r17=[r2],8;;
  417. ld8.fill r18=[r2],8;;
  418. ld8.fill r19=[r2],8;;
  419. ld8.fill r20=[r2],8;;
  420. ld8.fill r21=[r2],8;;
  421. ld8.fill r22=[r2],8;;
  422. ld8.fill r23=[r2],8;;
  423. ld8.fill r24=[r2],8;;
  424. ld8.fill r25=[r2],8;;
  425. ld8.fill r26=[r2],8;;
  426. ld8.fill r27=[r2],8;;
  427. ld8.fill r28=[r2],8;;
  428. ld8.fill r29=[r2],8;;
  429. ld8.fill r30=[r2],8;;
  430. ld8.fill r31=[r2],8;;
  432. ld8 r3=[r2],8;;              // increment to skip NaT
  433. bsw.0;;
  435. restore_BRs:
  436. add r4=8,r2                  // duplicate r2 in r4
  437. add r6=2*8,r2;;              // duplicate r2 in r4
  439. ld8 r3=[r2],3*8
  440. ld8 r5=[r4],3*8
  441. ld8 r7=[r6],3*8;;
  442. mov b0=r3
  443. mov b1=r5
  444. mov b2=r7;;
  446. ld8 r3=[r2],3*8
  447. ld8 r5=[r4],3*8
  448. ld8 r7=[r6],3*8;;
  449. mov b3=r3
  450. mov b4=r5
  451. mov b5=r7;;
  453. ld8 r3=[r2],2*8
  454. ld8 r5=[r4],2*8;;
  455. mov b6=r3
  456. mov b7=r5;;
  458. restore_CRs:
  459. add r4=8,r2                  // duplicate r2 in r4
  460. add r6=2*8,r2;;              // duplicate r2 in r4
  462. ld8 r3=[r2],8*8
  463. ld8 r5=[r4],3*8
  464. ld8 r7=[r6],3*8;;            // 48 byte increments
  465. mov cr0=r3                      // cr.dcr
  466. mov cr1=r5                      // cr.itm
  467. mov cr2=r7;;                    // cr.iva
  469. ld8 r3=[r2],8*8;;            // 64 byte increments
  470. //      mov cr8=r3                      // cr.pta
  473. // if PSR.ic=1, reading interruption registers causes an illegal operation fault
  474. mov r3=psr;;
  475. tbit.nz.unc p6,p0=r3,PSR_IC;;           // PSI Valid Log bit pos. test
  476. (p6)    st8     [r2]=r0,9*8+160             // increment by 232 byte inc.
  478. begin_rskip_intr_regs:
  479. (p6) br rSkipIntrRegs;;
  481. add r4=8,r2                  // duplicate r2 in r4
  482. add r6=2*8,r2;;              // duplicate r2 in r4
  484. ld8 r3=[r2],3*8
  485. ld8 r5=[r4],3*8
  486. ld8 r7=[r6],3*8;;
  487. mov cr16=r3                     // cr.ipsr
  488. mov cr17=r5                     // cr.isr is read only
  489. //      mov     cr18=r7;;                   // cr.ida (reserved - don't restore)
  491. ld8 r3=[r2],3*8
  492. ld8 r5=[r4],3*8
  493. ld8 r7=[r6],3*8;;
  494. mov cr19=r3                     // cr.iip
  495. mov cr20=r5                     // cr.idtr
  496. mov cr21=r7;;                   // cr.iitr
  498. ld8 r3=[r2],3*8
  499. ld8 r5=[r4],3*8
  500. ld8 r7=[r6],3*8;;
  501. mov cr22=r3                     // cr.iipa
  502. mov cr23=r5                     // cr.ifs
  503. mov cr24=r7                     // cr.iim
  505. ld8 r3=[r2],160;;               // 160 byte increment
  506. mov cr25=r3                     // cr.iha
  508. rSkipIntrRegs:
  509. ld8 r3=[r2],168;;               // another 168 byte inc.
  511. ld8 r3=[r2],40;;                // 40 byte increment
  512. mov cr66=r3                     // cr.lid
  514. ld8 r3=[r2],8;;
  515. //      mov cr71=r3                     // cr.ivr is read only
  516. ld8 r3=[r2],24;;                // 24 byte increment
  517. mov cr72=r3                     // cr.tpr
  519. ld8 r3=[r2],168;;               // 168 byte inc.
  520. //      mov cr75=r3                     // cr.eoi
  522. ld8 r3=[r2],16;;             // 16 byte inc.
  523. //      mov cr96=r3                     // cr.irr0 is read only
  525. ld8 r3=[r2],16;;             // 16 byte inc.
  526. //      mov cr98=r3                     // cr.irr1 is read only
  528. ld8 r3=[r2],16;;             // 16 byte inc
  529. //      mov cr100=r3                    // cr.irr2 is read only
  531. ld8 r3=[r2],16;;             // 16b inc.
  532. //      mov cr102=r3                    // cr.irr3 is read only
  534. ld8 r3=[r2],16;;             // 16 byte inc.
  535. //      mov cr114=r3                    // cr.itv
  537. ld8 r3=[r2],8;;
  538. //      mov cr116=r3                    // cr.pmv
  539. ld8 r3=[r2],8;;
  540. //      mov cr117=r3                    // cr.lrr0
  541. ld8 r3=[r2],8;;
  542. //      mov cr118=r3                    // cr.lrr1
  543. ld8 r3=[r2],8*10;;
  544. //      mov cr119=r3                    // cr.cmcv
  546. restore_ARs:
  547. add r4=8,r2                  // duplicate r2 in r4
  548. add r6=2*8,r2;;              // duplicate r2 in r4
  550. ld8 r3=[r2],3*8
  551. ld8 r5=[r4],3*8
  552. ld8 r7=[r6],3*8;;
  553. mov ar0=r3                      // ar.kro
  554. mov ar1=r5                      // ar.kr1
  555. mov ar2=r7;;                    // ar.kr2
  557. ld8 r3=[r2],3*8
  558. ld8 r5=[r4],3*8
  559. ld8 r7=[r6],3*8;;
  560. mov ar3=r3                      // ar.kr3
  561. mov ar4=r5                      // ar.kr4
  562. mov ar5=r7;;                    // ar.kr5
  564. ld8 r3=[r2],10*8
  565. ld8 r5=[r4],10*8
  566. ld8 r7=[r6],10*8;;
  567. mov ar6=r3                      // ar.kr6
  568. mov ar7=r5                      // ar.kr7
  569. //      mov ar8=r6                      // ar.kr8
  570. ;;
  572. ld8 r3=[r2],3*8
  573. ld8 r5=[r4],3*8
  574. ld8 r7=[r6],3*8;;
  575. //      mov ar16=r3                     // ar.rsc
  576. //      mov ar17=r5                     // ar.bsp is read only
  577. mov ar16=r0     // make sure that RSE is in enforced lazy mode
  578. ;;
  579. mov ar18=r7;;                   // ar.bspstore
  581. ld8 r9=[r2],8*13;;
  582. mov ar19=r9                     // ar.rnat
  584. mov ar16=r3     // ar.rsc
  585. ld8 r3=[r2],8*4;;
  586. mov ar32=r3                     // ar.ccv
  588. ld8 r3=[r2],8*4;;
  589. mov ar36=r3                     // ar.unat
  591. ld8 r3=[r2],8*4;;
  592. mov ar40=r3                     // ar.fpsr
  594. ld8 r3=[r2],160;;               // 160
  595. //      mov ar44=r3                     // ar.itc
  597. ld8 r3=[r2],8;;
  598. mov ar64=r3                     // ar.pfs
  600. ld8 r3=[r2],8;;
  601. mov ar65=r3                     // ar.lc
  603. ld8 r3=[r2];;
  604. mov ar66=r3                     // ar.ec
  605. add r2=8*62,r2;;             // padding
  607. restore_RRs:
  608. mov r5=ar.lc
  609. mov ar.lc=0x08-1
  610. movl r4=0x00
  611. cStRRr:
  612. ld8 r3=[r2],8;;
  613. //      mov rr[r4]=r3                   // what are its access previledges?
  614. add r4=1,r4
  615. br.cloop.sptk.few cStRRr
  616. ;;
  617. mov ar.lc=r5
  618. ;;
  619. end_os_mca_restore:
  620. br ia64_os_mca_done_restore;;
  622. //EndStub//////////////////////////////////////////////////////////////////////
  624. // ok, the issue here is that we need to save state information so
  625. // it can be useable by the kernel debugger and show regs routines.
  626. // In order to do this, our best bet is save the current state (plus
  627. // the state information obtain from the MIN_STATE_AREA) into a pt_regs
  628. // format.  This way we can pass it on in a useable format.
  629. //
  631. //
  632. // SAL to OS entry point for INIT on the monarch processor
  633. // This has been defined for registration purposes with SAL
  634. // as a part of ia64_mca_init.
  635. //
  636. // When we get here, the follow registers have been
  637. // set by the SAL for our use
  638. //
  639. // 1. GR1 = OS INIT GP
  640. // 2. GR8 = PAL_PROC physical address
  641. // 3. GR9 = SAL_PROC physical address
  642. // 4. GR10 = SAL GP (physical)
  643. // 5. GR11 = Init Reason
  644. // 0 = Received INIT for event other than crash dump switch
  645. // 1 = Received wakeup at the end of an OS_MCA corrected machine check
  646. // 2 = Received INIT dude to CrashDump switch assertion
  647. //
  648. // 6. GR12 = Return address to location within SAL_INIT procedure
  651. GLOBAL_ENTRY(ia64_monarch_init_handler)
  652. #if defined(CONFIG_SMP) && defined(SAL_MPINIT_WORKAROUND)
  653. //
  654. // work around SAL bug that sends all processors to monarch entry
  655. //
  656. mov r17=cr.lid
  657. // XXX fix me: this is wrong: hard_smp_processor_id() is a pair of lid/eid
  658. movl r18=ia64_cpu_to_sapicid
  659. ;;
  660. dep r18=0,r18,61,3 // convert to physical address
  661. ;;
  662. shr.u r17=r17,16
  663. ld4 r18=[r18] // get the BSP ID
  664. ;;
  665. dep r17=0,r17,16,48
  666. ;;
  667. cmp4.ne p6,p0=r17,r18 // Am I the BSP ?
  668. (p6) br.cond.spnt slave_init_spin_me
  669. ;;
  670. #endif
  673. //
  674. // ok, the first thing we do is stash the information
  675. // the SAL passed to os
  676. //
  677. _tmp = r2
  678. movl _tmp=ia64_sal_to_os_handoff_state
  679. ;;
  680. dep _tmp=0,_tmp, 61, 3 // get physical address
  681. ;;
  682. st8 [_tmp]=r1,0x08;;
  683. st8 [_tmp]=r8,0x08;;
  684. st8 [_tmp]=r9,0x08;;
  685. st8 [_tmp]=r10,0x08;;
  686. st8 [_tmp]=r11,0x08;;
  687. st8 [_tmp]=r12,0x08;;
  689. // now we want to save information so we can dump registers
  690. SAVE_MIN_WITH_COVER
  691. ;;
  692. mov r8=cr.ifa
  693. mov r9=cr.isr
  694. adds r3=8,r2 // set up second base pointer
  695. ;;
  696. SAVE_REST
  698. // ok, enough should be saved at this point to be dangerous, and  supply
  699. // information for a dump
  700. // We need to switch to Virtual mode before hitting the C functions.
  701. //
  702. //
  703. //
  704. movl r2=IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN
  705. mov r3=psr // get the current psr, minimum enabled at this point
  706. ;;
  707. or r2=r2,r3
  708. ;;
  709. movl r3=IVirtual_Switch
  710. ;;
  711. mov cr.iip=r3 // short return to set the appropriate bits
  712. mov cr.ipsr=r2 // need to do an rfi to set appropriate bits
  713. ;;
  714. rfi
  715. ;;
  716. IVirtual_Switch:
  717. //
  718. // We should now be running virtual
  719. //
  720. // Lets call the C handler to get the rest of the state info
  721. //
  722. alloc r14=ar.pfs,0,0,1,0 // now it's safe (must be first in insn group!)
  723. ;; //
  724. adds out0=16,sp // out0 = pointer to pt_regs
  725. ;;
  727. br.call.sptk.many rp=ia64_init_handler
  728. .ret1:
  730. return_from_init:
  731. br.sptk return_from_init
  732. END(ia64_monarch_init_handler)
  734. //
  735. // SAL to OS entry point for INIT on the slave processor
  736. // This has been defined for registration purposes with SAL
  737. // as a part of ia64_mca_init.
  738. //
  740. GLOBAL_ENTRY(ia64_slave_init_handler)
  741. 1: br.sptk 1b
  742. END(ia64_slave_init_handler)