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radeon.h
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：38k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

radeon.h：源码内容
  1. #ifndef _RADEON_H
  2. #define _RADEON_H
  5. /* radeon PCI ids */
  6. #define PCI_DEVICE_ID_RADEON_QD 0x5144
  7. #define PCI_DEVICE_ID_RADEON_QE 0x5145
  8. #define PCI_DEVICE_ID_RADEON_QF 0x5146
  9. #define PCI_DEVICE_ID_RADEON_QG 0x5147
  10. #define PCI_DEVICE_ID_RADEON_QY 0x5159
  11. #define PCI_DEVICE_ID_RADEON_QZ 0x515a
  12. #define PCI_DEVICE_ID_RADEON_LW 0x4c57
  13. #define PCI_DEVICE_ID_RADEON_LY 0x4c59
  14. #define PCI_DEVICE_ID_RADEON_LZ 0x4c5a
  15. #define PCI_DEVICE_ID_RADEON_QL 0x514c
  16. #define PCI_DEVICE_ID_RADEON_QW 0x5157
  18. #define RADEON_REGSIZE 0x4000
  21. #define MM_INDEX                               0x0000  
  22. #define MM_DATA                                0x0004  
  23. #define BUS_CNTL                               0x0030  
  24. #define HI_STAT                                0x004C  
  25. #define BUS_CNTL1                              0x0034
  26. #define I2C_CNTL_1        0x0094  
  27. #define CONFIG_CNTL                            0x00E0  
  28. #define CONFIG_MEMSIZE                         0x00F8  
  29. #define CONFIG_APER_0_BASE                     0x0100  
  30. #define CONFIG_APER_1_BASE                     0x0104  
  31. #define CONFIG_APER_SIZE                       0x0108  
  32. #define CONFIG_REG_1_BASE                      0x010C  
  33. #define CONFIG_REG_APER_SIZE                   0x0110  
  34. #define PAD_AGPINPUT_DELAY                     0x0164  
  35. #define PAD_CTLR_STRENGTH                      0x0168  
  36. #define PAD_CTLR_UPDATE                        0x016C
  37. #define AGP_CNTL                               0x0174
  38. #define BM_STATUS                              0x0160
  39. #define CAP0_TRIG_CNTL        0x0950
  40. #define VIPH_CONTROL        0x0C40
  41. #define VENDOR_ID                              0x0F00  
  42. #define DEVICE_ID                              0x0F02  
  43. #define COMMAND                                0x0F04  
  44. #define STATUS                                 0x0F06  
  45. #define REVISION_ID                            0x0F08  
  46. #define REGPROG_INF                            0x0F09  
  47. #define SUB_CLASS                              0x0F0A  
  48. #define BASE_CODE                              0x0F0B  
  49. #define CACHE_LINE                             0x0F0C  
  50. #define LATENCY                                0x0F0D  
  51. #define HEADER                                 0x0F0E  
  52. #define BIST                                   0x0F0F  
  53. #define REG_MEM_BASE                           0x0F10  
  54. #define REG_IO_BASE                            0x0F14  
  55. #define REG_REG_BASE                           0x0F18
  56. #define ADAPTER_ID                             0x0F2C
  57. #define BIOS_ROM                               0x0F30
  58. #define CAPABILITIES_PTR                       0x0F34  
  59. #define INTERRUPT_LINE                         0x0F3C  
  60. #define INTERRUPT_PIN                          0x0F3D  
  61. #define MIN_GRANT                              0x0F3E  
  62. #define MAX_LATENCY                            0x0F3F  
  63. #define ADAPTER_ID_W                           0x0F4C  
  64. #define PMI_CAP_ID                             0x0F50  
  65. #define PMI_NXT_CAP_PTR                        0x0F51  
  66. #define PMI_PMC_REG                            0x0F52  
  67. #define PM_STATUS                              0x0F54  
  68. #define PMI_DATA                               0x0F57  
  69. #define AGP_CAP_ID                             0x0F58  
  70. #define AGP_STATUS                             0x0F5C  
  71. #define AGP_COMMAND                            0x0F60  
  72. #define AIC_CTRL                               0x01D0
  73. #define AIC_STAT                               0x01D4
  74. #define AIC_PT_BASE                            0x01D8
  75. #define AIC_LO_ADDR                            0x01DC  
  76. #define AIC_HI_ADDR                            0x01E0  
  77. #define AIC_TLB_ADDR                           0x01E4  
  78. #define AIC_TLB_DATA                           0x01E8  
  79. #define DAC_CNTL                               0x0058  
  80. #define CRTC_GEN_CNTL                          0x0050  
  81. #define MEM_CNTL                               0x0140  
  82. #define EXT_MEM_CNTL                           0x0144  
  83. #define MC_AGP_LOCATION                        0x014C  
  84. #define MEM_IO_CNTL_A0                         0x0178  
  85. #define MEM_INIT_LATENCY_TIMER                 0x0154  
  86. #define MEM_SDRAM_MODE_REG                     0x0158  
  87. #define AGP_BASE                               0x0170  
  88. #define MEM_IO_CNTL_A1                         0x017C  
  89. #define MEM_IO_CNTL_B0                         0x0180
  90. #define MEM_IO_CNTL_B1                         0x0184
  91. #define MC_DEBUG                               0x0188
  92. #define MC_STATUS                              0x0150  
  93. #define MEM_IO_OE_CNTL                         0x018C  
  94. #define MC_FB_LOCATION                         0x0148  
  95. #define HOST_PATH_CNTL                         0x0130  
  96. #define MEM_VGA_WP_SEL                         0x0038  
  97. #define MEM_VGA_RP_SEL                         0x003C  
  98. #define HDP_DEBUG                              0x0138  
  99. #define SW_SEMAPHORE                           0x013C
  100. #define CRTC2_GEN_CNTL                         0x03f8  
  101. #define CRTC2_DISPLAY_BASE_ADDR                0x033c
  102. #define SURFACE_CNTL                           0x0B00  
  103. #define SURFACE0_LOWER_BOUND                   0x0B04  
  104. #define SURFACE1_LOWER_BOUND                   0x0B14  
  105. #define SURFACE2_LOWER_BOUND                   0x0B24  
  106. #define SURFACE3_LOWER_BOUND                   0x0B34  
  107. #define SURFACE4_LOWER_BOUND                   0x0B44  
  108. #define SURFACE5_LOWER_BOUND                   0x0B54
  109. #define SURFACE6_LOWER_BOUND                   0x0B64
  110. #define SURFACE7_LOWER_BOUND                   0x0B74
  111. #define SURFACE0_UPPER_BOUND                   0x0B08  
  112. #define SURFACE1_UPPER_BOUND                   0x0B18  
  113. #define SURFACE2_UPPER_BOUND                   0x0B28  
  114. #define SURFACE3_UPPER_BOUND                   0x0B38  
  115. #define SURFACE4_UPPER_BOUND                   0x0B48  
  116. #define SURFACE5_UPPER_BOUND                   0x0B58  
  117. #define SURFACE6_UPPER_BOUND                   0x0B68  
  118. #define SURFACE7_UPPER_BOUND                   0x0B78  
  119. #define SURFACE0_INFO                          0x0B0C  
  120. #define SURFACE1_INFO                          0x0B1C  
  121. #define SURFACE2_INFO                          0x0B2C  
  122. #define SURFACE3_INFO                          0x0B3C  
  123. #define SURFACE4_INFO                          0x0B4C  
  124. #define SURFACE5_INFO                          0x0B5C  
  125. #define SURFACE6_INFO                          0x0B6C
  126. #define SURFACE7_INFO                          0x0B7C
  127. #define SURFACE_ACCESS_FLAGS                   0x0BF8
  128. #define SURFACE_ACCESS_CLR                     0x0BFC  
  129. #define GEN_INT_CNTL                           0x0040  
  130. #define GEN_INT_STATUS                         0x0044  
  131. #define CRTC_EXT_CNTL                          0x0054
  132. #define RB3D_CNTL        0x1C3C  
  133. #define WAIT_UNTIL                             0x1720  
  134. #define ISYNC_CNTL                             0x1724  
  135. #define RBBM_GUICNTL                           0x172C  
  136. #define RBBM_STATUS                            0x0E40  
  137. #define RBBM_STATUS_alt_1                      0x1740  
  138. #define RBBM_CNTL                              0x00EC  
  139. #define RBBM_CNTL_alt_1                        0x0E44  
  140. #define RBBM_SOFT_RESET                        0x00F0  
  141. #define RBBM_SOFT_RESET_alt_1                  0x0E48  
  142. #define NQWAIT_UNTIL                           0x0E50  
  143. #define RBBM_DEBUG                             0x0E6C
  144. #define RBBM_CMDFIFO_ADDR                      0x0E70
  145. #define RBBM_CMDFIFO_DATAL                     0x0E74
  146. #define RBBM_CMDFIFO_DATAH                     0x0E78  
  147. #define RBBM_CMDFIFO_STAT                      0x0E7C  
  148. #define CRTC_STATUS                            0x005C  
  149. #define GPIO_VGA_DDC                           0x0060  
  150. #define GPIO_DVI_DDC                           0x0064  
  151. #define GPIO_MONID                             0x0068  
  152. #define PALETTE_INDEX                          0x00B0  
  153. #define PALETTE_DATA                           0x00B4  
  154. #define PALETTE_30_DATA                        0x00B8  
  155. #define CRTC_H_TOTAL_DISP                      0x0200  
  156. #define CRTC_H_SYNC_STRT_WID                   0x0204  
  157. #define CRTC_V_TOTAL_DISP                      0x0208  
  158. #define CRTC_V_SYNC_STRT_WID                   0x020C  
  159. #define CRTC_VLINE_CRNT_VLINE                  0x0210  
  160. #define CRTC_CRNT_FRAME                        0x0214
  161. #define CRTC_GUI_TRIG_VLINE                    0x0218
  162. #define CRTC_DEBUG                             0x021C
  163. #define CRTC_OFFSET_RIGHT                      0x0220  
  164. #define CRTC_OFFSET                            0x0224  
  165. #define CRTC_OFFSET_CNTL                       0x0228  
  166. #define CRTC_PITCH                             0x022C  
  167. #define OVR_CLR                                0x0230  
  168. #define OVR_WID_LEFT_RIGHT                     0x0234  
  169. #define OVR_WID_TOP_BOTTOM                     0x0238  
  170. #define DISPLAY_BASE_ADDR                      0x023C  
  171. #define SNAPSHOT_VH_COUNTS                     0x0240  
  172. #define SNAPSHOT_F_COUNT                       0x0244  
  173. #define N_VIF_COUNT                            0x0248  
  174. #define SNAPSHOT_VIF_COUNT                     0x024C  
  175. #define FP_CRTC_H_TOTAL_DISP                   0x0250  
  176. #define FP_CRTC_V_TOTAL_DISP                   0x0254  
  177. #define CRT_CRTC_H_SYNC_STRT_WID               0x0258
  178. #define CRT_CRTC_V_SYNC_STRT_WID               0x025C
  179. #define CUR_OFFSET                             0x0260
  180. #define CUR_HORZ_VERT_POSN                     0x0264  
  181. #define CUR_HORZ_VERT_OFF                      0x0268  
  182. #define CUR_CLR0                               0x026C  
  183. #define CUR_CLR1                               0x0270  
  184. #define FP_HORZ_VERT_ACTIVE                    0x0278  
  185. #define CRTC_MORE_CNTL                         0x027C  
  186. #define DAC_EXT_CNTL                           0x0280  
  187. #define FP_GEN_CNTL                            0x0284  
  188. #define FP_HORZ_STRETCH                        0x028C  
  189. #define FP_VERT_STRETCH                        0x0290  
  190. #define FP_H_SYNC_STRT_WID                     0x02C4  
  191. #define FP_V_SYNC_STRT_WID                     0x02C8  
  192. #define AUX_WINDOW_HORZ_CNTL                   0x02D8  
  193. #define AUX_WINDOW_VERT_CNTL                   0x02DC  
  194. #define DDA_CONFIG        0x02e0
  195. #define DDA_ON_OFF        0x02e4
  196. #define GRPH_BUFFER_CNTL                       0x02F0
  197. #define VGA_BUFFER_CNTL                        0x02F4
  198. #define OV0_Y_X_START                          0x0400
  199. #define OV0_Y_X_END                            0x0404  
  200. #define OV0_PIPELINE_CNTL                      0x0408  
  201. #define OV0_REG_LOAD_CNTL                      0x0410  
  202. #define OV0_SCALE_CNTL                         0x0420  
  203. #define OV0_V_INC                              0x0424  
  204. #define OV0_P1_V_ACCUM_INIT                    0x0428  
  205. #define OV0_P23_V_ACCUM_INIT                   0x042C  
  206. #define OV0_P1_BLANK_LINES_AT_TOP              0x0430  
  207. #define OV0_P23_BLANK_LINES_AT_TOP             0x0434  
  208. #define OV0_BASE_ADDR                          0x043C  
  209. #define OV0_VID_BUF0_BASE_ADRS                 0x0440  
  210. #define OV0_VID_BUF1_BASE_ADRS                 0x0444  
  211. #define OV0_VID_BUF2_BASE_ADRS                 0x0448  
  212. #define OV0_VID_BUF3_BASE_ADRS                 0x044C  
  213. #define OV0_VID_BUF4_BASE_ADRS                 0x0450
  214. #define OV0_VID_BUF5_BASE_ADRS                 0x0454
  215. #define OV0_VID_BUF_PITCH0_VALUE               0x0460
  216. #define OV0_VID_BUF_PITCH1_VALUE               0x0464  
  217. #define OV0_AUTO_FLIP_CNTRL                    0x0470  
  218. #define OV0_DEINTERLACE_PATTERN                0x0474  
  219. #define OV0_SUBMIT_HISTORY                     0x0478  
  220. #define OV0_H_INC                              0x0480  
  221. #define OV0_STEP_BY                            0x0484  
  222. #define OV0_P1_H_ACCUM_INIT                    0x0488  
  223. #define OV0_P23_H_ACCUM_INIT                   0x048C  
  224. #define OV0_P1_X_START_END                     0x0494  
  225. #define OV0_P2_X_START_END                     0x0498  
  226. #define OV0_P3_X_START_END                     0x049C  
  227. #define OV0_FILTER_CNTL                        0x04A0  
  228. #define OV0_FOUR_TAP_COEF_0                    0x04B0  
  229. #define OV0_FOUR_TAP_COEF_1                    0x04B4  
  230. #define OV0_FOUR_TAP_COEF_2                    0x04B8
  231. #define OV0_FOUR_TAP_COEF_3                    0x04BC
  232. #define OV0_FOUR_TAP_COEF_4                    0x04C0
  233. #define OV0_FLAG_CNTRL                         0x04DC  
  234. #define OV0_SLICE_CNTL                         0x04E0  
  235. #define OV0_VID_KEY_CLR_LOW                    0x04E4  
  236. #define OV0_VID_KEY_CLR_HIGH                   0x04E8  
  237. #define OV0_GRPH_KEY_CLR_LOW                   0x04EC  
  238. #define OV0_GRPH_KEY_CLR_HIGH                  0x04F0  
  239. #define OV0_KEY_CNTL                           0x04F4  
  240. #define OV0_TEST                               0x04F8  
  241. #define SUBPIC_CNTL                            0x0540  
  242. #define SUBPIC_DEFCOLCON                       0x0544  
  243. #define SUBPIC_Y_X_START                       0x054C  
  244. #define SUBPIC_Y_X_END                         0x0550  
  245. #define SUBPIC_V_INC                           0x0554  
  246. #define SUBPIC_H_INC                           0x0558  
  247. #define SUBPIC_BUF0_OFFSET                     0x055C
  248. #define SUBPIC_BUF1_OFFSET                     0x0560
  249. #define SUBPIC_LC0_OFFSET                      0x0564
  250. #define SUBPIC_LC1_OFFSET                      0x0568  
  251. #define SUBPIC_PITCH                           0x056C  
  252. #define SUBPIC_BTN_HLI_COLCON                  0x0570  
  253. #define SUBPIC_BTN_HLI_Y_X_START               0x0574  
  254. #define SUBPIC_BTN_HLI_Y_X_END                 0x0578  
  255. #define SUBPIC_PALETTE_INDEX                   0x057C  
  256. #define SUBPIC_PALETTE_DATA                    0x0580  
  257. #define SUBPIC_H_ACCUM_INIT                    0x0584  
  258. #define SUBPIC_V_ACCUM_INIT                    0x0588  
  259. #define DISP_MISC_CNTL                         0x0D00  
  260. #define DAC_MACRO_CNTL                         0x0D04  
  261. #define DISP_PWR_MAN                           0x0D08  
  262. #define DISP_TEST_DEBUG_CNTL                   0x0D10  
  263. #define DISP_HW_DEBUG                          0x0D14  
  264. #define DAC_CRC_SIG1                           0x0D18
  265. #define DAC_CRC_SIG2                           0x0D1C
  266. #define OV0_LIN_TRANS_A                        0x0D20
  267. #define OV0_LIN_TRANS_B                        0x0D24  
  268. #define OV0_LIN_TRANS_C                        0x0D28  
  269. #define OV0_LIN_TRANS_D                        0x0D2C  
  270. #define OV0_LIN_TRANS_E                        0x0D30  
  271. #define OV0_LIN_TRANS_F                        0x0D34  
  272. #define OV0_GAMMA_0_F                          0x0D40  
  273. #define OV0_GAMMA_10_1F                        0x0D44  
  274. #define OV0_GAMMA_20_3F                        0x0D48  
  275. #define OV0_GAMMA_40_7F                        0x0D4C  
  276. #define OV0_GAMMA_380_3BF                      0x0D50  
  277. #define OV0_GAMMA_3C0_3FF                      0x0D54  
  278. #define DISP_MERGE_CNTL                        0x0D60  
  279. #define DISP_OUTPUT_CNTL                       0x0D64  
  280. #define DISP_LIN_TRANS_GRPH_A                  0x0D80  
  281. #define DISP_LIN_TRANS_GRPH_B                  0x0D84
  282. #define DISP_LIN_TRANS_GRPH_C                  0x0D88
  283. #define DISP_LIN_TRANS_GRPH_D                  0x0D8C
  284. #define DISP_LIN_TRANS_GRPH_E                  0x0D90  
  285. #define DISP_LIN_TRANS_GRPH_F                  0x0D94  
  286. #define DISP_LIN_TRANS_VID_A                   0x0D98  
  287. #define DISP_LIN_TRANS_VID_B                   0x0D9C  
  288. #define DISP_LIN_TRANS_VID_C                   0x0DA0  
  289. #define DISP_LIN_TRANS_VID_D                   0x0DA4  
  290. #define DISP_LIN_TRANS_VID_E                   0x0DA8  
  291. #define DISP_LIN_TRANS_VID_F                   0x0DAC  
  292. #define RMX_HORZ_FILTER_0TAP_COEF              0x0DB0  
  293. #define RMX_HORZ_FILTER_1TAP_COEF              0x0DB4  
  294. #define RMX_HORZ_FILTER_2TAP_COEF              0x0DB8  
  295. #define RMX_HORZ_PHASE                         0x0DBC  
  296. #define DAC_EMBEDDED_SYNC_CNTL                 0x0DC0  
  297. #define DAC_BROAD_PULSE                        0x0DC4  
  298. #define DAC_SKEW_CLKS                          0x0DC8
  299. #define DAC_INCR                               0x0DCC
  300. #define DAC_NEG_SYNC_LEVEL                     0x0DD0
  301. #define DAC_POS_SYNC_LEVEL                     0x0DD4  
  302. #define DAC_BLANK_LEVEL                        0x0DD8  
  303. #define CLOCK_CNTL_INDEX                       0x0008  
  304. #define CLOCK_CNTL_DATA                        0x000C  
  305. #define CP_RB_CNTL                             0x0704  
  306. #define CP_RB_BASE                             0x0700  
  307. #define CP_RB_RPTR_ADDR                        0x070C  
  308. #define CP_RB_RPTR                             0x0710  
  309. #define CP_RB_WPTR                             0x0714  
  310. #define CP_RB_WPTR_DELAY                       0x0718  
  311. #define CP_IB_BASE                             0x0738  
  312. #define CP_IB_BUFSZ                            0x073C  
  313. #define SCRATCH_REG0                           0x15E0  
  314. #define GUI_SCRATCH_REG0                       0x15E0  
  315. #define SCRATCH_REG1                           0x15E4  
  316. #define GUI_SCRATCH_REG1                       0x15E4  
  317. #define SCRATCH_REG2                           0x15E8
  318. #define GUI_SCRATCH_REG2                       0x15E8
  319. #define SCRATCH_REG3                           0x15EC
  320. #define GUI_SCRATCH_REG3                       0x15EC  
  321. #define SCRATCH_REG4                           0x15F0  
  322. #define GUI_SCRATCH_REG4                       0x15F0  
  323. #define SCRATCH_REG5                           0x15F4  
  324. #define GUI_SCRATCH_REG5                       0x15F4  
  325. #define SCRATCH_UMSK                           0x0770  
  326. #define SCRATCH_ADDR                           0x0774  
  327. #define DP_BRUSH_FRGD_CLR                      0x147C  
  328. #define DP_BRUSH_BKGD_CLR                      0x1478
  329. #define DST_LINE_START                         0x1600
  330. #define DST_LINE_END                           0x1604  
  331. #define SRC_OFFSET                             0x15AC  
  332. #define SRC_PITCH                              0x15B0
  333. #define SRC_TILE                               0x1704
  334. #define SRC_PITCH_OFFSET                       0x1428
  335. #define SRC_X                                  0x1414  
  336. #define SRC_Y                                  0x1418  
  337. #define SRC_X_Y                                0x1590  
  338. #define SRC_Y_X                                0x1434  
  339. #define DST_Y_X        0x1438
  340. #define DST_WIDTH_HEIGHT        0x1598
  341. #define DST_HEIGHT_WIDTH        0x143c
  342. #define DST_OFFSET                             0x1404
  343. #define SRC_CLUT_ADDRESS                       0x1780  
  344. #define SRC_CLUT_DATA                          0x1784  
  345. #define SRC_CLUT_DATA_RD                       0x1788  
  346. #define HOST_DATA0                             0x17C0  
  347. #define HOST_DATA1                             0x17C4  
  348. #define HOST_DATA2                             0x17C8  
  349. #define HOST_DATA3                             0x17CC  
  350. #define HOST_DATA4                             0x17D0  
  351. #define HOST_DATA5                             0x17D4  
  352. #define HOST_DATA6                             0x17D8  
  353. #define HOST_DATA7                             0x17DC
  354. #define HOST_DATA_LAST                         0x17E0
  355. #define DP_SRC_ENDIAN                          0x15D4
  356. #define DP_SRC_FRGD_CLR                        0x15D8  
  357. #define DP_SRC_BKGD_CLR                        0x15DC  
  358. #define SC_LEFT                                0x1640  
  359. #define SC_RIGHT                               0x1644  
  360. #define SC_TOP                                 0x1648  
  361. #define SC_BOTTOM                              0x164C  
  362. #define SRC_SC_RIGHT                           0x1654  
  363. #define SRC_SC_BOTTOM                          0x165C  
  364. #define DP_CNTL                                0x16C0  
  365. #define DP_CNTL_XDIR_YDIR_YMAJOR               0x16D0  
  366. #define DP_DATATYPE                            0x16C4  
  367. #define DP_MIX                                 0x16C8  
  368. #define DP_WRITE_MSK                           0x16CC  
  369. #define DP_XOP                                 0x17F8  
  370. #define CLR_CMP_CLR_SRC                        0x15C4
  371. #define CLR_CMP_CLR_DST                        0x15C8
  372. #define CLR_CMP_CNTL                           0x15C0
  373. #define CLR_CMP_MSK                            0x15CC  
  374. #define DSTCACHE_MODE                          0x1710  
  375. #define DSTCACHE_CTLSTAT                       0x1714  
  376. #define DEFAULT_PITCH_OFFSET                   0x16E0  
  377. #define DEFAULT_SC_BOTTOM_RIGHT                0x16E8  
  378. #define DP_GUI_MASTER_CNTL                     0x146C  
  379. #define SC_TOP_LEFT                            0x16EC  
  380. #define SC_BOTTOM_RIGHT                        0x16F0  
  381. #define SRC_SC_BOTTOM_RIGHT                    0x16F4  
  382. #define RB2D_DSTCACHE_CTLSTAT        0x342C
  383. #define LVDS_GEN_CNTL        0x02d0
  384. #define LVDS_PLL_CNTL        0x02d4
  385. #define TMDS_CRC        0x02a0
  386. #define TMDS_TRANSMITTER_CNTL        0x02a4
  388. #define RADEON_BASE_CODE        0x0f0b
  389. #define RADEON_BIOS_0_SCRATCH        0x0010
  390. #define RADEON_BIOS_1_SCRATCH        0x0014
  391. #define RADEON_BIOS_2_SCRATCH        0x0018
  392. #define RADEON_BIOS_3_SCRATCH        0x001c
  393. #define RADEON_BIOS_4_SCRATCH        0x0020
  394. #define RADEON_BIOS_5_SCRATCH        0x0024
  395. #define RADEON_BIOS_6_SCRATCH        0x0028
  396. #define RADEON_BIOS_7_SCRATCH        0x002c
  399. #define CLK_PIN_CNTL                               0x0001
  400. #define PPLL_CNTL                                  0x0002
  401. #define PPLL_REF_DIV                               0x0003
  402. #define PPLL_DIV_0                                 0x0004
  403. #define PPLL_DIV_1                                 0x0005
  404. #define PPLL_DIV_2                                 0x0006
  405. #define PPLL_DIV_3                                 0x0007
  406. #define VCLK_ECP_CNTL                              0x0008
  407. #define HTOTAL_CNTL                                0x0009
  408. #define M_SPLL_REF_FB_DIV                          0x000a
  409. #define AGP_PLL_CNTL                               0x000b
  410. #define SPLL_CNTL                                  0x000c
  411. #define SCLK_CNTL                                  0x000d
  412. #define MPLL_CNTL                                  0x000e
  413. #define MDLL_CKO                                   0x000f
  414. #define MCLK_CNTL                                  0x0012
  415. #define AGP_PLL_CNTL                               0x000b
  416. #define PLL_TEST_CNTL                              0x0013
  418. /* MCLK_CNTL bit constants */
  419. #define FORCEON_MCLKA    (1 << 16)
  420. #define FORCEON_MCLKB                 (1 << 17)
  421. #define FORCEON_YCLKA                      (1 << 18)
  422. #define FORCEON_YCLKB                 (1 << 19)
  423. #define FORCEON_MC                    (1 << 20)
  424. #define FORCEON_AIC                   (1 << 21)
  427. /* BUS_CNTL bit constants */
  428. #define BUS_DBL_RESYNC                             0x00000001
  429. #define BUS_MSTR_RESET                             0x00000002
  430. #define BUS_FLUSH_BUF                              0x00000004
  431. #define BUS_STOP_REQ_DIS                           0x00000008
  432. #define BUS_ROTATION_DIS                           0x00000010
  433. #define BUS_MASTER_DIS                             0x00000040
  434. #define BUS_ROM_WRT_EN                             0x00000080
  435. #define BUS_DIS_ROM                                0x00001000
  436. #define BUS_PCI_READ_RETRY_EN                      0x00002000
  437. #define BUS_AGP_AD_STEPPING_EN                     0x00004000
  438. #define BUS_PCI_WRT_RETRY_EN                       0x00008000
  439. #define BUS_MSTR_RD_MULT                           0x00100000
  440. #define BUS_MSTR_RD_LINE                           0x00200000
  441. #define BUS_SUSPEND                                0x00400000
  442. #define LAT_16X                                    0x00800000
  443. #define BUS_RD_DISCARD_EN                          0x01000000
  444. #define BUS_RD_ABORT_EN                            0x02000000
  445. #define BUS_MSTR_WS                                0x04000000
  446. #define BUS_PARKING_DIS                            0x08000000
  447. #define BUS_MSTR_DISCONNECT_EN                     0x10000000
  448. #define BUS_WRT_BURST                              0x20000000
  449. #define BUS_READ_BURST                             0x40000000
  450. #define BUS_RDY_READ_DLY                           0x80000000
  453. /* CLOCK_CNTL_INDEX bit constants */
  454. #define PLL_WR_EN                                  0x00000080
  456. /* CONFIG_CNTL bit constants */
  457. #define CFG_VGA_RAM_EN                             0x00000100
  459. /* CRTC_EXT_CNTL bit constants */
  460. #define VGA_ATI_LINEAR                             0x00000008
  461. #define VGA_128KAP_PAGING                          0x00000010
  462. #define XCRT_CNT_EN    (1 << 6)
  463. #define CRTC_HSYNC_DIS    (1 << 8)
  464. #define CRTC_VSYNC_DIS    (1 << 9)
  465. #define CRTC_DISPLAY_DIS    (1 << 10)
  466. #define CRTC_CRT_ON    (1 << 15)
  469. /* DSTCACHE_CTLSTAT bit constants */
  470. #define RB2D_DC_FLUSH    (3 << 0)
  471. #define RB2D_DC_FLUSH_ALL    0xf
  472. #define RB2D_DC_BUSY    (1 << 31)
  475. /* CRTC_GEN_CNTL bit constants */
  476. #define CRTC_DBL_SCAN_EN                           0x00000001
  477. #define CRTC_CUR_EN                                0x00010000
  478. #define CRTC_INTERLACE_EN    (1 << 1)
  479. #define CRTC_EXT_DISP_EN          (1 << 24)
  480. #define CRTC_EN    (1 << 25)
  481. #define CRTC_DISP_REQ_EN_B                         (1 << 26)
  483. /* CRTC_STATUS bit constants */
  484. #define CRTC_VBLANK                                0x00000001
  486. /* CRTC2_GEN_CNTL bit constants */
  487. #define CRT2_ON                                    (1 << 7)
  488. #define CRTC2_DISPLAY_DIS                          (1 << 23)
  489. #define CRTC2_EN                                   (1 << 25)
  490. #define CRTC2_DISP_REQ_EN_B                        (1 << 26)
  492. /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
  493. #define CUR_LOCK                                   0x80000000
  496. /* FP bit constants */
  497. #define FP_CRTC_H_TOTAL_MASK    0x000003ff
  498. #define FP_CRTC_H_DISP_MASK    0x01ff0000
  499. #define FP_CRTC_V_TOTAL_MASK    0x00000fff
  500. #define FP_CRTC_V_DISP_MASK    0x0fff0000
  501. #define FP_H_SYNC_STRT_CHAR_MASK    0x00001ff8
  502. #define FP_H_SYNC_WID_MASK    0x003f0000
  503. #define FP_V_SYNC_STRT_MASK    0x00000fff
  504. #define FP_V_SYNC_WID_MASK    0x001f0000
  505. #define FP_CRTC_H_TOTAL_SHIFT    0x00000000
  506. #define FP_CRTC_H_DISP_SHIFT    0x00000010
  507. #define FP_CRTC_V_TOTAL_SHIFT    0x00000000
  508. #define FP_CRTC_V_DISP_SHIFT    0x00000010
  509. #define FP_H_SYNC_STRT_CHAR_SHIFT    0x00000003
  510. #define FP_H_SYNC_WID_SHIFT    0x00000010
  511. #define FP_V_SYNC_STRT_SHIFT    0x00000000
  512. #define FP_V_SYNC_WID_SHIFT    0x00000010
  514. /* FP_GEN_CNTL bit constants */
  515. #define FP_FPON    (1 << 0)
  516. #define FP_TMDS_EN    (1 << 2)
  517. #define FP_EN_TMDS    (1 << 7)
  518. #define FP_DETECT_SENSE    (1 << 8)
  519. #define FP_SEL_CRTC2    (1 << 13)
  520. #define FP_CRTC_DONT_SHADOW_HPAR    (1 << 15)
  521. #define FP_CRTC_DONT_SHADOW_VPAR    (1 << 16)
  522. #define FP_CRTC_DONT_SHADOW_HEND    (1 << 17)
  523. #define FP_CRTC_USE_SHADOW_VEND    (1 << 18)
  524. #define FP_RMX_HVSYNC_CONTROL_EN    (1 << 20)
  525. #define FP_DFP_SYNC_SEL    (1 << 21)
  526. #define FP_CRTC_LOCK_8DOT    (1 << 22)
  527. #define FP_CRT_SYNC_SEL    (1 << 23)
  528. #define FP_USE_SHADOW_EN    (1 << 24)
  529. #define FP_CRT_SYNC_ALT    (1 << 26)
  531. /* LVDS_GEN_CNTL bit constants */
  532. #define LVDS_ON    (1 << 0)
  533. #define LVDS_DISPLAY_DIS    (1 << 1)
  534. #define LVDS_PANEL_TYPE    (1 << 2)
  535. #define LVDS_PANEL_FORMAT    (1 << 3)
  536. #define LVDS_EN    (1 << 7)
  537. #define LVDS_BL_MOD_LEVEL_MASK    0x0000ff00
  538. #define LVDS_BL_MOD_LEVEL_SHIFT    8
  539. #define LVDS_BL_MOD_EN    (1 << 16)
  540. #define LVDS_DIGON    (1 << 18)
  541. #define LVDS_BLON    (1 << 19)
  542. #define LVDS_SEL_CRTC2    (1 << 23)
  543. #define LVDS_STATE_MASK
  544. (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | 
  545.  LVDS_EN | LVDS_DIGON | LVDS_BLON)
  547. /* LVDS_PLL_CNTL bit constatns */
  548. #define HSYNC_DELAY_SHIFT    0x1c
  549. #define HSYNC_DELAY_MASK    (0xf << 0x1c)
  551. /* TMDS_TRANSMITTER_CNTL bit constants */
  552. #define TMDS_PLL_EN    (1 << 0)
  553. #define TMDS_PLLRST    (1 << 1)
  554. #define TMDS_RAN_PAT_RST    (1 << 7)
  555. #define ICHCSEL    (1 << 28)
  557. /* FP_HORZ_STRETCH bit constants */
  558. #define HORZ_STRETCH_RATIO_MASK    0xffff
  559. #define HORZ_STRETCH_RATIO_MAX    4096
  560. #define HORZ_PANEL_SIZE    (0x1ff << 16)
  561. #define HORZ_PANEL_SHIFT    16
  562. #define HORZ_STRETCH_PIXREP    (0 << 25)
  563. #define HORZ_STRETCH_BLEND    (1 << 26)
  564. #define HORZ_STRETCH_ENABLE    (1 << 25)
  565. #define HORZ_AUTO_RATIO    (1 << 27)
  566. #define HORZ_FP_LOOP_STRETCH    (0x7 << 28)
  567. #define HORZ_AUTO_RATIO_INC    (1 << 31)
  570. /* FP_VERT_STRETCH bit constants */
  571. #define VERT_STRETCH_RATIO_MASK    0xfff
  572. #define VERT_STRETCH_RATIO_MAX    4096
  573. #define VERT_PANEL_SIZE    (0xfff << 12)
  574. #define VERT_PANEL_SHIFT    12
  575. #define VERT_STRETCH_LINREP    (0 << 26)
  576. #define VERT_STRETCH_BLEND    (1 << 26)
  577. #define VERT_STRETCH_ENABLE    (1 << 25)
  578. #define VERT_AUTO_RATIO_EN    (1 << 27)
  579. #define VERT_FP_LOOP_STRETCH    (0x7 << 28)
  580. #define VERT_STRETCH_RESERVED    0xf1000000
  582. /* DAC_CNTL bit constants */   
  583. #define DAC_8BIT_EN                                0x00000100
  584. #define DAC_4BPP_PIX_ORDER                         0x00000200
  585. #define DAC_CRC_EN                                 0x00080000
  586. #define DAC_MASK_ALL    (0xff << 24)
  587. #define DAC_EXPAND_MODE    (1 << 14)
  588. #define DAC_VGA_ADR_EN    (1 << 13)
  589. #define DAC_RANGE_CNTL    (3 << 0)
  590. #define DAC_BLANKING    (1 << 2)
  592. /* GEN_RESET_CNTL bit constants */
  593. #define SOFT_RESET_GUI                             0x00000001
  594. #define SOFT_RESET_VCLK                            0x00000100
  595. #define SOFT_RESET_PCLK                            0x00000200
  596. #define SOFT_RESET_ECP                             0x00000400
  597. #define SOFT_RESET_DISPENG_XCLK                    0x00000800
  599. /* MEM_CNTL bit constants */
  600. #define MEM_CTLR_STATUS_IDLE                       0x00000000
  601. #define MEM_CTLR_STATUS_BUSY                       0x00100000
  602. #define MEM_SEQNCR_STATUS_IDLE                     0x00000000
  603. #define MEM_SEQNCR_STATUS_BUSY                     0x00200000
  604. #define MEM_ARBITER_STATUS_IDLE                    0x00000000
  605. #define MEM_ARBITER_STATUS_BUSY                    0x00400000
  606. #define MEM_REQ_UNLOCK                             0x00000000
  607. #define MEM_REQ_LOCK                               0x00800000
  610. /* RBBM_SOFT_RESET bit constants */
  611. #define SOFT_RESET_CP               (1 <<  0)
  612. #define SOFT_RESET_HI               (1 <<  1)
  613. #define SOFT_RESET_SE               (1 <<  2)
  614. #define SOFT_RESET_RE               (1 <<  3)
  615. #define SOFT_RESET_PP               (1 <<  4)
  616. #define SOFT_RESET_E2               (1 <<  5)
  617. #define SOFT_RESET_RB               (1 <<  6)
  618. #define SOFT_RESET_HDP              (1 <<  7)
  620. /* SURFACE_CNTL bit consants */
  621. #define SURF_TRANSLATION_DIS    (1 << 8)
  622. #define NONSURF_AP0_SWP_16BPP    (1 << 20)
  623. #define NONSURF_AP0_SWP_32BPP    (1 << 21)
  625. /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
  626. #define DEFAULT_SC_RIGHT_MAX    (0x1fff << 0)
  627. #define DEFAULT_SC_BOTTOM_MAX    (0x1fff << 16)
  629. /* MM_INDEX bit constants */
  630. #define MM_APER                                    0x80000000
  632. /* CLR_CMP_CNTL bit constants */
  633. #define COMPARE_SRC_FALSE                          0x00000000
  634. #define COMPARE_SRC_TRUE                           0x00000001
  635. #define COMPARE_SRC_NOT_EQUAL                      0x00000004
  636. #define COMPARE_SRC_EQUAL                          0x00000005
  637. #define COMPARE_SRC_EQUAL_FLIP                     0x00000007
  638. #define COMPARE_DST_FALSE                          0x00000000
  639. #define COMPARE_DST_TRUE                           0x00000100
  640. #define COMPARE_DST_NOT_EQUAL                      0x00000400
  641. #define COMPARE_DST_EQUAL                          0x00000500
  642. #define COMPARE_DESTINATION                        0x00000000
  643. #define COMPARE_SOURCE                             0x01000000
  644. #define COMPARE_SRC_AND_DST                        0x02000000
  647. /* DP_CNTL bit constants */
  648. #define DST_X_RIGHT_TO_LEFT                        0x00000000
  649. #define DST_X_LEFT_TO_RIGHT                        0x00000001
  650. #define DST_Y_BOTTOM_TO_TOP                        0x00000000
  651. #define DST_Y_TOP_TO_BOTTOM                        0x00000002
  652. #define DST_X_MAJOR                                0x00000000
  653. #define DST_Y_MAJOR                                0x00000004
  654. #define DST_X_TILE                                 0x00000008
  655. #define DST_Y_TILE                                 0x00000010
  656. #define DST_LAST_PEL                               0x00000020
  657. #define DST_TRAIL_X_RIGHT_TO_LEFT                  0x00000000
  658. #define DST_TRAIL_X_LEFT_TO_RIGHT                  0x00000040
  659. #define DST_TRAP_FILL_RIGHT_TO_LEFT                0x00000000
  660. #define DST_TRAP_FILL_LEFT_TO_RIGHT                0x00000080
  661. #define DST_BRES_SIGN                              0x00000100
  662. #define DST_HOST_BIG_ENDIAN_EN                     0x00000200
  663. #define DST_POLYLINE_NONLAST                       0x00008000
  664. #define DST_RASTER_STALL                           0x00010000
  665. #define DST_POLY_EDGE                              0x00040000
  668. /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
  669. #define DST_X_MAJOR_S                              0x00000000
  670. #define DST_Y_MAJOR_S                              0x00000001
  671. #define DST_Y_BOTTOM_TO_TOP_S                      0x00000000
  672. #define DST_Y_TOP_TO_BOTTOM_S                      0x00008000
  673. #define DST_X_RIGHT_TO_LEFT_S                      0x00000000
  674. #define DST_X_LEFT_TO_RIGHT_S                      0x80000000
  677. /* DP_DATATYPE bit constants */
  678. #define DST_8BPP                                   0x00000002
  679. #define DST_15BPP                                  0x00000003
  680. #define DST_16BPP                                  0x00000004
  681. #define DST_24BPP                                  0x00000005
  682. #define DST_32BPP                                  0x00000006
  683. #define DST_8BPP_RGB332                            0x00000007
  684. #define DST_8BPP_Y8                                0x00000008
  685. #define DST_8BPP_RGB8                              0x00000009
  686. #define DST_16BPP_VYUY422                          0x0000000b
  687. #define DST_16BPP_YVYU422                          0x0000000c
  688. #define DST_32BPP_AYUV444                          0x0000000e
  689. #define DST_16BPP_ARGB4444                         0x0000000f
  690. #define BRUSH_SOLIDCOLOR                           0x00000d00
  691. #define SRC_MONO                                   0x00000000
  692. #define SRC_MONO_LBKGD                             0x00010000
  693. #define SRC_DSTCOLOR                               0x00030000
  694. #define BYTE_ORDER_MSB_TO_LSB                      0x00000000
  695. #define BYTE_ORDER_LSB_TO_MSB                      0x40000000
  696. #define DP_CONVERSION_TEMP                         0x80000000
  697. #define HOST_BIG_ENDIAN_EN    (1 << 29)
  700. /* DP_GUI_MASTER_CNTL bit constants */
  701. #define GMC_SRC_PITCH_OFFSET_DEFAULT               0x00000000
  702. #define GMC_SRC_PITCH_OFFSET_LEAVE                 0x00000001
  703. #define GMC_DST_PITCH_OFFSET_DEFAULT               0x00000000
  704. #define GMC_DST_PITCH_OFFSET_LEAVE                 0x00000002
  705. #define GMC_SRC_CLIP_DEFAULT                       0x00000000
  706. #define GMC_SRC_CLIP_LEAVE                         0x00000004
  707. #define GMC_DST_CLIP_DEFAULT                       0x00000000
  708. #define GMC_DST_CLIP_LEAVE                         0x00000008
  709. #define GMC_BRUSH_8x8MONO                          0x00000000
  710. #define GMC_BRUSH_8x8MONO_LBKGD                    0x00000010
  711. #define GMC_BRUSH_8x1MONO                          0x00000020
  712. #define GMC_BRUSH_8x1MONO_LBKGD                    0x00000030
  713. #define GMC_BRUSH_1x8MONO                          0x00000040
  714. #define GMC_BRUSH_1x8MONO_LBKGD                    0x00000050
  715. #define GMC_BRUSH_32x1MONO                         0x00000060
  716. #define GMC_BRUSH_32x1MONO_LBKGD                   0x00000070
  717. #define GMC_BRUSH_32x32MONO                        0x00000080
  718. #define GMC_BRUSH_32x32MONO_LBKGD                  0x00000090
  719. #define GMC_BRUSH_8x8COLOR                         0x000000a0
  720. #define GMC_BRUSH_8x1COLOR                         0x000000b0
  721. #define GMC_BRUSH_1x8COLOR                         0x000000c0
  722. #define GMC_BRUSH_SOLID_COLOR                       0x000000d0
  723. #define GMC_DST_8BPP                               0x00000200
  724. #define GMC_DST_15BPP                              0x00000300
  725. #define GMC_DST_16BPP                              0x00000400
  726. #define GMC_DST_24BPP                              0x00000500
  727. #define GMC_DST_32BPP                              0x00000600
  728. #define GMC_DST_8BPP_RGB332                        0x00000700
  729. #define GMC_DST_8BPP_Y8                            0x00000800
  730. #define GMC_DST_8BPP_RGB8                          0x00000900
  731. #define GMC_DST_16BPP_VYUY422                      0x00000b00
  732. #define GMC_DST_16BPP_YVYU422                      0x00000c00
  733. #define GMC_DST_32BPP_AYUV444                      0x00000e00
  734. #define GMC_DST_16BPP_ARGB4444                     0x00000f00
  735. #define GMC_SRC_MONO                               0x00000000
  736. #define GMC_SRC_MONO_LBKGD                         0x00001000
  737. #define GMC_SRC_DSTCOLOR                           0x00003000
  738. #define GMC_BYTE_ORDER_MSB_TO_LSB                  0x00000000
  739. #define GMC_BYTE_ORDER_LSB_TO_MSB                  0x00004000
  740. #define GMC_DP_CONVERSION_TEMP_9300                0x00008000
  741. #define GMC_DP_CONVERSION_TEMP_6500                0x00000000
  742. #define GMC_DP_SRC_RECT                            0x02000000
  743. #define GMC_DP_SRC_HOST                            0x03000000
  744. #define GMC_DP_SRC_HOST_BYTEALIGN                  0x04000000
  745. #define GMC_3D_FCN_EN_CLR                          0x00000000
  746. #define GMC_3D_FCN_EN_SET                          0x08000000
  747. #define GMC_DST_CLR_CMP_FCN_LEAVE                  0x00000000
  748. #define GMC_DST_CLR_CMP_FCN_CLEAR                  0x10000000
  749. #define GMC_AUX_CLIP_LEAVE                         0x00000000
  750. #define GMC_AUX_CLIP_CLEAR                         0x20000000
  751. #define GMC_WRITE_MASK_LEAVE                       0x00000000
  752. #define GMC_WRITE_MASK_SET                         0x40000000
  753. #define GMC_CLR_CMP_CNTL_DIS          (1 << 28)
  754. #define GMC_SRC_DATATYPE_COLOR    (3 << 12)
  755. #define ROP3_S                    0x00cc0000
  756. #define ROP3_SRCCOPY    0x00cc0000
  757. #define ROP3_P                    0x00f00000
  758. #define ROP3_PATCOPY    0x00f00000
  759. #define DP_SRC_SOURCE_MASK            (7    << 24)
  760. #define GMC_BRUSH_NONE                (15   <<  4)
  761. #define DP_SRC_SOURCE_MEMORY    (2    << 24)
  762. #define GMC_BRUSH_SOLIDCOLOR    0x000000d0
  764. /* DP_MIX bit constants */
  765. #define DP_SRC_RECT                                0x00000200
  766. #define DP_SRC_HOST                                0x00000300
  767. #define DP_SRC_HOST_BYTEALIGN                      0x00000400
  769. /* MPLL_CNTL bit constants */
  770. #define MPLL_RESET                                 0x00000001
  772. /* MDLL_CKO bit constants */
  773. #define MDLL_CKO__MCKOA_RESET                      0x00000002
  775. /* VCLK_ECP_CNTL constants */
  776. #define PIXCLK_ALWAYS_ONb                          0x00000040
  777. #define PIXCLK_DAC_ALWAYS_ONb                      0x00000080
  779. /* masks */
  781. #define CONFIG_MEMSIZE_MASK 0x1f000000
  782. #define MEM_CFG_TYPE 0x40000000
  783. #define DST_OFFSET_MASK 0x003fffff
  784. #define DST_PITCH_MASK 0x3fc00000
  785. #define DEFAULT_TILE_MASK 0xc0000000
  786. #define PPLL_DIV_SEL_MASK 0x00000300
  787. #define PPLL_RESET 0x00000001
  788. #define PPLL_ATOMIC_UPDATE_EN 0x00010000
  789. #define PPLL_REF_DIV_MASK 0x000003ff
  790. #define PPLL_FB3_DIV_MASK 0x000007ff
  791. #define PPLL_POST3_DIV_MASK 0x00070000
  792. #define PPLL_ATOMIC_UPDATE_R 0x00008000
  793. #define PPLL_ATOMIC_UPDATE_W 0x00008000
  794. #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
  796. #define GUI_ACTIVE 0x80000000
  798. #endif /* _RADEON_H */