开通博客赚积分
发布资源赚积分
分类

源码开发语言/平台
当前位置：首页 > 源码/资料 > 嵌入式/单片机编程 > 嵌入式Linux > 查看源码
ips.h
资源名称：SBC-2410X_kernel.tar.gz　[点击查看]
上传用户：lgb322
上传日期：2013-02-24
资源大小：30529k
文件大小：39k
源码类别：

嵌入式Linux

开发平台：

Unix_Linux

ips.h：源码内容
  1. /*****************************************************************************/
  2. /* ips.h -- driver for the IBM ServeRAID controller                          */
  3. /*                                                                           */
  4. /* Written By: Keith Mitchell, IBM Corporation                               */
  5. /*                                                                           */
  6. /* Copyright (C) 1999 IBM Corporation                                        */
  7. /*                                                                           */
  8. /* This program is free software; you can redistribute it and/or modify      */
  9. /* it under the terms of the GNU General Public License as published by      */
  10. /* the Free Software Foundation; either version 2 of the License, or         */
  11. /* (at your option) any later version.                                       */
  12. /*                                                                           */
  13. /* This program is distributed in the hope that it will be useful,           */
  14. /* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
  15. /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             */
  16. /* GNU General Public License for more details.                              */
  17. /*                                                                           */
  18. /* NO WARRANTY                                                               */
  19. /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR        */
  20. /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT      */
  21. /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,      */
  22. /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is    */
  23. /* solely responsible for determining the appropriateness of using and       */
  24. /* distributing the Program and assumes all risks associated with its        */
  25. /* exercise of rights under this Agreement, including but not limited to     */
  26. /* the risks and costs of program errors, damage to or loss of data,         */
  27. /* programs or equipment, and unavailability or interruption of operations.  */
  28. /*                                                                           */
  29. /* DISCLAIMER OF LIABILITY                                                   */
  30. /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY   */
  31. /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL        */
  32. /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND   */
  33. /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR     */
  34. /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE    */
  35. /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED  */
  36. /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES             */
  37. /*                                                                           */
  38. /* You should have received a copy of the GNU General Public License         */
  39. /* along with this program; if not, write to the Free Software               */
  40. /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */
  41. /*                                                                           */
  42. /* Bugs/Comments/Suggestions should be mailed to:                            */
  43. /*      ipslinux@us.ibm.com                                                  */
  44. /*                                                                           */
  45. /*****************************************************************************/
  47. #ifndef _IPS_H_
  48.    #define _IPS_H_
  50.    #include <asm/uaccess.h>
  51.    #include <asm/io.h>
  53.    /* type definitions */
  54.    #define u_int8_t  uint8_t
  55.    #define u_int16_t uint16_t
  56.    #define u_int32_t uint32_t
  57.    #define u_int64_t uint64_t
  59.    /* Prototypes */
  60.    extern int ips_detect(Scsi_Host_Template *);
  61.    extern int ips_release(struct Scsi_Host *);
  62.    extern int ips_eh_abort(Scsi_Cmnd *);
  63.    extern int ips_eh_reset(Scsi_Cmnd *);
  64.    extern int ips_queue(Scsi_Cmnd *, void (*) (Scsi_Cmnd *));
  65.    extern int ips_biosparam(Disk *, kdev_t, int *);
  66.    extern const char * ips_info(struct Scsi_Host *);
  67.    extern void do_ipsintr(int, void *, struct pt_regs *);
  69.    /*
  70.     * Some handy macros
  71.     */
  72.    #ifndef LinuxVersionCode
  73.       #define LinuxVersionCode(x,y,z)  (((x)<<16)+((y)<<8)+(z))
  74.    #endif
  76.    #define IPS_HA(x)                   ((ips_ha_t *) x->hostdata)
  77.    #define IPS_COMMAND_ID(ha, scb)     (int) (scb - ha->scbs)
  78.    #define IPS_IS_TROMBONE(ha)         (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && 
  79.                                          (ha->revision_id >= IPS_REVID_TROMBONE32) && 
  80.                                          (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
  81.    #define IPS_IS_CLARINET(ha)         (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && 
  82.                                          (ha->revision_id >= IPS_REVID_CLARINETP1) && 
  83.                                          (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
  84.    #define IPS_IS_MORPHEUS(ha)         (ha->device_id == IPS_DEVICEID_MORPHEUS)
  85.    #define IPS_USE_I2O_DELIVER(ha)     ((IPS_IS_MORPHEUS(ha) || 
  86.                                          (IPS_IS_TROMBONE(ha) && 
  87.                                           (ips_force_i2o))) ? 1 : 0)
  88.    #define IPS_USE_I2O_STATUS(ha)      (IPS_IS_MORPHEUS(ha))
  89.    #define IPS_USE_MEMIO(ha)           ((IPS_IS_MORPHEUS(ha) || 
  90.                                          ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && 
  91.                                           (ips_force_memio))) ? 1 : 0)
  93.    #ifndef VIRT_TO_BUS
  94.       #define VIRT_TO_BUS(x)           (unsigned int)virt_to_bus((void *) x)
  95.    #endif
  97.    #ifndef UDELAY
  98.       #define UDELAY udelay
  99.    #endif
  101.    #ifndef MDELAY
  102.       #define MDELAY mdelay
  103.    #endif
  105.    #ifndef verify_area_20
  106.       #define verify_area_20(t,a,sz)   (0) /* success */
  107.    #endif
  109.    #ifndef DECLARE_MUTEX_LOCKED
  110.       #define DECLARE_MUTEX_LOCKED(sem) struct semaphore sem = MUTEX_LOCKED;
  111.    #endif
  112.    
  113.    /*
  114.     * Lock macros
  115.     */
  116.    #define IPS_SCB_LOCK(cpu_flags)      spin_lock_irqsave(&ha->scb_lock, cpu_flags)
  117.    #define IPS_SCB_UNLOCK(cpu_flags)    spin_unlock_irqrestore(&ha->scb_lock, cpu_flags)
  118.    #define IPS_QUEUE_LOCK(queue)        spin_lock_irqsave(&(queue)->lock, (queue)->cpu_flags)
  119.    #define IPS_QUEUE_UNLOCK(queue)      spin_unlock_irqrestore(&(queue)->lock, (queue)->cpu_flags)
  120.    #define IPS_HA_LOCK(cpu_flags)       spin_lock_irqsave(&ha->ips_lock, cpu_flags)
  121.    #define IPS_HA_UNLOCK(cpu_flags)     spin_unlock_irqrestore(&ha->ips_lock, cpu_flags)
  123.    /*
  124.     * Adapter address map equates
  125.     */
  126.    #define IPS_REG_HISR                 0x08    /* Host Interrupt Status Reg   */
  127.    #define IPS_REG_CCSAR                0x10    /* Cmd Channel System Addr Reg */
  128.    #define IPS_REG_CCCR                 0x14    /* Cmd Channel Control Reg     */
  129.    #define IPS_REG_SQHR                 0x20    /* Status Q Head Reg           */
  130.    #define IPS_REG_SQTR                 0x24    /* Status Q Tail Reg           */
  131.    #define IPS_REG_SQER                 0x28    /* Status Q End Reg            */
  132.    #define IPS_REG_SQSR                 0x2C    /* Status Q Start Reg          */
  133.    #define IPS_REG_SCPR                 0x05    /* Subsystem control port reg  */
  134.    #define IPS_REG_ISPR                 0x06    /* interrupt status port reg   */
  135.    #define IPS_REG_CBSP                 0x07    /* CBSP register               */
  136.    #define IPS_REG_FLAP                 0x18    /* Flash address port          */
  137.    #define IPS_REG_FLDP                 0x1C    /* Flash data port             */
  138.    #define IPS_REG_NDAE                 0x38    /* Anaconda 64 NDAE Register   */
  139.    #define IPS_REG_I2O_INMSGQ           0x40    /* I2O Inbound Message Queue   */
  140.    #define IPS_REG_I2O_OUTMSGQ          0x44    /* I2O Outbound Message Queue  */
  141.    #define IPS_REG_I2O_HIR              0x30    /* I2O Interrupt Status        */
  142.    #define IPS_REG_I960_IDR             0x20    /* i960 Inbound Doorbell       */
  143.    #define IPS_REG_I960_MSG0            0x18    /* i960 Outbound Reg 0         */
  144.    #define IPS_REG_I960_MSG1            0x1C    /* i960 Outbound Reg 1         */
  145.    #define IPS_REG_I960_OIMR            0x34    /* i960 Oubound Int Mask Reg   */
  147.    /*
  148.     * Adapter register bit equates
  149.     */
  150.    #define IPS_BIT_GHI                  0x04    /* HISR General Host Interrupt */
  151.    #define IPS_BIT_SQO                  0x02    /* HISR Status Q Overflow      */
  152.    #define IPS_BIT_SCE                  0x01    /* HISR Status Channel Enqueue */
  153.    #define IPS_BIT_SEM                  0x08    /* CCCR Semaphore Bit          */
  154.    #define IPS_BIT_ILE                  0x10    /* CCCR ILE Bit                */
  155.    #define IPS_BIT_START_CMD            0x101A  /* CCCR Start Command Channel  */
  156.    #define IPS_BIT_START_STOP           0x0002  /* CCCR Start/Stop Bit         */
  157.    #define IPS_BIT_RST                  0x80    /* SCPR Reset Bit              */
  158.    #define IPS_BIT_EBM                  0x02    /* SCPR Enable Bus Master      */
  159.    #define IPS_BIT_EI                   0x80    /* HISR Enable Interrupts      */
  160.    #define IPS_BIT_OP                   0x01    /* OP bit in CBSP              */
  161.    #define IPS_BIT_I2O_OPQI             0x08    /* General Host Interrupt      */
  162.    #define IPS_BIT_I960_MSG0I           0x01    /* Message Register 0 Interrupt*/
  163.    #define IPS_BIT_I960_MSG1I           0x02    /* Message Register 1 Interrupt*/
  165.    /*
  166.     * Adapter Command ID Equates
  167.     */
  168.    #define IPS_CMD_GET_LD_INFO          0x19
  169.    #define IPS_CMD_GET_SUBSYS           0x40
  170.    #define IPS_CMD_READ_CONF            0x38
  171.    #define IPS_CMD_RW_NVRAM_PAGE        0xBC
  172.    #define IPS_CMD_READ                 0x02
  173.    #define IPS_CMD_WRITE                0x03
  174.    #define IPS_CMD_FFDC                 0xD7
  175.    #define IPS_CMD_ENQUIRY              0x05
  176.    #define IPS_CMD_FLUSH                0x0A
  177.    #define IPS_CMD_READ_SG              0x82
  178.    #define IPS_CMD_WRITE_SG             0x83
  179.    #define IPS_CMD_DCDB                 0x04
  180.    #define IPS_CMD_DCDB_SG              0x84
  181.    #define IPS_CMD_CONFIG_SYNC          0x58
  182.    #define IPS_CMD_ERROR_TABLE          0x17
  183.    #define IPS_CMD_RW_BIOSFW            0x22
  185.    /*
  186.     * Adapter Equates
  187.     */
  188.    #define IPS_CSL                      0xFF
  189.    #define IPS_POCL                     0x30
  190.    #define IPS_NORM_STATE               0x00
  191.    #define IPS_MAX_ADAPTERS             16
  192.    #define IPS_MAX_IOCTL                1
  193.    #define IPS_MAX_IOCTL_QUEUE          8
  194.    #define IPS_MAX_QUEUE                128
  195.    #define IPS_BLKSIZE                  512
  196.    #define IPS_MAX_SG                   17
  197.    #define IPS_MAX_LD                   8
  198.    #define IPS_MAX_CHANNELS             4
  199.    #define IPS_MAX_TARGETS              15
  200.    #define IPS_MAX_CHUNKS               16
  201.    #define IPS_MAX_CMDS                 128
  202.    #define IPS_MAX_XFER                 0x10000
  203.    #define IPS_NVRAM_P5_SIG             0xFFDDBB99
  204.    #define IPS_MAX_POST_BYTES           0x02
  205.    #define IPS_MAX_CONFIG_BYTES         0x02
  206.    #define IPS_GOOD_POST_STATUS         0x80
  207.    #define IPS_SEM_TIMEOUT              2000
  208.    #define IPS_IOCTL_COMMAND            0x0D
  209.    #define IPS_IOCTL_NEW_COMMAND        0x81
  210.    #define IPS_INTR_ON                  0
  211.    #define IPS_INTR_IORL                1
  212.    #define IPS_INTR_HAL                 2
  213.    #define IPS_ADAPTER_ID               0xF
  214.    #define IPS_VENDORID                 0x1014
  215.    #define IPS_DEVICEID_COPPERHEAD      0x002E
  216.    #define IPS_DEVICEID_MORPHEUS        0x01BD
  217.    #define IPS_SUBDEVICEID_4M           0x01BE
  218.    #define IPS_SUBDEVICEID_4L           0x01BF
  219.    #define IPS_SUBDEVICEID_4MX          0x0208
  220.    #define IPS_SUBDEVICEID_4LX          0x020E
  221.    #define IPS_IOCTL_SIZE               8192
  222.    #define IPS_STATUS_SIZE              4
  223.    #define IPS_STATUS_Q_SIZE            (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
  224.    #define IPS_IMAGE_SIZE               500 * 1024
  225.    #define IPS_MEMMAP_SIZE              128
  226.    #define IPS_ONE_MSEC                 1
  227.    #define IPS_ONE_SEC                  1000
  229.    /*
  230.     * Geometry Settings
  231.     */
  232.    #define IPS_COMP_HEADS               128
  233.    #define IPS_COMP_SECTORS             32
  234.    #define IPS_NORM_HEADS               254
  235.    #define IPS_NORM_SECTORS             63
  237.    /*
  238.     * Adapter Basic Status Codes
  239.     */
  240.    #define IPS_BASIC_STATUS_MASK        0xFF
  241.    #define IPS_GSC_STATUS_MASK          0x0F
  242.    #define IPS_CMD_SUCCESS              0x00
  243.    #define IPS_CMD_RECOVERED_ERROR      0x01
  244.    #define IPS_INVAL_OPCO               0x03
  245.    #define IPS_INVAL_CMD_BLK            0x04
  246.    #define IPS_INVAL_PARM_BLK           0x05
  247.    #define IPS_BUSY                     0x08
  248.    #define IPS_CMD_CMPLT_WERROR         0x0C
  249.    #define IPS_LD_ERROR                 0x0D
  250.    #define IPS_CMD_TIMEOUT              0x0E
  251.    #define IPS_PHYS_DRV_ERROR           0x0F
  253.    /*
  254.     * Adapter Extended Status Equates
  255.     */
  256.    #define IPS_ERR_SEL_TO               0xF0
  257.    #define IPS_ERR_OU_RUN               0xF2
  258.    #define IPS_ERR_HOST_RESET           0xF7
  259.    #define IPS_ERR_DEV_RESET            0xF8
  260.    #define IPS_ERR_RECOVERY             0xFC
  261.    #define IPS_ERR_CKCOND               0xFF
  263.    /*
  264.     * Operating System Defines
  265.     */
  266.    #define IPS_OS_WINDOWS_NT            0x01
  267.    #define IPS_OS_NETWARE               0x02
  268.    #define IPS_OS_OPENSERVER            0x03
  269.    #define IPS_OS_UNIXWARE              0x04
  270.    #define IPS_OS_SOLARIS               0x05
  271.    #define IPS_OS_OS2                   0x06
  272.    #define IPS_OS_LINUX                 0x07
  273.    #define IPS_OS_FREEBSD               0x08
  275.    /*
  276.     * Adapter Revision ID's
  277.     */
  278.    #define IPS_REVID_SERVERAID          0x02
  279.    #define IPS_REVID_NAVAJO             0x03
  280.    #define IPS_REVID_SERVERAID2         0x04
  281.    #define IPS_REVID_CLARINETP1         0x05
  282.    #define IPS_REVID_CLARINETP2         0x07
  283.    #define IPS_REVID_CLARINETP3         0x0D
  284.    #define IPS_REVID_TROMBONE32         0x0F
  285.    #define IPS_REVID_TROMBONE64         0x10
  287.    /*
  288.     * NVRAM Page 5 Adapter Defines
  289.     */
  290.    #define IPS_ADTYPE_SERVERAID         0x01
  291.    #define IPS_ADTYPE_SERVERAID2        0x02
  292.    #define IPS_ADTYPE_NAVAJO            0x03
  293.    #define IPS_ADTYPE_KIOWA             0x04
  294.    #define IPS_ADTYPE_SERVERAID3        0x05
  295.    #define IPS_ADTYPE_SERVERAID3L       0x06
  296.    #define IPS_ADTYPE_SERVERAID4H       0x07
  297.    #define IPS_ADTYPE_SERVERAID4M       0x08
  298.    #define IPS_ADTYPE_SERVERAID4L       0x09
  299.    #define IPS_ADTYPE_SERVERAID4MX      0x0A
  300.    #define IPS_ADTYPE_SERVERAID4LX      0x0B
  302.    /*
  303.     * Adapter Command/Status Packet Definitions
  304.     */
  305.    #define IPS_SUCCESS                  0x01 /* Successfully completed       */
  306.    #define IPS_SUCCESS_IMM              0x02 /* Success - Immediately        */
  307.    #define IPS_FAILURE                  0x04 /* Completed with Error         */
  309.    /*
  310.     * Logical Drive Equates
  311.     */
  312.    #define IPS_LD_OFFLINE               0x02
  313.    #define IPS_LD_OKAY                  0x03
  314.    #define IPS_LD_FREE                  0x00
  315.    #define IPS_LD_SYS                   0x06
  316.    #define IPS_LD_CRS                   0x24
  318.    /*
  319.     * DCDB Table Equates
  320.     */
  321.    #define IPS_NO_DISCONNECT            0x00
  322.    #define IPS_DISCONNECT_ALLOWED       0x80
  323.    #define IPS_NO_AUTO_REQSEN           0x40
  324.    #define IPS_DATA_NONE                0x00
  325.    #define IPS_DATA_UNK                 0x00
  326.    #define IPS_DATA_IN                  0x01
  327.    #define IPS_DATA_OUT                 0x02
  328.    #define IPS_TRANSFER64K              0x08
  329.    #define IPS_NOTIMEOUT                0x00
  330.    #define IPS_TIMEOUT10                0x10
  331.    #define IPS_TIMEOUT60                0x20
  332.    #define IPS_TIMEOUT20M               0x30
  334.    /*
  335.     * SCSI Inquiry Data Flags
  336.     */
  337.    #define IPS_SCSI_INQ_TYPE_DASD       0x00
  338.    #define IPS_SCSI_INQ_TYPE_PROCESSOR  0x03
  339.    #define IPS_SCSI_INQ_LU_CONNECTED    0x00
  340.    #define IPS_SCSI_INQ_RD_REV2         0x02
  341.    #define IPS_SCSI_INQ_REV2            0x02
  342.    #define IPS_SCSI_INQ_REV3            0x03
  343.    #define IPS_SCSI_INQ_Address16       0x01
  344.    #define IPS_SCSI_INQ_Address32       0x02
  345.    #define IPS_SCSI_INQ_MedChanger      0x08
  346.    #define IPS_SCSI_INQ_MultiPort       0x10
  347.    #define IPS_SCSI_INQ_EncServ         0x40
  348.    #define IPS_SCSI_INQ_SoftReset       0x01
  349.    #define IPS_SCSI_INQ_CmdQue          0x02
  350.    #define IPS_SCSI_INQ_Linked          0x08
  351.    #define IPS_SCSI_INQ_Sync            0x10
  352.    #define IPS_SCSI_INQ_WBus16          0x20
  353.    #define IPS_SCSI_INQ_WBus32          0x40
  354.    #define IPS_SCSI_INQ_RelAdr          0x80
  356.    /*
  357.     * SCSI Request Sense Data Flags
  358.     */
  359.    #define IPS_SCSI_REQSEN_VALID        0x80
  360.    #define IPS_SCSI_REQSEN_CURRENT_ERR  0x70
  361.    #define IPS_SCSI_REQSEN_NO_SENSE     0x00
  363.    /*
  364.     * SCSI Mode Page Equates
  365.     */
  366.    #define IPS_SCSI_MP3_SoftSector      0x01
  367.    #define IPS_SCSI_MP3_HardSector      0x02
  368.    #define IPS_SCSI_MP3_Removeable      0x04
  369.    #define IPS_SCSI_MP3_AllocateSurface 0x08
  371.    /*
  372.     * Configuration Structure Flags
  373.     */
  374.    #define IPS_CFG_USEROPT_UPDATECOUNT(cfg)   (((cfg)->UserOpt & 0xffff000) >> 16)
  375.    #define IPS_CFG_USEROPT_CONCURSTART(cfg)   (((cfg)->UserOpt & 0xf000) >> 12)
  376.    #define IPS_CFG_USEROPT_STARTUPDELAY(cfg)  (((cfg)->UserOpt & 0xf00) >> 8)
  377.    #define IPS_CFG_USEROPT_REARRANGE(cfg)     ((cfg)->UserOpt & 0x80)
  378.    #define IPS_CFG_USEROPT_CDBOOT(cfg)        ((cfg)->UserOpt & 0x40)
  379.    #define IPS_CFG_USEROPT_CLUSTER(cfg)       ((cfg)->UserOpt & 0x20)
  381.    /*
  382.     * Host adapter Flags (bit numbers)
  383.     */
  384.    #define IPS_IN_INTR                  0
  385.    #define IPS_IN_ABORT                 1
  386.    #define IPS_IN_RESET                 2
  388.    /*
  389.     * SCB Flags
  390.     */
  391.    #define IPS_SCB_ACTIVE               0x00001
  392.    #define IPS_SCB_WAITING              0x00002
  394.    /*
  395.     * Passthru stuff
  396.     */
  397.    #define IPS_COPPUSRCMD              (('C'<<8) | 65)
  398.    #define IPS_COPPIOCCMD              (('C'<<8) | 66)
  399.    #define IPS_NUMCTRLS                (('C'<<8) | 68)
  400.    #define IPS_CTRLINFO                (('C'<<8) | 69)
  401.    #define IPS_FLASHBIOS               (('C'<<8) | 70)
  403.    /* time oriented stuff */
  404.    #define IPS_IS_LEAP_YEAR(y)           (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
  405.    #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
  407.    #define IPS_SECS_MIN                 60
  408.    #define IPS_SECS_HOUR                3600
  409.    #define IPS_SECS_8HOURS              28800
  410.    #define IPS_SECS_DAY                 86400
  411.    #define IPS_DAYS_NORMAL_YEAR         365
  412.    #define IPS_DAYS_LEAP_YEAR           366
  413.    #define IPS_EPOCH_YEAR               1970
  415.    /*
  416.     * Scsi_Host Template
  417.     */
  418. #if LINUX_VERSION_CODE < LinuxVersionCode(2,3,27)
  419.  #define IPS {                            
  420.     next : NULL,                          
  421.     module : NULL,                        
  422.     proc_info : NULL,                     
  423.     proc_dir : NULL,                      
  424.     name : NULL,                          
  425.     detect : ips_detect,                  
  426.     release : ips_release,                
  427.     info : ips_info,                      
  428.     command : NULL,                       
  429.     queuecommand : ips_queue,             
  430.     eh_strategy_handler : NULL,           
  431.     eh_abort_handler : ips_eh_abort,      
  432.     eh_device_reset_handler : NULL,       
  433.     eh_bus_reset_handler : NULL,          
  434.     eh_host_reset_handler : ips_eh_reset, 
  435.     abort : NULL,                         
  436.     reset : NULL,                         
  437.     slave_attach : NULL,                  
  438.     bios_param : ips_biosparam,           
  439.     can_queue : 0,                        
  440.     this_id: -1,                          
  441.     sg_tablesize : IPS_MAX_SG,            
  442.     cmd_per_lun: 16,                      
  443.     present : 0,                          
  444.     unchecked_isa_dma : 0,                
  445.     use_clustering : ENABLE_CLUSTERING,   
  446.     use_new_eh_code : 1                   
  447. }
  448. #else
  449.  #define IPS {                            
  450.     next : NULL,                          
  451.     module : NULL,                        
  452.     proc_info : NULL,                     
  453.     name : NULL,                          
  454.     detect : ips_detect,                  
  455.     release : ips_release,                
  456.     info : ips_info,                      
  457.     command : NULL,                       
  458.     queuecommand : ips_queue,             
  459.     eh_strategy_handler : NULL,           
  460.     eh_abort_handler : ips_eh_abort,      
  461.     eh_device_reset_handler : NULL,       
  462.     eh_bus_reset_handler : NULL,          
  463.     eh_host_reset_handler : ips_eh_reset, 
  464.     abort : NULL,                         
  465.     reset : NULL,                         
  466.     slave_attach : NULL,                  
  467.     bios_param : ips_biosparam,           
  468.     can_queue : 0,                        
  469.     this_id: -1,                          
  470.     sg_tablesize : IPS_MAX_SG,            
  471.     cmd_per_lun: 16,                      
  472.     present : 0,                          
  473.     unchecked_isa_dma : 0,                
  474.     use_clustering : ENABLE_CLUSTERING,   
  475.     use_new_eh_code : 1                   
  476. }
  477. #endif
  479. /*
  480.  * IBM PCI Raid Command Formats
  481.  */
  482. typedef struct {
  483.    u_int8_t  op_code;
  484.    u_int8_t  command_id;
  485.    u_int8_t  log_drv;
  486.    u_int8_t  sg_count;
  487.    u_int32_t lba;
  488.    u_int32_t sg_addr;
  489.    u_int16_t sector_count;
  490.    u_int16_t reserved;
  491.    u_int32_t ccsar;
  492.    u_int32_t cccr;
  493. } IPS_IO_CMD, *PIPS_IO_CMD;
  495. typedef struct {
  496.    u_int8_t  op_code;
  497.    u_int8_t  command_id;
  498.    u_int16_t reserved;
  499.    u_int32_t reserved2;
  500.    u_int32_t buffer_addr;
  501.    u_int32_t reserved3;
  502.    u_int32_t ccsar;
  503.    u_int32_t cccr;
  504. } IPS_LD_CMD, *PIPS_LD_CMD;
  506. typedef struct {
  507.    u_int8_t  op_code;
  508.    u_int8_t  command_id;
  509.    u_int8_t  reserved;
  510.    u_int8_t  reserved2;
  511.    u_int32_t reserved3;
  512.    u_int32_t buffer_addr;
  513.    u_int32_t reserved4;
  514. } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
  516. typedef struct {
  517.    u_int8_t  op_code;
  518.    u_int8_t  command_id;
  519.    u_int16_t reserved;
  520.    u_int32_t reserved2;
  521.    u_int32_t dcdb_address;
  522.    u_int32_t reserved3;
  523.    u_int32_t ccsar;
  524.    u_int32_t cccr;
  525. } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
  527. typedef struct {
  528.    u_int8_t  op_code;
  529.    u_int8_t  command_id;
  530.    u_int8_t  channel;
  531.    u_int8_t  source_target;
  532.    u_int32_t reserved;
  533.    u_int32_t reserved2;
  534.    u_int32_t reserved3;
  535.    u_int32_t ccsar;
  536.    u_int32_t cccr;
  537. } IPS_CS_CMD, *PIPS_CS_CMD;
  539. typedef struct {
  540.    u_int8_t  op_code;
  541.    u_int8_t  command_id;
  542.    u_int8_t  log_drv;
  543.    u_int8_t  control;
  544.    u_int32_t reserved;
  545.    u_int32_t reserved2;
  546.    u_int32_t reserved3;
  547.    u_int32_t ccsar;
  548.    u_int32_t cccr;
  549. } IPS_US_CMD, *PIPS_US_CMD;
  551. typedef struct {
  552.    u_int8_t  op_code;
  553.    u_int8_t  command_id;
  554.    u_int8_t  reserved;
  555.    u_int8_t  state;
  556.    u_int32_t reserved2;
  557.    u_int32_t reserved3;
  558.    u_int32_t reserved4;
  559.    u_int32_t ccsar;
  560.    u_int32_t cccr;
  561. } IPS_FC_CMD, *PIPS_FC_CMD;
  563. typedef struct {
  564.    u_int8_t  op_code;
  565.    u_int8_t  command_id;
  566.    u_int8_t  reserved;
  567.    u_int8_t  desc;
  568.    u_int32_t reserved2;
  569.    u_int32_t buffer_addr;
  570.    u_int32_t reserved3;
  571.    u_int32_t ccsar;
  572.    u_int32_t cccr;
  573. } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
  575. typedef struct {
  576.    u_int8_t  op_code;
  577.    u_int8_t  command_id;
  578.    u_int8_t  page;
  579.    u_int8_t  write;
  580.    u_int32_t reserved;
  581.    u_int32_t buffer_addr;
  582.    u_int32_t reserved2;
  583.    u_int32_t ccsar;
  584.    u_int32_t cccr;
  585. } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
  587. typedef struct {
  588.    u_int8_t  op_code;
  589.    u_int8_t  command_id;
  590.    u_int8_t  reset_count;
  591.    u_int8_t  reset_type;
  592.    u_int8_t  second;
  593.    u_int8_t  minute;
  594.    u_int8_t  hour;
  595.    u_int8_t  day;
  596.    u_int8_t  reserved1[4];
  597.    u_int8_t  month;
  598.    u_int8_t  yearH;
  599.    u_int8_t  yearL;
  600.    u_int8_t  reserved2;
  601. } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
  603. typedef struct {
  604.    u_int8_t  op_code;
  605.    u_int8_t  command_id;
  606.    u_int8_t  type;
  607.    u_int8_t  direction;
  608.    u_int32_t count;
  609.    u_int32_t buffer_addr;
  610.    u_int8_t  total_packets;
  611.    u_int8_t  packet_num;
  612.    u_int16_t reserved;
  613. } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
  615. typedef struct {
  616.    u_int8_t  op_code;
  617.    u_int8_t  command_id;
  618.    u_int8_t  type;
  619.    u_int8_t  direction;
  620.    u_int32_t count;
  621.    u_int32_t buffer_addr;
  622.    u_int32_t offset;
  623. } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
  625. typedef union {
  626.    IPS_IO_CMD        basic_io;
  627.    IPS_LD_CMD        logical_info;
  628.    IPS_IOCTL_CMD     ioctl_info;
  629.    IPS_DCDB_CMD      dcdb;
  630.    IPS_CS_CMD        config_sync;
  631.    IPS_US_CMD        unlock_stripe;
  632.    IPS_FC_CMD        flush_cache;
  633.    IPS_STATUS_CMD    status;
  634.    IPS_NVRAM_CMD     nvram;
  635.    IPS_FFDC_CMD      ffdc;
  636.    IPS_FLASHFW_CMD    flashfw;
  637.    IPS_FLASHBIOS_CMD  flashbios;
  638. } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
  640. typedef struct {
  641.    u_int8_t  logical_id;
  642.    u_int8_t  reserved;
  643.    u_int8_t  raid_level;
  644.    u_int8_t  state;
  645.    u_int32_t sector_count;
  646. } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
  648. typedef struct {
  649.    u_int8_t       no_of_log_drive;
  650.    u_int8_t       reserved[3];
  651.    IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
  652. } IPS_LD_INFO, *PIPS_LD_INFO;
  654. typedef struct {
  655.    u_int8_t   device_address;
  656.    u_int8_t   cmd_attribute;
  657.    u_int16_t  transfer_length;
  658.    u_int32_t  buffer_pointer;
  659.    u_int8_t   cdb_length;
  660.    u_int8_t   sense_length;
  661.    u_int8_t   sg_count;
  662.    u_int8_t   reserved;
  663.    u_int8_t   scsi_cdb[12];
  664.    u_int8_t   sense_info[64];
  665.    u_int8_t   scsi_status;
  666.    u_int8_t   reserved2[3];
  667. } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
  669. typedef union {
  670.    struct {
  671.       volatile u_int8_t  reserved;
  672.       volatile u_int8_t  command_id;
  673.       volatile u_int8_t  basic_status;
  674.       volatile u_int8_t  extended_status;
  675.    } fields;
  677.    volatile u_int32_t    value;
  678. } IPS_STATUS, *PIPS_STATUS;
  680. typedef struct {
  681.    IPS_STATUS           status[IPS_MAX_CMDS + 1];
  682.    volatile PIPS_STATUS p_status_start;
  683.    volatile PIPS_STATUS p_status_end;
  684.    volatile PIPS_STATUS p_status_tail;
  685.    volatile u_int32_t   hw_status_start;
  686.    volatile u_int32_t   hw_status_tail;
  687.    IPS_LD_INFO          logical_drive_info;
  688. } IPS_ADAPTER, *PIPS_ADAPTER;
  690. typedef struct {
  691.    u_int8_t  ucLogDriveCount;
  692.    u_int8_t  ucMiscFlag;
  693.    u_int8_t  ucSLTFlag;
  694.    u_int8_t  ucBSTFlag;
  695.    u_int8_t  ucPwrChgCnt;
  696.    u_int8_t  ucWrongAdrCnt;
  697.    u_int8_t  ucUnidentCnt;
  698.    u_int8_t  ucNVramDevChgCnt;
  699.    u_int8_t  CodeBlkVersion[8];
  700.    u_int8_t  BootBlkVersion[8];
  701.    u_int32_t ulDriveSize[IPS_MAX_LD];
  702.    u_int8_t  ucConcurrentCmdCount;
  703.    u_int8_t  ucMaxPhysicalDevices;
  704.    u_int16_t usFlashRepgmCount;
  705.    u_int8_t  ucDefunctDiskCount;
  706.    u_int8_t  ucRebuildFlag;
  707.    u_int8_t  ucOfflineLogDrvCount;
  708.    u_int8_t  ucCriticalDrvCount;
  709.    u_int16_t usConfigUpdateCount;
  710.    u_int8_t  ucBlkFlag;
  711.    u_int8_t  reserved;
  712.    u_int16_t usAddrDeadDisk[IPS_MAX_CHANNELS * IPS_MAX_TARGETS];
  713. } IPS_ENQ, *PIPS_ENQ;
  715. typedef struct {
  716.    u_int8_t  ucInitiator;
  717.    u_int8_t  ucParameters;
  718.    u_int8_t  ucMiscFlag;
  719.    u_int8_t  ucState;
  720.    u_int32_t ulBlockCount;
  721.    u_int8_t  ucDeviceId[28];
  722. } IPS_DEVSTATE, *PIPS_DEVSTATE;
  724. typedef struct {
  725.    u_int8_t  ucChn;
  726.    u_int8_t  ucTgt;
  727.    u_int16_t ucReserved;
  728.    u_int32_t ulStartSect;
  729.    u_int32_t ulNoOfSects;
  730. } IPS_CHUNK, *PIPS_CHUNK;
  732. typedef struct {
  733.    u_int16_t ucUserField;
  734.    u_int8_t  ucState;
  735.    u_int8_t  ucRaidCacheParam;
  736.    u_int8_t  ucNoOfChunkUnits;
  737.    u_int8_t  ucStripeSize;
  738.    u_int8_t  ucParams;
  739.    u_int8_t  ucReserved;
  740.    u_int32_t ulLogDrvSize;
  741.    IPS_CHUNK chunk[IPS_MAX_CHUNKS];
  742. } IPS_LD, *PIPS_LD;
  744. typedef struct {
  745.    u_int8_t  board_disc[8];
  746.    u_int8_t  processor[8];
  747.    u_int8_t  ucNoChanType;
  748.    u_int8_t  ucNoHostIntType;
  749.    u_int8_t  ucCompression;
  750.    u_int8_t  ucNvramType;
  751.    u_int32_t ulNvramSize;
  752. } IPS_HARDWARE, *PIPS_HARDWARE;
  754. typedef struct {
  755.    u_int8_t       ucLogDriveCount;
  756.    u_int8_t       ucDateD;
  757.    u_int8_t       ucDateM;
  758.    u_int8_t       ucDateY;
  759.    u_int8_t       init_id[4];
  760.    u_int8_t       host_id[12];
  761.    u_int8_t       time_sign[8];
  762.    u_int32_t      UserOpt;
  763.    u_int16_t      user_field;
  764.    u_int8_t       ucRebuildRate;
  765.    u_int8_t       ucReserve;
  766.    IPS_HARDWARE   hardware_disc;
  767.    IPS_LD         logical_drive[IPS_MAX_LD];
  768.    IPS_DEVSTATE   dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
  769.    u_int8_t       reserved[512];
  770. } IPS_CONF, *PIPS_CONF;
  772. typedef struct {
  773.    u_int32_t  signature;
  774.    u_int8_t   reserved;
  775.    u_int8_t   adapter_slot;
  776.    u_int16_t  adapter_type;
  777.    u_int8_t   bios_high[4];
  778.    u_int8_t   bios_low[4];
  779.    u_int16_t  reserved2;
  780.    u_int8_t   reserved3;
  781.    u_int8_t   operating_system;
  782.    u_int8_t   driver_high[4];
  783.    u_int8_t   driver_low[4];
  784.    u_int8_t   reserved4[100];
  785. } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
  787. typedef struct _IPS_SUBSYS {
  788.    u_int32_t  param[128];
  789. } IPS_SUBSYS, *PIPS_SUBSYS;
  791. /**
  792.  ** SCSI Structures
  793.  **/
  795. /*
  796.  * Inquiry Data Format
  797.  */
  798. typedef struct {
  799.    u_int8_t  DeviceType;
  800.    u_int8_t  DeviceTypeQualifier;
  801.    u_int8_t  Version;
  802.    u_int8_t  ResponseDataFormat;
  803.    u_int8_t  AdditionalLength;
  804.    u_int8_t  Reserved;
  805.    u_int8_t  Flags[2];
  806.    char      VendorId[8];
  807.    char      ProductId[16];
  808.    char      ProductRevisionLevel[4];
  809. } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
  811. /*
  812.  * Read Capacity Data Format
  813.  */
  814. typedef struct {
  815.    u_int32_t lba;
  816.    u_int32_t len;
  817. } IPS_SCSI_CAPACITY;
  819. /*
  820.  * Request Sense Data Format
  821.  */
  822. typedef struct {
  823.    u_int8_t  ResponseCode;
  824.    u_int8_t  SegmentNumber;
  825.    u_int8_t  Flags;
  826.    u_int8_t  Information[4];
  827.    u_int8_t  AdditionalLength;
  828.    u_int8_t  CommandSpecific[4];
  829.    u_int8_t  AdditionalSenseCode;
  830.    u_int8_t  AdditionalSenseCodeQual;
  831.    u_int8_t  FRUCode;
  832.    u_int8_t  SenseKeySpecific[3];
  833. } IPS_SCSI_REQSEN;
  835. /*
  836.  * Sense Data Format - Page 3
  837.  */
  838. typedef struct {
  839.    u_int8_t  PageCode;
  840.    u_int8_t  PageLength;
  841.    u_int16_t TracksPerZone;
  842.    u_int16_t AltSectorsPerZone;
  843.    u_int16_t AltTracksPerZone;
  844.    u_int16_t AltTracksPerVolume;
  845.    u_int16_t SectorsPerTrack;
  846.    u_int16_t BytesPerSector;
  847.    u_int16_t Interleave;
  848.    u_int16_t TrackSkew;
  849.    u_int16_t CylinderSkew;
  850.    u_int8_t  flags;
  851.    u_int8_t  reserved[3];
  852. } IPS_SCSI_MODE_PAGE3;
  854. /*
  855.  * Sense Data Format - Page 4
  856.  */
  857. typedef struct {
  858.    u_int8_t  PageCode;
  859.    u_int8_t  PageLength;
  860.    u_int16_t CylindersHigh;
  861.    u_int8_t  CylindersLow;
  862.    u_int8_t  Heads;
  863.    u_int16_t WritePrecompHigh;
  864.    u_int8_t  WritePrecompLow;
  865.    u_int16_t ReducedWriteCurrentHigh;
  866.    u_int8_t  ReducedWriteCurrentLow;
  867.    u_int16_t StepRate;
  868.    u_int16_t LandingZoneHigh;
  869.    u_int8_t  LandingZoneLow;
  870.    u_int8_t  flags;
  871.    u_int8_t  RotationalOffset;
  872.    u_int8_t  Reserved;
  873.    u_int16_t MediumRotationRate;
  874.    u_int8_t  Reserved2[2];
  875. } IPS_SCSI_MODE_PAGE4;
  877. /*
  878.  * Sense Data Format - Block Descriptor (DASD)
  879.  */
  880. typedef struct {
  881.    u_int32_t NumberOfBlocks;
  882.    u_int8_t  DensityCode;
  883.    u_int16_t BlockLengthHigh;
  884.    u_int8_t  BlockLengthLow;
  885. } IPS_SCSI_MODE_PAGE_BLKDESC;
  887. /*
  888.  * Sense Data Format - Mode Page Header
  889.  */
  890. typedef struct {
  891.    u_int8_t  DataLength;
  892.    u_int8_t  MediumType;
  893.    u_int8_t  Reserved;
  894.    u_int8_t  BlockDescLength;
  895. } IPS_SCSI_MODE_PAGE_HEADER;
  897. typedef struct {
  898.    IPS_SCSI_MODE_PAGE_HEADER  hdr;
  899.    IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
  901.    union {
  902.       IPS_SCSI_MODE_PAGE3 pg3;
  903.       IPS_SCSI_MODE_PAGE4 pg4;
  904.    } pdata;
  905. } IPS_SCSI_MODE_PAGE_DATA;
  907. /*
  908.  * Scatter Gather list format
  909.  */
  910. typedef struct ips_sglist {
  911.    u_int32_t address;
  912.    u_int32_t length;
  913. } IPS_SG_LIST, *PIPS_SG_LIST;
  915. typedef struct _IPS_INFOSTR {
  916.    char *buffer;
  917.    int   length;
  918.    int   offset;
  919.    int   pos;
  920.    int   localpos;
  921. } IPS_INFOSTR;
  923. typedef struct {
  924.    char *option_name;
  925.    int  *option_flag;
  926.    int   option_value;
  927. } IPS_OPTION;
  929. typedef struct {
  930.    void             *userbuffer;
  931.    u_int32_t         usersize;
  932.    void             *kernbuffer;
  933.    u_int32_t         kernsize;
  934.    void             *ha;
  935.    void             *SC;
  936.    void             *pt;
  937.    struct semaphore *sem;
  938.    u_int32_t         offset;
  939.    u_int32_t         retcode;
  940. } IPS_FLASH_DATA;
  942. /*
  943.  * Status Info
  944.  */
  945. typedef struct ips_stat {
  946.    u_int32_t residue_len;
  947.    void     *scb_addr;
  948.    u_int8_t  padding[12 - sizeof(void *)];
  949. } ips_stat_t;
  951. /*
  952.  * SCB Queue Format
  953.  */
  954. typedef struct ips_scb_queue {
  955.    struct ips_scb *head;
  956.    struct ips_scb *tail;
  957.    u_int32_t       count;
  958.    u_int32_t       cpu_flags;
  959.    spinlock_t      lock;
  960. } ips_scb_queue_t;
  962. /*
  963.  * Wait queue_format
  964.  */
  965. typedef struct ips_wait_queue {
  966.    Scsi_Cmnd      *head;
  967.    Scsi_Cmnd      *tail;
  968.    u_int32_t       count;
  969.    u_int32_t       cpu_flags;
  970.    spinlock_t      lock;
  971. } ips_wait_queue_t;
  973. typedef struct ips_copp_wait_item {
  974.    Scsi_Cmnd                 *scsi_cmd;
  975.    struct semaphore          *sem;
  976.    struct ips_copp_wait_item *next;
  977. } ips_copp_wait_item_t;
  979. typedef struct ips_copp_queue {
  980.    struct ips_copp_wait_item *head;
  981.    struct ips_copp_wait_item *tail;
  982.    u_int32_t                  count;
  983.    u_int32_t                  cpu_flags;
  984.    spinlock_t                 lock;
  985. } ips_copp_queue_t;
  987. /* forward decl for host structure */
  988. struct ips_ha;
  990. typedef struct {
  991.    int       (*reset)(struct ips_ha *);
  992.    int       (*issue)(struct ips_ha *, struct ips_scb *);
  993.    int       (*isinit)(struct ips_ha *);
  994.    int       (*isintr)(struct ips_ha *);
  995.    int       (*init)(struct ips_ha *);
  996.    int       (*erasebios)(struct ips_ha *);
  997.    int       (*programbios)(struct ips_ha *, char *, u_int32_t, u_int32_t);
  998.    int       (*verifybios)(struct ips_ha *, char *, u_int32_t, u_int32_t);
  999.    void      (*statinit)(struct ips_ha *);
  1000.    void      (*intr)(struct ips_ha *);
  1001.    void      (*enableint)(struct ips_ha *);
  1002.    u_int32_t (*statupd)(struct ips_ha *);
  1003. } ips_hw_func_t;
  1005. typedef struct ips_ha {
  1006.    u_int8_t           ha_id[IPS_MAX_CHANNELS+1];
  1007.    u_int32_t          dcdb_active[IPS_MAX_CHANNELS];
  1008.    u_int32_t          io_addr;            /* Base I/O address           */
  1009.    u_int8_t           irq;                /* IRQ for adapter            */
  1010.    u_int8_t           ntargets;           /* Number of targets          */
  1011.    u_int8_t           nbus;               /* Number of buses            */
  1012.    u_int8_t           nlun;               /* Number of Luns             */
  1013.    u_int16_t          ad_type;            /* Adapter type               */
  1014.    u_int16_t          host_num;           /* Adapter number             */
  1015.    u_int32_t          max_xfer;           /* Maximum Xfer size          */
  1016.    u_int32_t          max_cmds;           /* Max concurrent commands    */
  1017.    u_int32_t          num_ioctl;          /* Number of Ioctls           */
  1018.    ips_stat_t         sp;                 /* Status packer pointer      */
  1019.    struct ips_scb    *scbs;               /* Array of all CCBS          */
  1020.    struct ips_scb    *scb_freelist;       /* SCB free list              */
  1021.    ips_wait_queue_t   scb_waitlist;       /* Pending SCB list           */
  1022.    ips_copp_queue_t   copp_waitlist;      /* Pending PT list            */
  1023.    ips_scb_queue_t    scb_activelist;     /* Active SCB list            */
  1024.    IPS_IO_CMD        *dummy;              /* dummy command              */
  1025.    IPS_ADAPTER       *adapt;              /* Adapter status area        */
  1026.    IPS_ENQ           *enq;                /* Adapter Enquiry data       */
  1027.    IPS_CONF          *conf;               /* Adapter config data        */
  1028.    IPS_NVRAM_P5      *nvram;              /* NVRAM page 5 data          */
  1029.    IPS_SUBSYS        *subsys;             /* Subsystem parameters       */
  1030.    char              *ioctl_data;         /* IOCTL data area            */
  1031.    u_int32_t          ioctl_datasize;     /* IOCTL data size            */
  1032.    u_int32_t          cmd_in_progress;    /* Current command in progress*/
  1033.    unsigned long      flags;              /* HA flags                   */
  1034.    u_int8_t           waitflag;           /* are we waiting for cmd     */
  1035.    u_int8_t           active;
  1036.    u_int16_t          reset_count;        /* number of resets           */
  1037.    u_int32_t          last_ffdc;          /* last time we sent ffdc info*/
  1038.    u_int8_t           revision_id;        /* Revision level             */
  1039.    u_int16_t          device_id;          /* PCI device ID              */
  1040.    u_int8_t           slot_num;           /* PCI Slot Number            */
  1041.    u_int16_t          subdevice_id;       /* Subsystem device ID        */
  1042.    u_int8_t           ioctl_order;        /* Number of pages in ioctl   */
  1043.    u_int8_t           reserved2;          /* Empty                      */
  1044.    u_int8_t           bios_version[8];    /* BIOS Revision              */
  1045.    u_int32_t          mem_addr;           /* Memory mapped address      */
  1046.    u_int32_t          io_len;             /* Size of IO Address         */
  1047.    u_int32_t          mem_len;            /* Size of memory address     */
  1048.    char              *mem_ptr;            /* Memory mapped Ptr          */
  1049.    char              *ioremap_ptr;        /* ioremapped memory pointer  */
  1050.    ips_hw_func_t      func;               /* hw function pointers       */
  1051.    struct pci_dev    *pcidev;             /* PCI device handle          */
  1052.    spinlock_t         scb_lock;
  1053.    spinlock_t         copp_lock;
  1054.    spinlock_t         ips_lock;
  1055.    struct semaphore   ioctl_sem;          /* Semaphore for new IOCTL's  */
  1056.    struct semaphore   flash_ioctl_sem;    /* Semaphore for Flashing     */
  1057.    char              *save_ioctl_data;    /* Save Area for ioctl_data   */
  1058.    u8                 save_ioctl_order;   /* Save Area for ioctl_order  */
  1059.    u32                save_ioctl_datasize;/* Save Area for ioctl_datasize */
  1060. } ips_ha_t;
  1062. typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
  1064. /*
  1065.  * SCB Format
  1066.  */
  1067. typedef struct ips_scb {
  1068.    IPS_HOST_COMMAND  cmd;
  1069.    IPS_DCDB_TABLE    dcdb;
  1070.    u_int8_t          target_id;
  1071.    u_int8_t          bus;
  1072.    u_int8_t          lun;
  1073.    u_int8_t          cdb[12];
  1074.    u_int32_t         scb_busaddr;
  1075.    u_int32_t         data_busaddr;
  1076.    u_int32_t         timeout;
  1077.    u_int8_t          basic_status;
  1078.    u_int8_t          extended_status;
  1079.    u_int8_t          breakup;
  1080.    u_int8_t          sg_break;
  1081.    u_int32_t         data_len;
  1082.    u_int32_t         sg_len;
  1083.    u_int32_t         flags;
  1084.    u_int32_t         op_code;
  1085.    IPS_SG_LIST      *sg_list;
  1086.    Scsi_Cmnd        *scsi_cmd;
  1087.    struct ips_scb   *q_next;
  1088.    ips_scb_callback  callback;
  1089.    struct semaphore *sem;
  1090. } ips_scb_t;
  1092. typedef struct ips_scb_pt {
  1093.    IPS_HOST_COMMAND  cmd;
  1094.    IPS_DCDB_TABLE    dcdb;
  1095.    u_int8_t          target_id;
  1096.    u_int8_t          bus;
  1097.    u_int8_t          lun;
  1098.    u_int8_t          cdb[12];
  1099.    u_int32_t         scb_busaddr;
  1100.    u_int32_t         data_busaddr;
  1101.    u_int32_t         timeout;
  1102.    u_int8_t          basic_status;
  1103.    u_int8_t          extended_status;
  1104.    u_int16_t         breakup;
  1105.    u_int32_t         data_len;
  1106.    u_int32_t         sg_len;
  1107.    u_int32_t         flags;
  1108.    u_int32_t         op_code;
  1109.    IPS_SG_LIST      *sg_list;
  1110.    Scsi_Cmnd        *scsi_cmd;
  1111.    struct ips_scb   *q_next;
  1112.    ips_scb_callback  callback;
  1113. } ips_scb_pt_t;
  1115. /*
  1116.  * Passthru Command Format
  1117.  */
  1118. typedef struct {
  1119.    u_int8_t      CoppID[4];
  1120.    u_int32_t     CoppCmd;
  1121.    u_int32_t     PtBuffer;
  1122.    u_int8_t     *CmdBuffer;
  1123.    u_int32_t     CmdBSize;
  1124.    ips_scb_pt_t  CoppCP;
  1125.    u_int32_t     TimeOut;
  1126.    u_int8_t      BasicStatus;
  1127.    u_int8_t      ExtendedStatus;
  1128.    u_int16_t     reserved;
  1129. } ips_passthru_t;
  1131. #endif
  1133. /*
  1134.  * Overrides for Emacs so that we almost follow Linus's tabbing style.
  1135.  * Emacs will notice this stuff at the end of the file and automatically
  1136.  * adjust the settings for this buffer only.  This must remain at the end
  1137.  * of the file.
  1138.  * ---------------------------------------------------------------------------
  1139.  * Local variables:
  1140.  * c-indent-level: 2
  1141.  * c-brace-imaginary-offset: 0
  1142.  * c-brace-offset: -2
  1143.  * c-argdecl-indent: 2
  1144.  * c-label-offset: -2
  1145.  * c-continued-statement-offset: 2
  1146.  * c-continued-brace-offset: 0
  1147.  * indent-tabs-mode: nil
  1148.  * tab-width: 8
  1149.  * End:
  1150.  */