VHDL/FPGA/Verilog

开发平台：

C/C++

使用变量的状态机.txt：源码内容

							-- State Machine using Variable
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
ENTITY fsm2 IS
    PORT(clock,x : IN BIT; z : OUT BIT);
END fsm2;
-------------------------------------------------
ARCHITECTURE using_wait OF fsm2 IS
TYPE state_type IS (s0,s1,s2,s3);
BEGIN
   PROCESS
      VARIABLE state : state_type := s0;
   BEGIN
      WAIT UNTIL (clock'EVENT AND clock = '1');
         CASE state IS
            WHEN s0 => IF x = '0' THEN 
                           state := s0;
                           z <= '0';
                       ELSE
                           state := s2;
                           z <= '1';
                       END IF;
            WHEN s2 => IF x = '0' THEN 
                           state := s2;
                           z <= '1';
                       ELSE
                           state := s3;
                           z <= '0';
                       END IF;
            WHEN s3 => IF x = '0' THEN 
                           state := s3;
                           z <= '0';
                       ELSE
                           state := s1;
                           z <= '1';
                       END IF;
            WHEN s1 => IF x = '0' THEN 
                           state := s0;
                           z <= '0';
                       ELSE
                           state := s2;
                           z <= '0';
                       END IF;
            
         END CASE;
   END PROCESS;
END using_wait;

						