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pci.h
资源名称：linux-2.4.20.tar.gz　[点击查看]
上传用户：jlfgdled
上传日期：2013-04-10
资源大小：33168k
文件大小：7k
源码类别：

Linux/Unix编程

开发平台：

Unix_Linux

pci.h：源码内容
  1. /* PCI.h - PCI functions header file */
  3. /* Copyright - Galileo technology. */
  5. #ifndef  __INCpcih
  6. #define  __INCpcih
  8. /* includes */
  10. #include"core.h"
  12. /* defines */
  14. #define PCI0_MASTER_ENABLE(deviceNumber) pci0WriteConfigReg(                  
  15.           PCI_0STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                
  16.           pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  18. #define PCI0_MASTER_DISABLE(deviceNumber) pci0WriteConfigReg(                 
  19.           PCI_0STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               
  20.           pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  22. #define PCI1_MASTER_ENABLE(deviceNumber) pci1WriteConfigReg(                  
  23.           PCI_0STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                
  24.           pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  26. #define PCI1_MASTER_DISABLE(deviceNumber) pci1WriteConfigReg(                 
  27.           PCI_0STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               
  28.           pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  30. #define PCI0_MEMORY_ENABLE(deviceNumber) pci0WriteConfigReg(                  
  31.           PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                
  32.           pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  34. #define PCI1_MEMORY_ENABLE(deviceNumber) pci1WriteConfigReg(                  
  35.           PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                
  36.           pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  38. #define PCI0_IO_ENABLE(deviceNumber) pci0WriteConfigReg(                      
  39.           PCI_0STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   
  40.           pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  42. #define PCI1_IO_ENABLE(deviceNumber) pci1WriteConfigReg(                      
  43.           PCI_0STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   
  44.           pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  46. #define PCI0_SLAVE_ENABLE(deviceNumber) pci0WriteConfigReg(                   
  47.           PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   
  48.           pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  50. #define PCI1_SLAVE_ENABLE(deviceNumber) pci1WriteConfigReg(                   
  51.           PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   
  52.           pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
  54. #define PCI0_DISABLE(deviceNumber) pci0WriteConfigReg(                        
  55.           PCI_0STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  
  56.           pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber))
  58. #define PCI1_DISABLE(deviceNumber) pci1WriteConfigReg(                        
  59.           PCI_0STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  
  60.           pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber))
  62. #define  MASTER_ENABLE BIT2
  63. #define MEMORY_ENABLE BIT1
  64. #define I_O_ENABLE   BIT0
  65. #define     SELF                    0
  66. /* Agent on the PCI bus may have up to 6 BARS. */
  67. #define     BAR0                    0x10
  68. #define     BAR1                    0x14
  69. #define     BAR2                    0x18
  70. #define     BAR3                    0x1c
  71. #define     BAR4                    0x20
  72. #define     BAR5                    0x24
  75. /* typedefs */
  77. typedef struct pciDevice
  78. {
  79.     char            type[20];
  80.     unsigned int    deviceNum;
  81.     unsigned int    venID;
  82.     unsigned int    deviceID;
  83.     unsigned int    bar0Base;
  84.     unsigned int    bar0Size;
  85.     unsigned int    bar0Type;
  86.     unsigned int    bar1Base;
  87.     unsigned int    bar1Size;
  88.     unsigned int    bar1Type;
  89.     unsigned int    bar2Base;
  90.     unsigned int    bar2Size;
  91.     unsigned int    bar2Type;
  92.     unsigned int    bar3Base;
  93.     unsigned int    bar3Size;
  94.     unsigned int    bar3Type;
  95.     unsigned int    bar4Base;
  96.     unsigned int    bar4Size;
  97.     unsigned int    bar4Type;
  98.     unsigned int    bar5Base;
  99.     unsigned int    bar5Size;
  100.     unsigned int    bar5Type;
  101. } PCI_DEVICE;
  103. void    pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
  104.                            unsigned int data);
  105. void    pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
  106.                            unsigned int data);
  107. void    pci0ScanDevices(PCI_DEVICE *pci0Detect,unsigned int numberOfElment);
  108. void    pci1ScanDevices(PCI_DEVICE *pci1Detect,unsigned int numberOfElment);
  109. unsigned int    pci0ReadConfigReg (unsigned int regOffset,
  110.                                    unsigned int pciDevNum);
  111. unsigned int    pci1ReadConfigReg (unsigned int regOffset,
  112.                                    unsigned int pciDevNum);
  114. /*      Master`s memory space   */
  116. void    pci0MapIOspace(unsigned int pci0IoBase,unsigned int pci0IoLength);
  117. void    pci0MapMemory0space(unsigned int pci0Mem0Base,
  118.                             unsigned int pci0Mem0Length);
  119. void    pci0MapMemory1space(unsigned int pci0Mem1Base,
  120.                             unsigned int pci0Mem1Length);
  122. void    pci1MapIOspace(unsigned int pci1IoBase,unsigned int pci1IoLength);
  123. void    pci1MapMemory0space(unsigned int pci1Mem0Base,
  124.                             unsigned int pci1Mem0Length);
  125. void    pci1MapMemory1space(unsigned int pci1Mem1Base,
  126.                             unsigned int pci1Mem1Length);
  128. unsigned int    pci0GetIOspaceBase(void);
  129. unsigned int    pci0GetIOspaceSize(void);
  130. unsigned int    pci0GetMemory0Base(void);
  131. unsigned int    pci0GetMemory0Size(void);
  132. unsigned int    pci0GetMemory1Base(void);
  133. unsigned int    pci0GetMemory1Size(void);
  135. unsigned int    pci1GetIOspaceBase(void);
  136. unsigned int    pci1GetIOspaceSize(void);
  137. unsigned int    pci1GetMemory0Base(void);
  138. unsigned int    pci1GetMemory0Size(void);
  139. unsigned int    pci1GetMemory1Base(void);
  140. unsigned int    pci1GetMemory1Size(void);
  142. /*      Slave`s memory space   */
  143. void    pci0MapInternalRegSpace(unsigned int pci0InternalBase);
  144. void    pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
  145. void    pci0MapMemoryBanks0_1(unsigned int pci0Dram0_1Base,
  146.                               unsigned int pci0Dram0_1Size);
  147. void    pci0MapMemoryBanks2_3(unsigned int pci0Dram2_3Base,
  148.                               unsigned int pci0Dram2_3Size);
  149. void    pci0MapDevices0_1and2MemorySpace(unsigned int pci0Dev012Base,
  150.                                          unsigned int pci0Dev012Length);
  151. void    pci0MapDevices3andBootMemorySpace(unsigned int pci0Dev3andBootBase,
  152.                                           unsigned int pci0Dev3andBootLength);
  154. void    pci1MapInternalRegSpace(unsigned int pci1InternalBase);
  155. void    pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
  156. void    pci1MapMemoryBanks0_1(unsigned int pci1Dram0_1Base,
  157.                               unsigned int pci1Dram0_1Size);
  158. void    pci1MapMemoryBanks2_3(unsigned int pci1Dram2_3Base,
  159.                               unsigned int pci1Dram2_3Size);
  160. void    pci1MapDevices0_1and2MemorySpace(unsigned int pci1Dev012Base,
  161.                                          unsigned int pci1Dev012Length);
  162. void    pci1MapDevices3andBootMemorySpace(unsigned int pci1Dev3andBootBase,
  163.                                           unsigned int pci1Dev3andBootLength);
  165. #endif  /* __INCpcih */