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shub_mmr.h
资源名称：linux-2.4.20.tar.gz　[点击查看]
上传用户：jlfgdled
上传日期：2013-04-10
资源大小：33168k
文件大小：1725k
源码类别：

Linux/Unix编程

开发平台：

Unix_Linux

shub_mmr.h：源码内容
  1. /*
  2.  *
  3.  * This file is subject to the terms and conditions of the GNU General Public
  4.  * License.  See the file "COPYING" in the main directory of this archive
  5.  * for more details.
  6.  *
  7.  * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
  8.  */
  11. #ifndef _ASM_IA64_SN_SN2_SHUB_MMR_H
  12. #define _ASM_IA64_SN_SN2_SHUB_MMR_H
  14. /* ==================================================================== */
  15. /*                   Register "SH_FSB_BINIT_CONTROL"                    */
  16. /*                          FSB BINIT# Control                          */
  17. /* ==================================================================== */
  19. #define SH_FSB_BINIT_CONTROL                     0x0000000120010000
  20. #define SH_FSB_BINIT_CONTROL_MASK                0x0000000000000001
  21. #define SH_FSB_BINIT_CONTROL_INIT                0x0000000000000000
  23. /*   SH_FSB_BINIT_CONTROL_BINIT                                         */
  24. /*   Description:  Assert the FSB's BINIT# Signal                       */
  25. #define SH_FSB_BINIT_CONTROL_BINIT_SHFT          0
  26. #define SH_FSB_BINIT_CONTROL_BINIT_MASK          0x0000000000000001
  28. /* ==================================================================== */
  29. /*                   Register "SH_FSB_RESET_CONTROL"                    */
  30. /*                          FSB Reset Control                           */
  31. /* ==================================================================== */
  33. #define SH_FSB_RESET_CONTROL                     0x0000000120010080
  34. #define SH_FSB_RESET_CONTROL_MASK                0x0000000000000001
  35. #define SH_FSB_RESET_CONTROL_INIT                0x0000000000000000
  37. /*   SH_FSB_RESET_CONTROL_RESET                                         */
  38. /*   Description:  Assert the FSB's RESET# Signal                       */
  39. #define SH_FSB_RESET_CONTROL_RESET_SHFT          0
  40. #define SH_FSB_RESET_CONTROL_RESET_MASK          0x0000000000000001
  42. /* ==================================================================== */
  43. /*                Register "SH_FSB_SYSTEM_AGENT_CONFIG"                 */
  44. /*                    FSB System Agent Configuration                    */
  45. /* ==================================================================== */
  47. #define SH_FSB_SYSTEM_AGENT_CONFIG               0x0000000120010100
  48. #define SH_FSB_SYSTEM_AGENT_CONFIG_MASK          0x00003fff0187fff9
  49. #define SH_FSB_SYSTEM_AGENT_CONFIG_INIT          0x0000000000000000
  51. /*   SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN                            */
  52. /*   Description:  RCNT/SCNT Assertion Enabled                          */
  53. #define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0
  54. #define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001
  56. /*   SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN                          */
  57. /*   Description:  BERR Assertion Enabled for Bus Errors                */
  58. #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3
  59. #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008
  61. /*   SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN                        */
  62. /*   Description:  BERR Sampling Enabled                                */
  63. #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4
  64. #define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010
  66. /*   SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN                         */
  67. /*   Description:  BINIT Assertion Enabled                              */
  68. #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5
  69. #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020
  71. /*   SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN                       */
  72. /*   Description:  stutter FSB request assertion                        */
  73. #define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6
  74. #define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040
  76. /*   SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN                           */
  77. /*   Description:  use short duration hang timeout                      */
  78. #define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7
  79. #define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080
  81. /*   SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA                           */
  82. /*   Description:  Interrupt Acknowledge Response Data                  */
  83. #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8
  84. #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00
  86. /*   SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP                            */
  87. /*   Description:  IO Transaction Response                              */
  88. #define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16
  89. #define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000
  91. /*   SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP                          */
  92. /*   Description:  External Task Priority Register (xTPR) Transaction   */
  93. /*  Response                                                            */
  94. #define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17
  95. #define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000
  97. /*   SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP                          */
  98. /*   Description:  Interrupt Acknowledge Transaction Response           */
  99. #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18
  100. #define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000
  102. /*   SH_FSB_SYSTEM_AGENT_CONFIG_TDOT                                    */
  103. /*   Description:  Throttle Data-bus Ownership Transitions              */
  104. #define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT     23
  105. #define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK     0x0000000000800000
  107. /*   SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN                        */
  108. /*   Description:  serialize processor transactions                     */
  109. #define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24
  110. #define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000
  112. /*   SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES                     */
  113. /*   Description:  FSB error binit enables                              */
  114. #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32
  115. #define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000
  117. /* ==================================================================== */
  118. /*                     Register "SH_FSB_VGA_REMAP"                      */
  119. /*                     FSB VGA Address Space Remap                      */
  120. /* ==================================================================== */
  122. #define SH_FSB_VGA_REMAP                         0x0000000120010180
  123. #define SH_FSB_VGA_REMAP_MASK                    0x4001fffffffe0000
  124. #define SH_FSB_VGA_REMAP_INIT                    0x0000000000000000
  126. /*   SH_FSB_VGA_REMAP_OFFSET                                            */
  127. /*   Description:  VGA Remap Node Offset                                */
  128. #define SH_FSB_VGA_REMAP_OFFSET_SHFT             17
  129. #define SH_FSB_VGA_REMAP_OFFSET_MASK             0x0000000ffffe0000
  131. /*   SH_FSB_VGA_REMAP_ASID                                              */
  132. /*   Description:  VGA Remap Address Space ID                           */
  133. #define SH_FSB_VGA_REMAP_ASID_SHFT               36
  134. #define SH_FSB_VGA_REMAP_ASID_MASK               0x0000003000000000
  136. /*   SH_FSB_VGA_REMAP_NID                                               */
  137. /*   Description:  VGA Remap Node ID                                    */
  138. #define SH_FSB_VGA_REMAP_NID_SHFT                38
  139. #define SH_FSB_VGA_REMAP_NID_MASK                0x0001ffc000000000
  141. /*   SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED                             */
  142. /*   Description:  VGA Remapping Enabled                                */
  143. #define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62
  144. #define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000
  146. /* ==================================================================== */
  147. /*                    Register "SH_FSB_RESET_STATUS"                    */
  148. /*                           FSB Reset Status                           */
  149. /* ==================================================================== */
  151. #define SH_FSB_RESET_STATUS                      0x0000000120020000
  152. #define SH_FSB_RESET_STATUS_MASK                 0x0000000000000001
  153. #define SH_FSB_RESET_STATUS_INIT                 0x0000000000000000
  155. /*   SH_FSB_RESET_STATUS_RESET_IN_PROGRESS                              */
  156. /*   Description:  Reset in Progress                                    */
  157. #define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0
  158. #define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001
  160. /* ==================================================================== */
  161. /*               Register "SH_FSB_SYMMETRIC_AGENT_STATUS"               */
  162. /*                      FSB Symmetric Agent Status                      */
  163. /* ==================================================================== */
  165. #define SH_FSB_SYMMETRIC_AGENT_STATUS            0x0000000120020080
  166. #define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK       0x0000000000000007
  167. #define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT       0x0000000000000000
  169. /*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE                         */
  170. /*   Description:  CPU 0 Active.                                        */
  171. #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0
  172. #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001
  174. /*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE                         */
  175. /*   Description:  CPU 1 Active.                                        */
  176. #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1
  177. #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002
  179. /*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY                           */
  180. /*   Description:  The Processors are Ready                             */
  181. #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2
  182. #define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004
  184. /* ==================================================================== */
  185. /*                   Register "SH_GFX_CREDIT_COUNT_0"                   */
  186. /*                Graphics-write Credit Count for CPU 0                 */
  187. /* ==================================================================== */
  189. #define SH_GFX_CREDIT_COUNT_0                    0x0000000120030000
  190. #define SH_GFX_CREDIT_COUNT_0_MASK               0x80000000000fffff
  191. #define SH_GFX_CREDIT_COUNT_0_INIT               0x000000000000003f
  193. /*   SH_GFX_CREDIT_COUNT_0_COUNT                                        */
  194. /*   Description:  Credit Count                                         */
  195. #define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT         0
  196. #define SH_GFX_CREDIT_COUNT_0_COUNT_MASK         0x00000000000fffff
  198. /*   SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE                              */
  199. /*   Description:  Reset GFX state                                      */
  200. #define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63
  201. #define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000
  203. /* ==================================================================== */
  204. /*                   Register "SH_GFX_CREDIT_COUNT_1"                   */
  205. /*                Graphics-write Credit Count for CPU 1                 */
  206. /* ==================================================================== */
  208. #define SH_GFX_CREDIT_COUNT_1                    0x0000000120030080
  209. #define SH_GFX_CREDIT_COUNT_1_MASK               0x80000000000fffff
  210. #define SH_GFX_CREDIT_COUNT_1_INIT               0x000000000000003f
  212. /*   SH_GFX_CREDIT_COUNT_1_COUNT                                        */
  213. /*   Description:  Credit Count                                         */
  214. #define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT         0
  215. #define SH_GFX_CREDIT_COUNT_1_COUNT_MASK         0x00000000000fffff
  217. /*   SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE                              */
  218. /*   Description:  Reset GFX state                                      */
  219. #define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63
  220. #define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000
  222. /* ==================================================================== */
  223. /*                    Register "SH_GFX_MODE_CNTRL_0"                    */
  224. /*         Graphics credit mode amd message ordering for CPU 0          */
  225. /* ==================================================================== */
  227. #define SH_GFX_MODE_CNTRL_0                      0x0000000120030100
  228. #define SH_GFX_MODE_CNTRL_0_MASK                 0x0000000000000007
  229. #define SH_GFX_MODE_CNTRL_0_INIT                 0x0000000000000003
  231. /*   SH_GFX_MODE_CNTRL_0_DWORD_CREDITS                                  */
  232. /*   Description:  GFX credits are tracked by D-words                   */
  233. #define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT   0
  234. #define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK   0x0000000000000001
  236. /*   SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS                             */
  237. /*   Description:  GFX credits are tracked by D-words and messages      */
  238. #define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1
  239. #define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002
  241. /*   SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING                               */
  242. /*   Description:  GFX message routing order                            */
  243. #define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2
  244. #define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004
  246. /* ==================================================================== */
  247. /*                    Register "SH_GFX_MODE_CNTRL_1"                    */
  248. /*         Graphics credit mode amd message ordering for CPU 1          */
  249. /* ==================================================================== */
  251. #define SH_GFX_MODE_CNTRL_1                      0x0000000120030180
  252. #define SH_GFX_MODE_CNTRL_1_MASK                 0x0000000000000007
  253. #define SH_GFX_MODE_CNTRL_1_INIT                 0x0000000000000003
  255. /*   SH_GFX_MODE_CNTRL_1_DWORD_CREDITS                                  */
  256. /*   Description:  GFX credits are tracked by D-words                   */
  257. #define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT   0
  258. #define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK   0x0000000000000001
  260. /*   SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS                             */
  261. /*   Description:  GFX credits are tracked by D-words and messages      */
  262. #define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1
  263. #define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002
  265. /*   SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING                               */
  266. /*   Description:  GFX message routing order                            */
  267. #define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2
  268. #define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004
  270. /* ==================================================================== */
  271. /*                Register "SH_GFX_SKID_CREDIT_COUNT_0"                 */
  272. /*              Graphics-write Skid Credit Count for CPU 0              */
  273. /* ==================================================================== */
  275. #define SH_GFX_SKID_CREDIT_COUNT_0               0x0000000120030200
  276. #define SH_GFX_SKID_CREDIT_COUNT_0_MASK          0x00000000000fffff
  277. #define SH_GFX_SKID_CREDIT_COUNT_0_INIT          0x0000000000000030
  279. /*   SH_GFX_SKID_CREDIT_COUNT_0_SKID                                    */
  280. /*   Description:  Skid Credit Count                                    */
  281. #define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT     0
  282. #define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK     0x00000000000fffff
  284. /* ==================================================================== */
  285. /*                Register "SH_GFX_SKID_CREDIT_COUNT_1"                 */
  286. /*              Graphics-write Skid Credit Count for CPU 1              */
  287. /* ==================================================================== */
  289. #define SH_GFX_SKID_CREDIT_COUNT_1               0x0000000120030280
  290. #define SH_GFX_SKID_CREDIT_COUNT_1_MASK          0x00000000000fffff
  291. #define SH_GFX_SKID_CREDIT_COUNT_1_INIT          0x0000000000000030
  293. /*   SH_GFX_SKID_CREDIT_COUNT_1_SKID                                    */
  294. /*   Description:  Skid Credit Count                                    */
  295. #define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT     0
  296. #define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK     0x00000000000fffff
  298. /* ==================================================================== */
  299. /*                   Register "SH_GFX_STALL_LIMIT_0"                    */
  300. /*                 Graphics-write Stall Limit for CPU 0                 */
  301. /* ==================================================================== */
  303. #define SH_GFX_STALL_LIMIT_0                     0x0000000120030300
  304. #define SH_GFX_STALL_LIMIT_0_MASK                0x0000000003ffffff
  305. #define SH_GFX_STALL_LIMIT_0_INIT                0x0000000000010000
  307. /*   SH_GFX_STALL_LIMIT_0_LIMIT                                         */
  308. /*   Description:  Graphics Stall Limit for CPU 0                       */
  309. #define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT          0
  310. #define SH_GFX_STALL_LIMIT_0_LIMIT_MASK          0x0000000003ffffff
  312. /* ==================================================================== */
  313. /*                   Register "SH_GFX_STALL_LIMIT_1"                    */
  314. /*                 Graphics-write Stall Limit for CPU 1                 */
  315. /* ==================================================================== */
  317. #define SH_GFX_STALL_LIMIT_1                     0x0000000120030380
  318. #define SH_GFX_STALL_LIMIT_1_MASK                0x0000000003ffffff
  319. #define SH_GFX_STALL_LIMIT_1_INIT                0x0000000000010000
  321. /*   SH_GFX_STALL_LIMIT_1_LIMIT                                         */
  322. /*   Description:  Graphics Stall Limit for CPU 1                       */
  323. #define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT          0
  324. #define SH_GFX_STALL_LIMIT_1_LIMIT_MASK          0x0000000003ffffff
  326. /* ==================================================================== */
  327. /*                   Register "SH_GFX_STALL_TIMER_0"                    */
  328. /*                 Graphics-write Stall Timer for CPU 0                 */
  329. /* ==================================================================== */
  331. #define SH_GFX_STALL_TIMER_0                     0x0000000120030400
  332. #define SH_GFX_STALL_TIMER_0_MASK                0x0000000003ffffff
  333. #define SH_GFX_STALL_TIMER_0_INIT                0x0000000000000000
  335. /*   SH_GFX_STALL_TIMER_0_TIMER_VALUE                                   */
  336. /*   Description:  Timer Value                                          */
  337. #define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT    0
  338. #define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK    0x0000000003ffffff
  340. /* ==================================================================== */
  341. /*                   Register "SH_GFX_STALL_TIMER_1"                    */
  342. /*                 Graphics-write Stall Timer for CPU 1                 */
  343. /* ==================================================================== */
  345. #define SH_GFX_STALL_TIMER_1                     0x0000000120030480
  346. #define SH_GFX_STALL_TIMER_1_MASK                0x0000000003ffffff
  347. #define SH_GFX_STALL_TIMER_1_INIT                0x0000000000000000
  349. /*   SH_GFX_STALL_TIMER_1_TIMER_VALUE                                   */
  350. /*   Description:  Timer Value                                          */
  351. #define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT    0
  352. #define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK    0x0000000003ffffff
  354. /* ==================================================================== */
  355. /*                      Register "SH_GFX_WINDOW_0"                      */
  356. /*                   Graphics-write Window for CPU 0                    */
  357. /* ==================================================================== */
  359. #define SH_GFX_WINDOW_0                          0x0000000120030500
  360. #define SH_GFX_WINDOW_0_MASK                     0x8000000fff000000
  361. #define SH_GFX_WINDOW_0_INIT                     0x0000000000000000
  363. /*   SH_GFX_WINDOW_0_BASE_ADDR                                          */
  364. /*   Description:  Base Address for CPU 0's 16 MB Graphics Window       */
  365. #define SH_GFX_WINDOW_0_BASE_ADDR_SHFT           24
  366. #define SH_GFX_WINDOW_0_BASE_ADDR_MASK           0x0000000fff000000
  368. /*   SH_GFX_WINDOW_0_GFX_WINDOW_EN                                      */
  369. /*   Description:  Graphics Window Enabled                              */
  370. #define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT       63
  371. #define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK       0x8000000000000000
  373. /* ==================================================================== */
  374. /*                      Register "SH_GFX_WINDOW_1"                      */
  375. /*                   Graphics-write Window for CPU 1                    */
  376. /* ==================================================================== */
  378. #define SH_GFX_WINDOW_1                          0x0000000120030580
  379. #define SH_GFX_WINDOW_1_MASK                     0x8000000fff000000
  380. #define SH_GFX_WINDOW_1_INIT                     0x0000000000000000
  382. /*   SH_GFX_WINDOW_1_BASE_ADDR                                          */
  383. /*   Description:  Base Address for CPU 1's 16 MB Graphics Window       */
  384. #define SH_GFX_WINDOW_1_BASE_ADDR_SHFT           24
  385. #define SH_GFX_WINDOW_1_BASE_ADDR_MASK           0x0000000fff000000
  387. /*   SH_GFX_WINDOW_1_GFX_WINDOW_EN                                      */
  388. /*   Description:  Graphics Window Enabled                              */
  389. #define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT       63
  390. #define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK       0x8000000000000000
  392. /* ==================================================================== */
  393. /*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
  394. /*               Graphics-write Interrupt Limit for CPU 0               */
  395. /* ==================================================================== */
  397. #define SH_GFX_INTERRUPT_TIMER_LIMIT_0           0x0000000120030600
  398. #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK      0x00000000000000ff
  399. #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT      0x0000000000000040
  401. /*   SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT               */
  402. /*   Description:  GFX Interrupt Timer Limit                            */
  403. #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0
  404. #define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
  406. /* ==================================================================== */
  407. /*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
  408. /*               Graphics-write Interrupt Limit for CPU 1               */
  409. /* ==================================================================== */
  411. #define SH_GFX_INTERRUPT_TIMER_LIMIT_1           0x0000000120030680
  412. #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK      0x00000000000000ff
  413. #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT      0x0000000000000040
  415. /*   SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT               */
  416. /*   Description:  GFX Interrupt Timer Limit                            */
  417. #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0
  418. #define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
  420. /* ==================================================================== */
  421. /*                   Register "SH_GFX_WRITE_STATUS_0"                   */
  422. /*                   Graphics Write Status for CPU 0                    */
  423. /* ==================================================================== */
  425. #define SH_GFX_WRITE_STATUS_0                    0x0000000120040000
  426. #define SH_GFX_WRITE_STATUS_0_MASK               0x8000000000000001
  427. #define SH_GFX_WRITE_STATUS_0_INIT               0x0000000000000000
  429. /*   SH_GFX_WRITE_STATUS_0_BUSY                                         */
  430. /*   Description:  Busy                                                 */
  431. #define SH_GFX_WRITE_STATUS_0_BUSY_SHFT          0
  432. #define SH_GFX_WRITE_STATUS_0_BUSY_MASK          0x0000000000000001
  434. /*   SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL                          */
  435. /*   Description:  Re-enable GFX stall logic for this processor         */
  436. #define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63
  437. #define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
  439. /* ==================================================================== */
  440. /*                   Register "SH_GFX_WRITE_STATUS_1"                   */
  441. /*                   Graphics Write Status for CPU 1                    */
  442. /* ==================================================================== */
  444. #define SH_GFX_WRITE_STATUS_1                    0x0000000120040080
  445. #define SH_GFX_WRITE_STATUS_1_MASK               0x8000000000000001
  446. #define SH_GFX_WRITE_STATUS_1_INIT               0x0000000000000000
  448. /*   SH_GFX_WRITE_STATUS_1_BUSY                                         */
  449. /*   Description:  Busy                                                 */
  450. #define SH_GFX_WRITE_STATUS_1_BUSY_SHFT          0
  451. #define SH_GFX_WRITE_STATUS_1_BUSY_MASK          0x0000000000000001
  453. /*   SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL                          */
  454. /*   Description:  Re-enable GFX stall logic for this processor         */
  455. #define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63
  456. #define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
  458. /* ==================================================================== */
  459. /*                        Register "SH_II_INT0"                         */
  460. /*                    SHub II Interrupt 0 Registers                     */
  461. /* ==================================================================== */
  463. #define SH_II_INT0                               0x0000000110000000
  464. #define SH_II_INT0_MASK                          0x00000000000001ff
  465. #define SH_II_INT0_INIT                          0x0000000000000000
  467. /*   SH_II_INT0_IDX                                                     */
  468. /*   Description:  Targeted McKinley interrupt vector                   */
  469. #define SH_II_INT0_IDX_SHFT                      0
  470. #define SH_II_INT0_IDX_MASK                      0x00000000000000ff
  472. /*   SH_II_INT0_SEND                                                    */
  473. /*   Description:  Send Interrupt Message to PI, This generates a puls  */
  474. #define SH_II_INT0_SEND_SHFT                     8
  475. #define SH_II_INT0_SEND_MASK                     0x0000000000000100
  477. /* ==================================================================== */
  478. /*                     Register "SH_II_INT0_CONFIG"                     */
  479. /*                 SHub II Interrupt 0 Config Registers                 */
  480. /* ==================================================================== */
  482. #define SH_II_INT0_CONFIG                        0x0000000110000080
  483. #define SH_II_INT0_CONFIG_MASK                   0x0003ffffffefffff
  484. #define SH_II_INT0_CONFIG_INIT                   0x0000000000000000
  486. /*   SH_II_INT0_CONFIG_TYPE                                             */
  487. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  488. #define SH_II_INT0_CONFIG_TYPE_SHFT              0
  489. #define SH_II_INT0_CONFIG_TYPE_MASK              0x0000000000000007
  491. /*   SH_II_INT0_CONFIG_AGT                                              */
  492. /*   Description:  Agent, must be 0 for SHub                            */
  493. #define SH_II_INT0_CONFIG_AGT_SHFT               3
  494. #define SH_II_INT0_CONFIG_AGT_MASK               0x0000000000000008
  496. /*   SH_II_INT0_CONFIG_PID                                              */
  497. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  498. #define SH_II_INT0_CONFIG_PID_SHFT               4
  499. #define SH_II_INT0_CONFIG_PID_MASK               0x00000000000ffff0
  501. /*   SH_II_INT0_CONFIG_BASE                                             */
  502. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  503. #define SH_II_INT0_CONFIG_BASE_SHFT              21
  504. #define SH_II_INT0_CONFIG_BASE_MASK              0x0003ffffffe00000
  506. /* ==================================================================== */
  507. /*                     Register "SH_II_INT0_ENABLE"                     */
  508. /*                 SHub II Interrupt 0 Enable Registers                 */
  509. /* ==================================================================== */
  511. #define SH_II_INT0_ENABLE                        0x0000000110000200
  512. #define SH_II_INT0_ENABLE_MASK                   0x0000000000000001
  513. #define SH_II_INT0_ENABLE_INIT                   0x0000000000000000
  515. /*   SH_II_INT0_ENABLE_II_ENABLE                                        */
  516. /*   Description:  Enable II Interrupt                                  */
  517. #define SH_II_INT0_ENABLE_II_ENABLE_SHFT         0
  518. #define SH_II_INT0_ENABLE_II_ENABLE_MASK         0x0000000000000001
  520. /* ==================================================================== */
  521. /*                        Register "SH_II_INT1"                         */
  522. /*                    SHub II Interrupt 1 Registers                     */
  523. /* ==================================================================== */
  525. #define SH_II_INT1                               0x0000000110000100
  526. #define SH_II_INT1_MASK                          0x00000000000001ff
  527. #define SH_II_INT1_INIT                          0x0000000000000000
  529. /*   SH_II_INT1_IDX                                                     */
  530. /*   Description:  Targeted McKinley interrupt vector                   */
  531. #define SH_II_INT1_IDX_SHFT                      0
  532. #define SH_II_INT1_IDX_MASK                      0x00000000000000ff
  534. /*   SH_II_INT1_SEND                                                    */
  535. /*   Description:  Send Interrupt Message to PI, This generates a puls  */
  536. #define SH_II_INT1_SEND_SHFT                     8
  537. #define SH_II_INT1_SEND_MASK                     0x0000000000000100
  539. /* ==================================================================== */
  540. /*                     Register "SH_II_INT1_CONFIG"                     */
  541. /*                 SHub II Interrupt 1 Config Registers                 */
  542. /* ==================================================================== */
  544. #define SH_II_INT1_CONFIG                        0x0000000110000180
  545. #define SH_II_INT1_CONFIG_MASK                   0x0003ffffffefffff
  546. #define SH_II_INT1_CONFIG_INIT                   0x0000000000000000
  548. /*   SH_II_INT1_CONFIG_TYPE                                             */
  549. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  550. #define SH_II_INT1_CONFIG_TYPE_SHFT              0
  551. #define SH_II_INT1_CONFIG_TYPE_MASK              0x0000000000000007
  553. /*   SH_II_INT1_CONFIG_AGT                                              */
  554. /*   Description:  Agent, must be 0 for SHub                            */
  555. #define SH_II_INT1_CONFIG_AGT_SHFT               3
  556. #define SH_II_INT1_CONFIG_AGT_MASK               0x0000000000000008
  558. /*   SH_II_INT1_CONFIG_PID                                              */
  559. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  560. #define SH_II_INT1_CONFIG_PID_SHFT               4
  561. #define SH_II_INT1_CONFIG_PID_MASK               0x00000000000ffff0
  563. /*   SH_II_INT1_CONFIG_BASE                                             */
  564. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  565. #define SH_II_INT1_CONFIG_BASE_SHFT              21
  566. #define SH_II_INT1_CONFIG_BASE_MASK              0x0003ffffffe00000
  568. /* ==================================================================== */
  569. /*                     Register "SH_II_INT1_ENABLE"                     */
  570. /*                 SHub II Interrupt 1 Enable Registers                 */
  571. /* ==================================================================== */
  573. #define SH_II_INT1_ENABLE                        0x0000000110000280
  574. #define SH_II_INT1_ENABLE_MASK                   0x0000000000000001
  575. #define SH_II_INT1_ENABLE_INIT                   0x0000000000000000
  577. /*   SH_II_INT1_ENABLE_II_ENABLE                                        */
  578. /*   Description:  Enable II 1 Interrupt                                */
  579. #define SH_II_INT1_ENABLE_II_ENABLE_SHFT         0
  580. #define SH_II_INT1_ENABLE_II_ENABLE_MASK         0x0000000000000001
  582. /* ==================================================================== */
  583. /*                   Register "SH_INT_NODE_ID_CONFIG"                   */
  584. /*                 SHub Interrupt Node ID Configuration                 */
  585. /* ==================================================================== */
  587. #define SH_INT_NODE_ID_CONFIG                    0x0000000110000300
  588. #define SH_INT_NODE_ID_CONFIG_MASK               0x0000000000000fff
  589. #define SH_INT_NODE_ID_CONFIG_INIT               0x0000000000000000
  591. /*   SH_INT_NODE_ID_CONFIG_NODE_ID                                      */
  592. /*   Description:  Node ID for interrupt messages                       */
  593. #define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT       0
  594. #define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK       0x00000000000007ff
  596. /*   SH_INT_NODE_ID_CONFIG_ID_SEL                                       */
  597. /*   Description:  Select node id for interrupt messages                */
  598. #define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT        11
  599. #define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK        0x0000000000000800
  601. /* ==================================================================== */
  602. /*                        Register "SH_IPI_INT"                         */
  603. /*               SHub Inter-Processor Interrupt Registers               */
  604. /* ==================================================================== */
  606. #define SH_IPI_INT                               0x0000000110000380
  607. #define SH_IPI_INT_MASK                          0x8ff3ffffffefffff
  608. #define SH_IPI_INT_INIT                          0x0000000000000000
  610. /*   SH_IPI_INT_TYPE                                                    */
  611. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  612. #define SH_IPI_INT_TYPE_SHFT                     0
  613. #define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
  615. /*   SH_IPI_INT_AGT                                                     */
  616. /*   Description:  Agent, must be 0 for SHub                            */
  617. #define SH_IPI_INT_AGT_SHFT                      3
  618. #define SH_IPI_INT_AGT_MASK                      0x0000000000000008
  620. /*   SH_IPI_INT_PID                                                     */
  621. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  622. #define SH_IPI_INT_PID_SHFT                      4
  623. #define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
  625. /*   SH_IPI_INT_BASE                                                    */
  626. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  627. #define SH_IPI_INT_BASE_SHFT                     21
  628. #define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
  630. /*   SH_IPI_INT_IDX                                                     */
  631. /*   Description:  Targeted McKinley interrupt vector                   */
  632. #define SH_IPI_INT_IDX_SHFT                      52
  633. #define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
  635. /*   SH_IPI_INT_SEND                                                    */
  636. /*   Description:  Send Interrupt Message to PI, This generates a puls  */
  637. #define SH_IPI_INT_SEND_SHFT                     63
  638. #define SH_IPI_INT_SEND_MASK                     0x8000000000000000
  640. /* ==================================================================== */
  641. /*                     Register "SH_IPI_INT_ENABLE"                     */
  642. /*           SHub Inter-Processor Interrupt Enable Registers            */
  643. /* ==================================================================== */
  645. #define SH_IPI_INT_ENABLE                        0x0000000110000400
  646. #define SH_IPI_INT_ENABLE_MASK                   0x0000000000000001
  647. #define SH_IPI_INT_ENABLE_INIT                   0x0000000000000000
  649. /*   SH_IPI_INT_ENABLE_PIO_ENABLE                                       */
  650. /*   Description:  Enable PIO Interrupt                                 */
  651. #define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT        0
  652. #define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK        0x0000000000000001
  654. /* ==================================================================== */
  655. /*                   Register "SH_LOCAL_INT0_CONFIG"                    */
  656. /*                   SHub Local Interrupt 0 Registers                   */
  657. /* ==================================================================== */
  659. #define SH_LOCAL_INT0_CONFIG                     0x0000000110000480
  660. #define SH_LOCAL_INT0_CONFIG_MASK                0x0ff3ffffffefffff
  661. #define SH_LOCAL_INT0_CONFIG_INIT                0x0000000000000000
  663. /*   SH_LOCAL_INT0_CONFIG_TYPE                                          */
  664. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  665. #define SH_LOCAL_INT0_CONFIG_TYPE_SHFT           0
  666. #define SH_LOCAL_INT0_CONFIG_TYPE_MASK           0x0000000000000007
  668. /*   SH_LOCAL_INT0_CONFIG_AGT                                           */
  669. /*   Description:  Agent, must be 0 for SHub                            */
  670. #define SH_LOCAL_INT0_CONFIG_AGT_SHFT            3
  671. #define SH_LOCAL_INT0_CONFIG_AGT_MASK            0x0000000000000008
  673. /*   SH_LOCAL_INT0_CONFIG_PID                                           */
  674. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  675. #define SH_LOCAL_INT0_CONFIG_PID_SHFT            4
  676. #define SH_LOCAL_INT0_CONFIG_PID_MASK            0x00000000000ffff0
  678. /*   SH_LOCAL_INT0_CONFIG_BASE                                          */
  679. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  680. #define SH_LOCAL_INT0_CONFIG_BASE_SHFT           21
  681. #define SH_LOCAL_INT0_CONFIG_BASE_MASK           0x0003ffffffe00000
  683. /*   SH_LOCAL_INT0_CONFIG_IDX                                           */
  684. /*   Description:  Targeted McKinley interrupt vector                   */
  685. #define SH_LOCAL_INT0_CONFIG_IDX_SHFT            52
  686. #define SH_LOCAL_INT0_CONFIG_IDX_MASK            0x0ff0000000000000
  688. /* ==================================================================== */
  689. /*                   Register "SH_LOCAL_INT0_ENABLE"                    */
  690. /*                    SHub Local Interrupt 0 Enable                     */
  691. /* ==================================================================== */
  693. #define SH_LOCAL_INT0_ENABLE                     0x0000000110000500
  694. #define SH_LOCAL_INT0_ENABLE_MASK                0x000000000000f7ff
  695. #define SH_LOCAL_INT0_ENABLE_INIT                0x0000000000000000
  697. /*   SH_LOCAL_INT0_ENABLE_PI_HW_INT                                     */
  698. /*   Description:  Enable PI Hardware interrupt                         */
  699. #define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT      0
  700. #define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK      0x0000000000000001
  702. /*   SH_LOCAL_INT0_ENABLE_MD_HW_INT                                     */
  703. /*   Description:  Enable MD Hardware interrupt                         */
  704. #define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT      1
  705. #define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK      0x0000000000000002
  707. /*   SH_LOCAL_INT0_ENABLE_XN_HW_INT                                     */
  708. /*   Description:  Enable XN Hardware interrupt                         */
  709. #define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT      2
  710. #define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK      0x0000000000000004
  712. /*   SH_LOCAL_INT0_ENABLE_LB_HW_INT                                     */
  713. /*   Description:  Enable LB Hardware interrupt                         */
  714. #define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT      3
  715. #define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK      0x0000000000000008
  717. /*   SH_LOCAL_INT0_ENABLE_II_HW_INT                                     */
  718. /*   Description:  Enable II wrapper Hardware interrupt                 */
  719. #define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT      4
  720. #define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK      0x0000000000000010
  722. /*   SH_LOCAL_INT0_ENABLE_PI_CE_INT                                     */
  723. /*   Description:  Enable PI Correctable Error Interrupt                */
  724. #define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT      5
  725. #define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK      0x0000000000000020
  727. /*   SH_LOCAL_INT0_ENABLE_MD_CE_INT                                     */
  728. /*   Description:  Enable MD Correctable Error Interrupt                */
  729. #define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT      6
  730. #define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK      0x0000000000000040
  732. /*   SH_LOCAL_INT0_ENABLE_XN_CE_INT                                     */
  733. /*   Description:  Enable XN Correctable Error Interrupt                */
  734. #define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT      7
  735. #define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK      0x0000000000000080
  737. /*   SH_LOCAL_INT0_ENABLE_PI_UCE_INT                                    */
  738. /*   Description:  Enable PI Correctable Error Interrupt                */
  739. #define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT     8
  740. #define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
  742. /*   SH_LOCAL_INT0_ENABLE_MD_UCE_INT                                    */
  743. /*   Description:  Enable MD Correctable Error Interrupt                */
  744. #define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT     9
  745. #define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
  747. /*   SH_LOCAL_INT0_ENABLE_XN_UCE_INT                                    */
  748. /*   Description:  Enable XN Correctable Error Interrupt                */
  749. #define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT     10
  750. #define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
  752. /*   SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT                           */
  753. /*   Description:  Enable System Shutdown Interrupt                     */
  754. #define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
  755. #define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
  757. /*   SH_LOCAL_INT0_ENABLE_UART_INT                                      */
  758. /*   Description:  Enable Junk Bus UART Interrupt                       */
  759. #define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT       13
  760. #define SH_LOCAL_INT0_ENABLE_UART_INT_MASK       0x0000000000002000
  762. /*   SH_LOCAL_INT0_ENABLE_L1_NMI_INT                                    */
  763. /*   Description:  Enable L1 Controller NMI Interrupt                   */
  764. #define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT     14
  765. #define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
  767. /*   SH_LOCAL_INT0_ENABLE_STOP_CLOCK                                    */
  768. /*   Description:  Stop Clock Interrupt                                 */
  769. #define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT     15
  770. #define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
  772. /* ==================================================================== */
  773. /*                   Register "SH_LOCAL_INT1_CONFIG"                    */
  774. /*                   SHub Local Interrupt 1 Registers                   */
  775. /* ==================================================================== */
  777. #define SH_LOCAL_INT1_CONFIG                     0x0000000110000580
  778. #define SH_LOCAL_INT1_CONFIG_MASK                0x0ff3ffffffefffff
  779. #define SH_LOCAL_INT1_CONFIG_INIT                0x0000000000000000
  781. /*   SH_LOCAL_INT1_CONFIG_TYPE                                          */
  782. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  783. #define SH_LOCAL_INT1_CONFIG_TYPE_SHFT           0
  784. #define SH_LOCAL_INT1_CONFIG_TYPE_MASK           0x0000000000000007
  786. /*   SH_LOCAL_INT1_CONFIG_AGT                                           */
  787. /*   Description:  Agent, must be 0 for SHub                            */
  788. #define SH_LOCAL_INT1_CONFIG_AGT_SHFT            3
  789. #define SH_LOCAL_INT1_CONFIG_AGT_MASK            0x0000000000000008
  791. /*   SH_LOCAL_INT1_CONFIG_PID                                           */
  792. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  793. #define SH_LOCAL_INT1_CONFIG_PID_SHFT            4
  794. #define SH_LOCAL_INT1_CONFIG_PID_MASK            0x00000000000ffff0
  796. /*   SH_LOCAL_INT1_CONFIG_BASE                                          */
  797. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  798. #define SH_LOCAL_INT1_CONFIG_BASE_SHFT           21
  799. #define SH_LOCAL_INT1_CONFIG_BASE_MASK           0x0003ffffffe00000
  801. /*   SH_LOCAL_INT1_CONFIG_IDX                                           */
  802. /*   Description:  Targeted McKinley interrupt vector                   */
  803. #define SH_LOCAL_INT1_CONFIG_IDX_SHFT            52
  804. #define SH_LOCAL_INT1_CONFIG_IDX_MASK            0x0ff0000000000000
  806. /* ==================================================================== */
  807. /*                   Register "SH_LOCAL_INT1_ENABLE"                    */
  808. /*                    SHub Local Interrupt 1 Enable                     */
  809. /* ==================================================================== */
  811. #define SH_LOCAL_INT1_ENABLE                     0x0000000110000600
  812. #define SH_LOCAL_INT1_ENABLE_MASK                0x000000000000f7ff
  813. #define SH_LOCAL_INT1_ENABLE_INIT                0x0000000000000000
  815. /*   SH_LOCAL_INT1_ENABLE_PI_HW_INT                                     */
  816. /*   Description:  Enable PI Hardware interrupt                         */
  817. #define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT      0
  818. #define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK      0x0000000000000001
  820. /*   SH_LOCAL_INT1_ENABLE_MD_HW_INT                                     */
  821. /*   Description:  Enable MD Hardware interrupt                         */
  822. #define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT      1
  823. #define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK      0x0000000000000002
  825. /*   SH_LOCAL_INT1_ENABLE_XN_HW_INT                                     */
  826. /*   Description:  Enable XN Hardware interrupt                         */
  827. #define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT      2
  828. #define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK      0x0000000000000004
  830. /*   SH_LOCAL_INT1_ENABLE_LB_HW_INT                                     */
  831. /*   Description:  Enable LB Hardware interrupt                         */
  832. #define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT      3
  833. #define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK      0x0000000000000008
  835. /*   SH_LOCAL_INT1_ENABLE_II_HW_INT                                     */
  836. /*   Description:  Enable II wrapper Hardware interrupt                 */
  837. #define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT      4
  838. #define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK      0x0000000000000010
  840. /*   SH_LOCAL_INT1_ENABLE_PI_CE_INT                                     */
  841. /*   Description:  Enable PI Correctable Error Interrupt                */
  842. #define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT      5
  843. #define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK      0x0000000000000020
  845. /*   SH_LOCAL_INT1_ENABLE_MD_CE_INT                                     */
  846. /*   Description:  Enable MD Correctable Error Interrupt                */
  847. #define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT      6
  848. #define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK      0x0000000000000040
  850. /*   SH_LOCAL_INT1_ENABLE_XN_CE_INT                                     */
  851. /*   Description:  Enable XN Correctable Error Interrupt                */
  852. #define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT      7
  853. #define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK      0x0000000000000080
  855. /*   SH_LOCAL_INT1_ENABLE_PI_UCE_INT                                    */
  856. /*   Description:  Enable PI Correctable Error Interrupt                */
  857. #define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT     8
  858. #define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
  860. /*   SH_LOCAL_INT1_ENABLE_MD_UCE_INT                                    */
  861. /*   Description:  Enable MD Correctable Error Interrupt                */
  862. #define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT     9
  863. #define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
  865. /*   SH_LOCAL_INT1_ENABLE_XN_UCE_INT                                    */
  866. /*   Description:  Enable XN Correctable Error Interrupt                */
  867. #define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT     10
  868. #define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
  870. /*   SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT                           */
  871. /*   Description:  Enable System Shutdown Interrupt                     */
  872. #define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
  873. #define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
  875. /*   SH_LOCAL_INT1_ENABLE_UART_INT                                      */
  876. /*   Description:  Enable Junk Bus UART Interrupt                       */
  877. #define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT       13
  878. #define SH_LOCAL_INT1_ENABLE_UART_INT_MASK       0x0000000000002000
  880. /*   SH_LOCAL_INT1_ENABLE_L1_NMI_INT                                    */
  881. /*   Description:  Enable L1 Controller NMI Interrupt                   */
  882. #define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT     14
  883. #define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
  885. /*   SH_LOCAL_INT1_ENABLE_STOP_CLOCK                                    */
  886. /*   Description:  Stop Clock Interrupt                                 */
  887. #define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT     15
  888. #define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
  890. /* ==================================================================== */
  891. /*                   Register "SH_LOCAL_INT2_CONFIG"                    */
  892. /*                   SHub Local Interrupt 2 Registers                   */
  893. /* ==================================================================== */
  895. #define SH_LOCAL_INT2_CONFIG                     0x0000000110000680
  896. #define SH_LOCAL_INT2_CONFIG_MASK                0x0ff3ffffffefffff
  897. #define SH_LOCAL_INT2_CONFIG_INIT                0x0000000000000000
  899. /*   SH_LOCAL_INT2_CONFIG_TYPE                                          */
  900. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  901. #define SH_LOCAL_INT2_CONFIG_TYPE_SHFT           0
  902. #define SH_LOCAL_INT2_CONFIG_TYPE_MASK           0x0000000000000007
  904. /*   SH_LOCAL_INT2_CONFIG_AGT                                           */
  905. /*   Description:  Agent, must be 0 for SHub                            */
  906. #define SH_LOCAL_INT2_CONFIG_AGT_SHFT            3
  907. #define SH_LOCAL_INT2_CONFIG_AGT_MASK            0x0000000000000008
  909. /*   SH_LOCAL_INT2_CONFIG_PID                                           */
  910. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  911. #define SH_LOCAL_INT2_CONFIG_PID_SHFT            4
  912. #define SH_LOCAL_INT2_CONFIG_PID_MASK            0x00000000000ffff0
  914. /*   SH_LOCAL_INT2_CONFIG_BASE                                          */
  915. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  916. #define SH_LOCAL_INT2_CONFIG_BASE_SHFT           21
  917. #define SH_LOCAL_INT2_CONFIG_BASE_MASK           0x0003ffffffe00000
  919. /*   SH_LOCAL_INT2_CONFIG_IDX                                           */
  920. /*   Description:  Targeted McKinley interrupt vector                   */
  921. #define SH_LOCAL_INT2_CONFIG_IDX_SHFT            52
  922. #define SH_LOCAL_INT2_CONFIG_IDX_MASK            0x0ff0000000000000
  924. /* ==================================================================== */
  925. /*                   Register "SH_LOCAL_INT2_ENABLE"                    */
  926. /*                    SHub Local Interrupt 2 Enable                     */
  927. /* ==================================================================== */
  929. #define SH_LOCAL_INT2_ENABLE                     0x0000000110000700
  930. #define SH_LOCAL_INT2_ENABLE_MASK                0x000000000000f7ff
  931. #define SH_LOCAL_INT2_ENABLE_INIT                0x0000000000000000
  933. /*   SH_LOCAL_INT2_ENABLE_PI_HW_INT                                     */
  934. /*   Description:  Enable PI Hardware interrupt                         */
  935. #define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT      0
  936. #define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK      0x0000000000000001
  938. /*   SH_LOCAL_INT2_ENABLE_MD_HW_INT                                     */
  939. /*   Description:  Enable MD Hardware interrupt                         */
  940. #define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT      1
  941. #define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK      0x0000000000000002
  943. /*   SH_LOCAL_INT2_ENABLE_XN_HW_INT                                     */
  944. /*   Description:  Enable XN Hardware interrupt                         */
  945. #define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT      2
  946. #define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK      0x0000000000000004
  948. /*   SH_LOCAL_INT2_ENABLE_LB_HW_INT                                     */
  949. /*   Description:  Enable LB Hardware interrupt                         */
  950. #define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT      3
  951. #define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK      0x0000000000000008
  953. /*   SH_LOCAL_INT2_ENABLE_II_HW_INT                                     */
  954. /*   Description:  Enable II wrapper Hardware interrupt                 */
  955. #define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT      4
  956. #define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK      0x0000000000000010
  958. /*   SH_LOCAL_INT2_ENABLE_PI_CE_INT                                     */
  959. /*   Description:  Enable PI Correctable Error Interrupt                */
  960. #define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT      5
  961. #define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK      0x0000000000000020
  963. /*   SH_LOCAL_INT2_ENABLE_MD_CE_INT                                     */
  964. /*   Description:  Enable MD Correctable Error Interrupt                */
  965. #define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT      6
  966. #define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK      0x0000000000000040
  968. /*   SH_LOCAL_INT2_ENABLE_XN_CE_INT                                     */
  969. /*   Description:  Enable XN Correctable Error Interrupt                */
  970. #define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT      7
  971. #define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK      0x0000000000000080
  973. /*   SH_LOCAL_INT2_ENABLE_PI_UCE_INT                                    */
  974. /*   Description:  Enable PI Correctable Error Interrupt                */
  975. #define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT     8
  976. #define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
  978. /*   SH_LOCAL_INT2_ENABLE_MD_UCE_INT                                    */
  979. /*   Description:  Enable MD Correctable Error Interrupt                */
  980. #define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT     9
  981. #define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
  983. /*   SH_LOCAL_INT2_ENABLE_XN_UCE_INT                                    */
  984. /*   Description:  Enable XN Correctable Error Interrupt                */
  985. #define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT     10
  986. #define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
  988. /*   SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT                           */
  989. /*   Description:  Enable System Shutdown Interrupt                     */
  990. #define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
  991. #define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
  993. /*   SH_LOCAL_INT2_ENABLE_UART_INT                                      */
  994. /*   Description:  Enable Junk Bus UART Interrupt                       */
  995. #define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT       13
  996. #define SH_LOCAL_INT2_ENABLE_UART_INT_MASK       0x0000000000002000
  998. /*   SH_LOCAL_INT2_ENABLE_L1_NMI_INT                                    */
  999. /*   Description:  Enable L1 Controller NMI Interrupt                   */
  1000. #define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT     14
  1001. #define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
  1003. /*   SH_LOCAL_INT2_ENABLE_STOP_CLOCK                                    */
  1004. /*   Description:  Stop Clock Interrupt                                 */
  1005. #define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT     15
  1006. #define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
  1008. /* ==================================================================== */
  1009. /*                   Register "SH_LOCAL_INT3_CONFIG"                    */
  1010. /*                   SHub Local Interrupt 3 Registers                   */
  1011. /* ==================================================================== */
  1013. #define SH_LOCAL_INT3_CONFIG                     0x0000000110000780
  1014. #define SH_LOCAL_INT3_CONFIG_MASK                0x0ff3ffffffefffff
  1015. #define SH_LOCAL_INT3_CONFIG_INIT                0x0000000000000000
  1017. /*   SH_LOCAL_INT3_CONFIG_TYPE                                          */
  1018. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1019. #define SH_LOCAL_INT3_CONFIG_TYPE_SHFT           0
  1020. #define SH_LOCAL_INT3_CONFIG_TYPE_MASK           0x0000000000000007
  1022. /*   SH_LOCAL_INT3_CONFIG_AGT                                           */
  1023. /*   Description:  Agent, must be 0 for SHub                            */
  1024. #define SH_LOCAL_INT3_CONFIG_AGT_SHFT            3
  1025. #define SH_LOCAL_INT3_CONFIG_AGT_MASK            0x0000000000000008
  1027. /*   SH_LOCAL_INT3_CONFIG_PID                                           */
  1028. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1029. #define SH_LOCAL_INT3_CONFIG_PID_SHFT            4
  1030. #define SH_LOCAL_INT3_CONFIG_PID_MASK            0x00000000000ffff0
  1032. /*   SH_LOCAL_INT3_CONFIG_BASE                                          */
  1033. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1034. #define SH_LOCAL_INT3_CONFIG_BASE_SHFT           21
  1035. #define SH_LOCAL_INT3_CONFIG_BASE_MASK           0x0003ffffffe00000
  1037. /*   SH_LOCAL_INT3_CONFIG_IDX                                           */
  1038. /*   Description:  Targeted McKinley interrupt vector                   */
  1039. #define SH_LOCAL_INT3_CONFIG_IDX_SHFT            52
  1040. #define SH_LOCAL_INT3_CONFIG_IDX_MASK            0x0ff0000000000000
  1042. /* ==================================================================== */
  1043. /*                   Register "SH_LOCAL_INT3_ENABLE"                    */
  1044. /*                    SHub Local Interrupt 3 Enable                     */
  1045. /* ==================================================================== */
  1047. #define SH_LOCAL_INT3_ENABLE                     0x0000000110000800
  1048. #define SH_LOCAL_INT3_ENABLE_MASK                0x000000000000f7ff
  1049. #define SH_LOCAL_INT3_ENABLE_INIT                0x0000000000000000
  1051. /*   SH_LOCAL_INT3_ENABLE_PI_HW_INT                                     */
  1052. /*   Description:  Enable PI Hardware interrupt                         */
  1053. #define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT      0
  1054. #define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK      0x0000000000000001
  1056. /*   SH_LOCAL_INT3_ENABLE_MD_HW_INT                                     */
  1057. /*   Description:  Enable MD Hardware interrupt                         */
  1058. #define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT      1
  1059. #define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK      0x0000000000000002
  1061. /*   SH_LOCAL_INT3_ENABLE_XN_HW_INT                                     */
  1062. /*   Description:  Enable XN Hardware interrupt                         */
  1063. #define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT      2
  1064. #define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK      0x0000000000000004
  1066. /*   SH_LOCAL_INT3_ENABLE_LB_HW_INT                                     */
  1067. /*   Description:  Enable LB Hardware interrupt                         */
  1068. #define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT      3
  1069. #define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK      0x0000000000000008
  1071. /*   SH_LOCAL_INT3_ENABLE_II_HW_INT                                     */
  1072. /*   Description:  Enable II wrapper Hardware interrupt                 */
  1073. #define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT      4
  1074. #define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK      0x0000000000000010
  1076. /*   SH_LOCAL_INT3_ENABLE_PI_CE_INT                                     */
  1077. /*   Description:  Enable PI Correctable Error Interrupt                */
  1078. #define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT      5
  1079. #define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK      0x0000000000000020
  1081. /*   SH_LOCAL_INT3_ENABLE_MD_CE_INT                                     */
  1082. /*   Description:  Enable MD Correctable Error Interrupt                */
  1083. #define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT      6
  1084. #define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK      0x0000000000000040
  1086. /*   SH_LOCAL_INT3_ENABLE_XN_CE_INT                                     */
  1087. /*   Description:  Enable XN Correctable Error Interrupt                */
  1088. #define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT      7
  1089. #define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK      0x0000000000000080
  1091. /*   SH_LOCAL_INT3_ENABLE_PI_UCE_INT                                    */
  1092. /*   Description:  Enable PI Correctable Error Interrupt                */
  1093. #define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT     8
  1094. #define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
  1096. /*   SH_LOCAL_INT3_ENABLE_MD_UCE_INT                                    */
  1097. /*   Description:  Enable MD Correctable Error Interrupt                */
  1098. #define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT     9
  1099. #define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
  1101. /*   SH_LOCAL_INT3_ENABLE_XN_UCE_INT                                    */
  1102. /*   Description:  Enable XN Correctable Error Interrupt                */
  1103. #define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT     10
  1104. #define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
  1106. /*   SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT                           */
  1107. /*   Description:  Enable System Shutdown Interrupt                     */
  1108. #define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
  1109. #define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
  1111. /*   SH_LOCAL_INT3_ENABLE_UART_INT                                      */
  1112. /*   Description:  Enable Junk Bus UART Interrupt                       */
  1113. #define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT       13
  1114. #define SH_LOCAL_INT3_ENABLE_UART_INT_MASK       0x0000000000002000
  1116. /*   SH_LOCAL_INT3_ENABLE_L1_NMI_INT                                    */
  1117. /*   Description:  Enable L1 Controller NMI Interrupt                   */
  1118. #define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT     14
  1119. #define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
  1121. /*   SH_LOCAL_INT3_ENABLE_STOP_CLOCK                                    */
  1122. /*   Description:  Stop Clock Interrupt                                 */
  1123. #define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT     15
  1124. #define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
  1126. /* ==================================================================== */
  1127. /*                   Register "SH_LOCAL_INT4_CONFIG"                    */
  1128. /*                   SHub Local Interrupt 4 Registers                   */
  1129. /* ==================================================================== */
  1131. #define SH_LOCAL_INT4_CONFIG                     0x0000000110000880
  1132. #define SH_LOCAL_INT4_CONFIG_MASK                0x0ff3ffffffefffff
  1133. #define SH_LOCAL_INT4_CONFIG_INIT                0x0000000000000000
  1135. /*   SH_LOCAL_INT4_CONFIG_TYPE                                          */
  1136. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1137. #define SH_LOCAL_INT4_CONFIG_TYPE_SHFT           0
  1138. #define SH_LOCAL_INT4_CONFIG_TYPE_MASK           0x0000000000000007
  1140. /*   SH_LOCAL_INT4_CONFIG_AGT                                           */
  1141. /*   Description:  Agent, must be 0 for SHub                            */
  1142. #define SH_LOCAL_INT4_CONFIG_AGT_SHFT            3
  1143. #define SH_LOCAL_INT4_CONFIG_AGT_MASK            0x0000000000000008
  1145. /*   SH_LOCAL_INT4_CONFIG_PID                                           */
  1146. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1147. #define SH_LOCAL_INT4_CONFIG_PID_SHFT            4
  1148. #define SH_LOCAL_INT4_CONFIG_PID_MASK            0x00000000000ffff0
  1150. /*   SH_LOCAL_INT4_CONFIG_BASE                                          */
  1151. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1152. #define SH_LOCAL_INT4_CONFIG_BASE_SHFT           21
  1153. #define SH_LOCAL_INT4_CONFIG_BASE_MASK           0x0003ffffffe00000
  1155. /*   SH_LOCAL_INT4_CONFIG_IDX                                           */
  1156. /*   Description:  Targeted McKinley interrupt vector                   */
  1157. #define SH_LOCAL_INT4_CONFIG_IDX_SHFT            52
  1158. #define SH_LOCAL_INT4_CONFIG_IDX_MASK            0x0ff0000000000000
  1160. /* ==================================================================== */
  1161. /*                   Register "SH_LOCAL_INT4_ENABLE"                    */
  1162. /*                    SHub Local Interrupt 4 Enable                     */
  1163. /* ==================================================================== */
  1165. #define SH_LOCAL_INT4_ENABLE                     0x0000000110000900
  1166. #define SH_LOCAL_INT4_ENABLE_MASK                0x000000000000f7ff
  1167. #define SH_LOCAL_INT4_ENABLE_INIT                0x0000000000000000
  1169. /*   SH_LOCAL_INT4_ENABLE_PI_HW_INT                                     */
  1170. /*   Description:  Enable PI Hardware interrupt                         */
  1171. #define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT      0
  1172. #define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK      0x0000000000000001
  1174. /*   SH_LOCAL_INT4_ENABLE_MD_HW_INT                                     */
  1175. /*   Description:  Enable MD Hardware interrupt                         */
  1176. #define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT      1
  1177. #define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK      0x0000000000000002
  1179. /*   SH_LOCAL_INT4_ENABLE_XN_HW_INT                                     */
  1180. /*   Description:  Enable XN Hardware interrupt                         */
  1181. #define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT      2
  1182. #define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK      0x0000000000000004
  1184. /*   SH_LOCAL_INT4_ENABLE_LB_HW_INT                                     */
  1185. /*   Description:  Enable LB Hardware interrupt                         */
  1186. #define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT      3
  1187. #define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK      0x0000000000000008
  1189. /*   SH_LOCAL_INT4_ENABLE_II_HW_INT                                     */
  1190. /*   Description:  Enable II wrapper Hardware interrupt                 */
  1191. #define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT      4
  1192. #define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK      0x0000000000000010
  1194. /*   SH_LOCAL_INT4_ENABLE_PI_CE_INT                                     */
  1195. /*   Description:  Enable PI Correctable Error Interrupt                */
  1196. #define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT      5
  1197. #define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK      0x0000000000000020
  1199. /*   SH_LOCAL_INT4_ENABLE_MD_CE_INT                                     */
  1200. /*   Description:  Enable MD Correctable Error Interrupt                */
  1201. #define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT      6
  1202. #define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK      0x0000000000000040
  1204. /*   SH_LOCAL_INT4_ENABLE_XN_CE_INT                                     */
  1205. /*   Description:  Enable XN Correctable Error Interrupt                */
  1206. #define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT      7
  1207. #define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK      0x0000000000000080
  1209. /*   SH_LOCAL_INT4_ENABLE_PI_UCE_INT                                    */
  1210. /*   Description:  Enable PI Correctable Error Interrupt                */
  1211. #define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT     8
  1212. #define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
  1214. /*   SH_LOCAL_INT4_ENABLE_MD_UCE_INT                                    */
  1215. /*   Description:  Enable MD Correctable Error Interrupt                */
  1216. #define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT     9
  1217. #define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
  1219. /*   SH_LOCAL_INT4_ENABLE_XN_UCE_INT                                    */
  1220. /*   Description:  Enable XN Correctable Error Interrupt                */
  1221. #define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT     10
  1222. #define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
  1224. /*   SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT                           */
  1225. /*   Description:  Enable System Shutdown Interrupt                     */
  1226. #define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
  1227. #define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
  1229. /*   SH_LOCAL_INT4_ENABLE_UART_INT                                      */
  1230. /*   Description:  Enable Junk Bus UART Interrupt                       */
  1231. #define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT       13
  1232. #define SH_LOCAL_INT4_ENABLE_UART_INT_MASK       0x0000000000002000
  1234. /*   SH_LOCAL_INT4_ENABLE_L1_NMI_INT                                    */
  1235. /*   Description:  Enable L1 Controller NMI Interrupt                   */
  1236. #define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT     14
  1237. #define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
  1239. /*   SH_LOCAL_INT4_ENABLE_STOP_CLOCK                                    */
  1240. /*   Description:  Stop Clock Interrupt                                 */
  1241. #define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT     15
  1242. #define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
  1244. /* ==================================================================== */
  1245. /*                   Register "SH_LOCAL_INT5_CONFIG"                    */
  1246. /*                   SHub Local Interrupt 5 Registers                   */
  1247. /* ==================================================================== */
  1249. #define SH_LOCAL_INT5_CONFIG                     0x0000000110000980
  1250. #define SH_LOCAL_INT5_CONFIG_MASK                0x0ff3ffffffefffff
  1251. #define SH_LOCAL_INT5_CONFIG_INIT                0x0000000000000000
  1253. /*   SH_LOCAL_INT5_CONFIG_TYPE                                          */
  1254. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1255. #define SH_LOCAL_INT5_CONFIG_TYPE_SHFT           0
  1256. #define SH_LOCAL_INT5_CONFIG_TYPE_MASK           0x0000000000000007
  1258. /*   SH_LOCAL_INT5_CONFIG_AGT                                           */
  1259. /*   Description:  Agent, must be 0 for SHub                            */
  1260. #define SH_LOCAL_INT5_CONFIG_AGT_SHFT            3
  1261. #define SH_LOCAL_INT5_CONFIG_AGT_MASK            0x0000000000000008
  1263. /*   SH_LOCAL_INT5_CONFIG_PID                                           */
  1264. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1265. #define SH_LOCAL_INT5_CONFIG_PID_SHFT            4
  1266. #define SH_LOCAL_INT5_CONFIG_PID_MASK            0x00000000000ffff0
  1268. /*   SH_LOCAL_INT5_CONFIG_BASE                                          */
  1269. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1270. #define SH_LOCAL_INT5_CONFIG_BASE_SHFT           21
  1271. #define SH_LOCAL_INT5_CONFIG_BASE_MASK           0x0003ffffffe00000
  1273. /*   SH_LOCAL_INT5_CONFIG_IDX                                           */
  1274. /*   Description:  Targeted McKinley interrupt vector                   */
  1275. #define SH_LOCAL_INT5_CONFIG_IDX_SHFT            52
  1276. #define SH_LOCAL_INT5_CONFIG_IDX_MASK            0x0ff0000000000000
  1278. /* ==================================================================== */
  1279. /*                   Register "SH_LOCAL_INT5_ENABLE"                    */
  1280. /*                    SHub Local Interrupt 5 Enable                     */
  1281. /* ==================================================================== */
  1283. #define SH_LOCAL_INT5_ENABLE                     0x0000000110000a00
  1284. #define SH_LOCAL_INT5_ENABLE_MASK                0x000000000000f7ff
  1285. #define SH_LOCAL_INT5_ENABLE_INIT                0x0000000000000000
  1287. /*   SH_LOCAL_INT5_ENABLE_PI_HW_INT                                     */
  1288. /*   Description:  Enable PI Hardware interrupt                         */
  1289. #define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT      0
  1290. #define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK      0x0000000000000001
  1292. /*   SH_LOCAL_INT5_ENABLE_MD_HW_INT                                     */
  1293. /*   Description:  Enable MD Hardware interrupt                         */
  1294. #define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT      1
  1295. #define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK      0x0000000000000002
  1297. /*   SH_LOCAL_INT5_ENABLE_XN_HW_INT                                     */
  1298. /*   Description:  Enable XN Hardware interrupt                         */
  1299. #define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT      2
  1300. #define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK      0x0000000000000004
  1302. /*   SH_LOCAL_INT5_ENABLE_LB_HW_INT                                     */
  1303. /*   Description:  Enable LB Hardware interrupt                         */
  1304. #define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT      3
  1305. #define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK      0x0000000000000008
  1307. /*   SH_LOCAL_INT5_ENABLE_II_HW_INT                                     */
  1308. /*   Description:  Enable II wrapper Hardware interrupt                 */
  1309. #define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT      4
  1310. #define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK      0x0000000000000010
  1312. /*   SH_LOCAL_INT5_ENABLE_PI_CE_INT                                     */
  1313. /*   Description:  Enable PI Correctable Error Interrupt                */
  1314. #define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT      5
  1315. #define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK      0x0000000000000020
  1317. /*   SH_LOCAL_INT5_ENABLE_MD_CE_INT                                     */
  1318. /*   Description:  Enable MD Correctable Error Interrupt                */
  1319. #define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT      6
  1320. #define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK      0x0000000000000040
  1322. /*   SH_LOCAL_INT5_ENABLE_XN_CE_INT                                     */
  1323. /*   Description:  Enable XN Correctable Error Interrupt                */
  1324. #define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT      7
  1325. #define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK      0x0000000000000080
  1327. /*   SH_LOCAL_INT5_ENABLE_PI_UCE_INT                                    */
  1328. /*   Description:  Enable PI Correctable Error Interrupt                */
  1329. #define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT     8
  1330. #define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
  1332. /*   SH_LOCAL_INT5_ENABLE_MD_UCE_INT                                    */
  1333. /*   Description:  Enable MD Correctable Error Interrupt                */
  1334. #define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT     9
  1335. #define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
  1337. /*   SH_LOCAL_INT5_ENABLE_XN_UCE_INT                                    */
  1338. /*   Description:  Enable XN Correctable Error Interrupt                */
  1339. #define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT     10
  1340. #define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
  1342. /*   SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT                           */
  1343. /*   Description:  Enable System Shutdown Interrupt                     */
  1344. #define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
  1345. #define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
  1347. /*   SH_LOCAL_INT5_ENABLE_UART_INT                                      */
  1348. /*   Description:  Enable Junk Bus UART Interrupt                       */
  1349. #define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT       13
  1350. #define SH_LOCAL_INT5_ENABLE_UART_INT_MASK       0x0000000000002000
  1352. /*   SH_LOCAL_INT5_ENABLE_L1_NMI_INT                                    */
  1353. /*   Description:  Enable L1 Controller NMI Interrupt                   */
  1354. #define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT     14
  1355. #define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
  1357. /*   SH_LOCAL_INT5_ENABLE_STOP_CLOCK                                    */
  1358. /*   Description:  Stop Clock Interrupt                                 */
  1359. #define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT     15
  1360. #define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
  1362. /* ==================================================================== */
  1363. /*                  Register "SH_PROC0_ERR_INT_CONFIG"                  */
  1364. /*              SHub Processor 0 Error Interrupt Registers              */
  1365. /* ==================================================================== */
  1367. #define SH_PROC0_ERR_INT_CONFIG                  0x0000000110000a80
  1368. #define SH_PROC0_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1369. #define SH_PROC0_ERR_INT_CONFIG_INIT             0x0000000000000000
  1371. /*   SH_PROC0_ERR_INT_CONFIG_TYPE                                       */
  1372. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1373. #define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT        0
  1374. #define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1376. /*   SH_PROC0_ERR_INT_CONFIG_AGT                                        */
  1377. /*   Description:  Agent, must be 0 for SHub                            */
  1378. #define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT         3
  1379. #define SH_PROC0_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
  1381. /*   SH_PROC0_ERR_INT_CONFIG_PID                                        */
  1382. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1383. #define SH_PROC0_ERR_INT_CONFIG_PID_SHFT         4
  1384. #define SH_PROC0_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1386. /*   SH_PROC0_ERR_INT_CONFIG_BASE                                       */
  1387. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1388. #define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT        21
  1389. #define SH_PROC0_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1391. /*   SH_PROC0_ERR_INT_CONFIG_IDX                                        */
  1392. /*   Description:  Targeted McKinley interrupt vector                   */
  1393. #define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT         52
  1394. #define SH_PROC0_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1396. /* ==================================================================== */
  1397. /*                  Register "SH_PROC1_ERR_INT_CONFIG"                  */
  1398. /*              SHub Processor 1 Error Interrupt Registers              */
  1399. /* ==================================================================== */
  1401. #define SH_PROC1_ERR_INT_CONFIG                  0x0000000110000b00
  1402. #define SH_PROC1_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1403. #define SH_PROC1_ERR_INT_CONFIG_INIT             0x0000000000000000
  1405. /*   SH_PROC1_ERR_INT_CONFIG_TYPE                                       */
  1406. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1407. #define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT        0
  1408. #define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1410. /*   SH_PROC1_ERR_INT_CONFIG_AGT                                        */
  1411. /*   Description:  Agent, must be 0 for SHub                            */
  1412. #define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT         3
  1413. #define SH_PROC1_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
  1415. /*   SH_PROC1_ERR_INT_CONFIG_PID                                        */
  1416. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1417. #define SH_PROC1_ERR_INT_CONFIG_PID_SHFT         4
  1418. #define SH_PROC1_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1420. /*   SH_PROC1_ERR_INT_CONFIG_BASE                                       */
  1421. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1422. #define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT        21
  1423. #define SH_PROC1_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1425. /*   SH_PROC1_ERR_INT_CONFIG_IDX                                        */
  1426. /*   Description:  Targeted McKinley interrupt vector                   */
  1427. #define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT         52
  1428. #define SH_PROC1_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1430. /* ==================================================================== */
  1431. /*                  Register "SH_PROC2_ERR_INT_CONFIG"                  */
  1432. /*              SHub Processor 2 Error Interrupt Registers              */
  1433. /* ==================================================================== */
  1435. #define SH_PROC2_ERR_INT_CONFIG                  0x0000000110000b80
  1436. #define SH_PROC2_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1437. #define SH_PROC2_ERR_INT_CONFIG_INIT             0x0000000000000000
  1439. /*   SH_PROC2_ERR_INT_CONFIG_TYPE                                       */
  1440. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1441. #define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT        0
  1442. #define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1444. /*   SH_PROC2_ERR_INT_CONFIG_AGT                                        */
  1445. /*   Description:  Agent, must be 0 for SHub                            */
  1446. #define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT         3
  1447. #define SH_PROC2_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
  1449. /*   SH_PROC2_ERR_INT_CONFIG_PID                                        */
  1450. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1451. #define SH_PROC2_ERR_INT_CONFIG_PID_SHFT         4
  1452. #define SH_PROC2_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1454. /*   SH_PROC2_ERR_INT_CONFIG_BASE                                       */
  1455. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1456. #define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT        21
  1457. #define SH_PROC2_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1459. /*   SH_PROC2_ERR_INT_CONFIG_IDX                                        */
  1460. /*   Description:  Targeted McKinley interrupt vector                   */
  1461. #define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT         52
  1462. #define SH_PROC2_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1464. /* ==================================================================== */
  1465. /*                  Register "SH_PROC3_ERR_INT_CONFIG"                  */
  1466. /*              SHub Processor 3 Error Interrupt Registers              */
  1467. /* ==================================================================== */
  1469. #define SH_PROC3_ERR_INT_CONFIG                  0x0000000110000c00
  1470. #define SH_PROC3_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1471. #define SH_PROC3_ERR_INT_CONFIG_INIT             0x0000000000000000
  1473. /*   SH_PROC3_ERR_INT_CONFIG_TYPE                                       */
  1474. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1475. #define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT        0
  1476. #define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1478. /*   SH_PROC3_ERR_INT_CONFIG_AGT                                        */
  1479. /*   Description:  Agent, must be 0 for SHub                            */
  1480. #define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT         3
  1481. #define SH_PROC3_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
  1483. /*   SH_PROC3_ERR_INT_CONFIG_PID                                        */
  1484. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1485. #define SH_PROC3_ERR_INT_CONFIG_PID_SHFT         4
  1486. #define SH_PROC3_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1488. /*   SH_PROC3_ERR_INT_CONFIG_BASE                                       */
  1489. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1490. #define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT        21
  1491. #define SH_PROC3_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1493. /*   SH_PROC3_ERR_INT_CONFIG_IDX                                        */
  1494. /*   Description:  Targeted McKinley interrupt vector                   */
  1495. #define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT         52
  1496. #define SH_PROC3_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1498. /* ==================================================================== */
  1499. /*                  Register "SH_PROC0_ADV_INT_CONFIG"                  */
  1500. /*            SHub Processor 0 Advisory Interrupt Registers             */
  1501. /* ==================================================================== */
  1503. #define SH_PROC0_ADV_INT_CONFIG                  0x0000000110000c80
  1504. #define SH_PROC0_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1505. #define SH_PROC0_ADV_INT_CONFIG_INIT             0x0000000000000000
  1507. /*   SH_PROC0_ADV_INT_CONFIG_TYPE                                       */
  1508. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1509. #define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT        0
  1510. #define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1512. /*   SH_PROC0_ADV_INT_CONFIG_AGT                                        */
  1513. /*   Description:  Agent, must be 0 for SHub                            */
  1514. #define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT         3
  1515. #define SH_PROC0_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
  1517. /*   SH_PROC0_ADV_INT_CONFIG_PID                                        */
  1518. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1519. #define SH_PROC0_ADV_INT_CONFIG_PID_SHFT         4
  1520. #define SH_PROC0_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1522. /*   SH_PROC0_ADV_INT_CONFIG_BASE                                       */
  1523. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1524. #define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT        21
  1525. #define SH_PROC0_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1527. /*   SH_PROC0_ADV_INT_CONFIG_IDX                                        */
  1528. /*   Description:  Targeted McKinley interrupt vector                   */
  1529. #define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT         52
  1530. #define SH_PROC0_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1532. /* ==================================================================== */
  1533. /*                  Register "SH_PROC1_ADV_INT_CONFIG"                  */
  1534. /*            SHub Processor 1 Advisory Interrupt Registers             */
  1535. /* ==================================================================== */
  1537. #define SH_PROC1_ADV_INT_CONFIG                  0x0000000110000d00
  1538. #define SH_PROC1_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1539. #define SH_PROC1_ADV_INT_CONFIG_INIT             0x0000000000000000
  1541. /*   SH_PROC1_ADV_INT_CONFIG_TYPE                                       */
  1542. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1543. #define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT        0
  1544. #define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1546. /*   SH_PROC1_ADV_INT_CONFIG_AGT                                        */
  1547. /*   Description:  Agent, must be 0 for SHub                            */
  1548. #define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT         3
  1549. #define SH_PROC1_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
  1551. /*   SH_PROC1_ADV_INT_CONFIG_PID                                        */
  1552. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1553. #define SH_PROC1_ADV_INT_CONFIG_PID_SHFT         4
  1554. #define SH_PROC1_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1556. /*   SH_PROC1_ADV_INT_CONFIG_BASE                                       */
  1557. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1558. #define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT        21
  1559. #define SH_PROC1_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1561. /*   SH_PROC1_ADV_INT_CONFIG_IDX                                        */
  1562. /*   Description:  Targeted McKinley interrupt vector                   */
  1563. #define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT         52
  1564. #define SH_PROC1_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1566. /* ==================================================================== */
  1567. /*                  Register "SH_PROC2_ADV_INT_CONFIG"                  */
  1568. /*            SHub Processor 2 Advisory Interrupt Registers             */
  1569. /* ==================================================================== */
  1571. #define SH_PROC2_ADV_INT_CONFIG                  0x0000000110000d80
  1572. #define SH_PROC2_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1573. #define SH_PROC2_ADV_INT_CONFIG_INIT             0x0000000000000000
  1575. /*   SH_PROC2_ADV_INT_CONFIG_TYPE                                       */
  1576. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1577. #define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT        0
  1578. #define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1580. /*   SH_PROC2_ADV_INT_CONFIG_AGT                                        */
  1581. /*   Description:  Agent, must be 0 for SHub                            */
  1582. #define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT         3
  1583. #define SH_PROC2_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
  1585. /*   SH_PROC2_ADV_INT_CONFIG_PID                                        */
  1586. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1587. #define SH_PROC2_ADV_INT_CONFIG_PID_SHFT         4
  1588. #define SH_PROC2_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1590. /*   SH_PROC2_ADV_INT_CONFIG_BASE                                       */
  1591. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1592. #define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT        21
  1593. #define SH_PROC2_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1595. /*   SH_PROC2_ADV_INT_CONFIG_IDX                                        */
  1596. /*   Description:  Targeted McKinley interrupt vector                   */
  1597. #define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT         52
  1598. #define SH_PROC2_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1600. /* ==================================================================== */
  1601. /*                  Register "SH_PROC3_ADV_INT_CONFIG"                  */
  1602. /*            SHub Processor 3 Advisory Interrupt Registers             */
  1603. /* ==================================================================== */
  1605. #define SH_PROC3_ADV_INT_CONFIG                  0x0000000110000e00
  1606. #define SH_PROC3_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
  1607. #define SH_PROC3_ADV_INT_CONFIG_INIT             0x0000000000000000
  1609. /*   SH_PROC3_ADV_INT_CONFIG_TYPE                                       */
  1610. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1611. #define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT        0
  1612. #define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
  1614. /*   SH_PROC3_ADV_INT_CONFIG_AGT                                        */
  1615. /*   Description:  Agent, must be 0 for SHub                            */
  1616. #define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT         3
  1617. #define SH_PROC3_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
  1619. /*   SH_PROC3_ADV_INT_CONFIG_PID                                        */
  1620. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1621. #define SH_PROC3_ADV_INT_CONFIG_PID_SHFT         4
  1622. #define SH_PROC3_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
  1624. /*   SH_PROC3_ADV_INT_CONFIG_BASE                                       */
  1625. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1626. #define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT        21
  1627. #define SH_PROC3_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
  1629. /*   SH_PROC3_ADV_INT_CONFIG_IDX                                        */
  1630. /*   Description:  Targeted McKinley interrupt vector                   */
  1631. #define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT         52
  1632. #define SH_PROC3_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
  1634. /* ==================================================================== */
  1635. /*                  Register "SH_PROC0_ERR_INT_ENABLE"                  */
  1636. /*          SHub Processor 0 Error Interrupt Enable Registers           */
  1637. /* ==================================================================== */
  1639. #define SH_PROC0_ERR_INT_ENABLE                  0x0000000110000e80
  1640. #define SH_PROC0_ERR_INT_ENABLE_MASK             0x0000000000000001
  1641. #define SH_PROC0_ERR_INT_ENABLE_INIT             0x0000000000000000
  1643. /*   SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE                           */
  1644. /*   Description:  Enable Processor 0 Error Interrupt                   */
  1645. #define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0
  1646. #define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001
  1648. /* ==================================================================== */
  1649. /*                  Register "SH_PROC1_ERR_INT_ENABLE"                  */
  1650. /*          SHub Processor 1 Error Interrupt Enable Registers           */
  1651. /* ==================================================================== */
  1653. #define SH_PROC1_ERR_INT_ENABLE                  0x0000000110000f00
  1654. #define SH_PROC1_ERR_INT_ENABLE_MASK             0x0000000000000001
  1655. #define SH_PROC1_ERR_INT_ENABLE_INIT             0x0000000000000000
  1657. /*   SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE                           */
  1658. /*   Description:  Enable Processor 1 Error Interrupt                   */
  1659. #define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0
  1660. #define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001
  1662. /* ==================================================================== */
  1663. /*                  Register "SH_PROC2_ERR_INT_ENABLE"                  */
  1664. /*          SHub Processor 2 Error Interrupt Enable Registers           */
  1665. /* ==================================================================== */
  1667. #define SH_PROC2_ERR_INT_ENABLE                  0x0000000110000f80
  1668. #define SH_PROC2_ERR_INT_ENABLE_MASK             0x0000000000000001
  1669. #define SH_PROC2_ERR_INT_ENABLE_INIT             0x0000000000000000
  1671. /*   SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE                           */
  1672. /*   Description:  Enable Processor 2 Error Interrupt                   */
  1673. #define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0
  1674. #define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001
  1676. /* ==================================================================== */
  1677. /*                  Register "SH_PROC3_ERR_INT_ENABLE"                  */
  1678. /*          SHub Processor 3 Error Interrupt Enable Registers           */
  1679. /* ==================================================================== */
  1681. #define SH_PROC3_ERR_INT_ENABLE                  0x0000000110001000
  1682. #define SH_PROC3_ERR_INT_ENABLE_MASK             0x0000000000000001
  1683. #define SH_PROC3_ERR_INT_ENABLE_INIT             0x0000000000000000
  1685. /*   SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE                           */
  1686. /*   Description:  Enable Processor 3 Error Interrupt                   */
  1687. #define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0
  1688. #define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001
  1690. /* ==================================================================== */
  1691. /*                  Register "SH_PROC0_ADV_INT_ENABLE"                  */
  1692. /*         SHub Processor 0 Advisory Interrupt Enable Registers         */
  1693. /* ==================================================================== */
  1695. #define SH_PROC0_ADV_INT_ENABLE                  0x0000000110001080
  1696. #define SH_PROC0_ADV_INT_ENABLE_MASK             0x0000000000000001
  1697. #define SH_PROC0_ADV_INT_ENABLE_INIT             0x0000000000000000
  1699. /*   SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE                           */
  1700. /*   Description:  Enable Processor 0 Advisory Interrupt                */
  1701. #define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0
  1702. #define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001
  1704. /* ==================================================================== */
  1705. /*                  Register "SH_PROC1_ADV_INT_ENABLE"                  */
  1706. /*         SHub Processor 1 Advisory Interrupt Enable Registers         */
  1707. /* ==================================================================== */
  1709. #define SH_PROC1_ADV_INT_ENABLE                  0x0000000110001100
  1710. #define SH_PROC1_ADV_INT_ENABLE_MASK             0x0000000000000001
  1711. #define SH_PROC1_ADV_INT_ENABLE_INIT             0x0000000000000000
  1713. /*   SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE                           */
  1714. /*   Description:  Enable Processor 1 Advisory Interrupt                */
  1715. #define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0
  1716. #define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001
  1718. /* ==================================================================== */
  1719. /*                  Register "SH_PROC2_ADV_INT_ENABLE"                  */
  1720. /*         SHub Processor 2 Advisory Interrupt Enable Registers         */
  1721. /* ==================================================================== */
  1723. #define SH_PROC2_ADV_INT_ENABLE                  0x0000000110001180
  1724. #define SH_PROC2_ADV_INT_ENABLE_MASK             0x0000000000000001
  1725. #define SH_PROC2_ADV_INT_ENABLE_INIT             0x0000000000000000
  1727. /*   SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE                           */
  1728. /*   Description:  Enable Processor 2 Advisory Interrupt                */
  1729. #define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0
  1730. #define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001
  1732. /* ==================================================================== */
  1733. /*                  Register "SH_PROC3_ADV_INT_ENABLE"                  */
  1734. /*         SHub Processor 3 Advisory Interrupt Enable Registers         */
  1735. /* ==================================================================== */
  1737. #define SH_PROC3_ADV_INT_ENABLE                  0x0000000110001200
  1738. #define SH_PROC3_ADV_INT_ENABLE_MASK             0x0000000000000001
  1739. #define SH_PROC3_ADV_INT_ENABLE_INIT             0x0000000000000000
  1741. /*   SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE                           */
  1742. /*   Description:  Enable Processor 3 Advisory Interrupt                */
  1743. #define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0
  1744. #define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001
  1746. /* ==================================================================== */
  1747. /*                   Register "SH_PROFILE_INT_CONFIG"                   */
  1748. /*            SHub Profile Interrupt Configuration Registers            */
  1749. /* ==================================================================== */
  1751. #define SH_PROFILE_INT_CONFIG                    0x0000000110001280
  1752. #define SH_PROFILE_INT_CONFIG_MASK               0x0ff3ffffffefffff
  1753. #define SH_PROFILE_INT_CONFIG_INIT               0x0000000000000000
  1755. /*   SH_PROFILE_INT_CONFIG_TYPE                                         */
  1756. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1757. #define SH_PROFILE_INT_CONFIG_TYPE_SHFT          0
  1758. #define SH_PROFILE_INT_CONFIG_TYPE_MASK          0x0000000000000007
  1760. /*   SH_PROFILE_INT_CONFIG_AGT                                          */
  1761. /*   Description:  Agent, must be 0 for SHub                            */
  1762. #define SH_PROFILE_INT_CONFIG_AGT_SHFT           3
  1763. #define SH_PROFILE_INT_CONFIG_AGT_MASK           0x0000000000000008
  1765. /*   SH_PROFILE_INT_CONFIG_PID                                          */
  1766. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1767. #define SH_PROFILE_INT_CONFIG_PID_SHFT           4
  1768. #define SH_PROFILE_INT_CONFIG_PID_MASK           0x00000000000ffff0
  1770. /*   SH_PROFILE_INT_CONFIG_BASE                                         */
  1771. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1772. #define SH_PROFILE_INT_CONFIG_BASE_SHFT          21
  1773. #define SH_PROFILE_INT_CONFIG_BASE_MASK          0x0003ffffffe00000
  1775. /*   SH_PROFILE_INT_CONFIG_IDX                                          */
  1776. /*   Description:  Targeted McKinley interrupt vector                   */
  1777. #define SH_PROFILE_INT_CONFIG_IDX_SHFT           52
  1778. #define SH_PROFILE_INT_CONFIG_IDX_MASK           0x0ff0000000000000
  1780. /* ==================================================================== */
  1781. /*                   Register "SH_PROFILE_INT_ENABLE"                   */
  1782. /*               SHub Profile Interrupt Enable Registers                */
  1783. /* ==================================================================== */
  1785. #define SH_PROFILE_INT_ENABLE                    0x0000000110001300
  1786. #define SH_PROFILE_INT_ENABLE_MASK               0x0000000000000001
  1787. #define SH_PROFILE_INT_ENABLE_INIT               0x0000000000000000
  1789. /*   SH_PROFILE_INT_ENABLE_PROFILE_ENABLE                               */
  1790. /*   Description:  Enable Profile Interrupt                             */
  1791. #define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0
  1792. #define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001
  1794. /* ==================================================================== */
  1795. /*                    Register "SH_RTC0_INT_CONFIG"                     */
  1796. /*                SHub RTC 0 Interrupt Config Registers                 */
  1797. /* ==================================================================== */
  1799. #define SH_RTC0_INT_CONFIG                       0x0000000110001380
  1800. #define SH_RTC0_INT_CONFIG_MASK                  0x0ff3ffffffefffff
  1801. #define SH_RTC0_INT_CONFIG_INIT                  0x0000000000000000
  1803. /*   SH_RTC0_INT_CONFIG_TYPE                                            */
  1804. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1805. #define SH_RTC0_INT_CONFIG_TYPE_SHFT             0
  1806. #define SH_RTC0_INT_CONFIG_TYPE_MASK             0x0000000000000007
  1808. /*   SH_RTC0_INT_CONFIG_AGT                                             */
  1809. /*   Description:  Agent, must be 0 for SHub                            */
  1810. #define SH_RTC0_INT_CONFIG_AGT_SHFT              3
  1811. #define SH_RTC0_INT_CONFIG_AGT_MASK              0x0000000000000008
  1813. /*   SH_RTC0_INT_CONFIG_PID                                             */
  1814. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1815. #define SH_RTC0_INT_CONFIG_PID_SHFT              4
  1816. #define SH_RTC0_INT_CONFIG_PID_MASK              0x00000000000ffff0
  1818. /*   SH_RTC0_INT_CONFIG_BASE                                            */
  1819. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1820. #define SH_RTC0_INT_CONFIG_BASE_SHFT             21
  1821. #define SH_RTC0_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
  1823. /*   SH_RTC0_INT_CONFIG_IDX                                             */
  1824. /*   Description:  Targeted McKinley interrupt vector                   */
  1825. #define SH_RTC0_INT_CONFIG_IDX_SHFT              52
  1826. #define SH_RTC0_INT_CONFIG_IDX_MASK              0x0ff0000000000000
  1828. /* ==================================================================== */
  1829. /*                    Register "SH_RTC0_INT_ENABLE"                     */
  1830. /*                SHub RTC 0 Interrupt Enable Registers                 */
  1831. /* ==================================================================== */
  1833. #define SH_RTC0_INT_ENABLE                       0x0000000110001400
  1834. #define SH_RTC0_INT_ENABLE_MASK                  0x0000000000000001
  1835. #define SH_RTC0_INT_ENABLE_INIT                  0x0000000000000000
  1837. /*   SH_RTC0_INT_ENABLE_RTC0_ENABLE                                     */
  1838. /*   Description:  Enable RTC 0 Interrupt                               */
  1839. #define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT      0
  1840. #define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK      0x0000000000000001
  1842. /* ==================================================================== */
  1843. /*                    Register "SH_RTC1_INT_CONFIG"                     */
  1844. /*                SHub RTC 1 Interrupt Config Registers                 */
  1845. /* ==================================================================== */
  1847. #define SH_RTC1_INT_CONFIG                       0x0000000110001480
  1848. #define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
  1849. #define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
  1851. /*   SH_RTC1_INT_CONFIG_TYPE                                            */
  1852. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1853. #define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
  1854. #define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
  1856. /*   SH_RTC1_INT_CONFIG_AGT                                             */
  1857. /*   Description:  Agent, must be 0 for SHub                            */
  1858. #define SH_RTC1_INT_CONFIG_AGT_SHFT              3
  1859. #define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
  1861. /*   SH_RTC1_INT_CONFIG_PID                                             */
  1862. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1863. #define SH_RTC1_INT_CONFIG_PID_SHFT              4
  1864. #define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
  1866. /*   SH_RTC1_INT_CONFIG_BASE                                            */
  1867. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1868. #define SH_RTC1_INT_CONFIG_BASE_SHFT             21
  1869. #define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
  1871. /*   SH_RTC1_INT_CONFIG_IDX                                             */
  1872. /*   Description:  Targeted McKinley interrupt vector                   */
  1873. #define SH_RTC1_INT_CONFIG_IDX_SHFT              52
  1874. #define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
  1876. /* ==================================================================== */
  1877. /*                    Register "SH_RTC1_INT_ENABLE"                     */
  1878. /*                SHub RTC 1 Interrupt Enable Registers                 */
  1879. /* ==================================================================== */
  1881. #define SH_RTC1_INT_ENABLE                       0x0000000110001500
  1882. #define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
  1883. #define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
  1885. /*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
  1886. /*   Description:  Enable RTC 1 Interrupt                               */
  1887. #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
  1888. #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
  1890. /* ==================================================================== */
  1891. /*                    Register "SH_RTC2_INT_CONFIG"                     */
  1892. /*                SHub RTC 2 Interrupt Config Registers                 */
  1893. /* ==================================================================== */
  1895. #define SH_RTC2_INT_CONFIG                       0x0000000110001580
  1896. #define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
  1897. #define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
  1899. /*   SH_RTC2_INT_CONFIG_TYPE                                            */
  1900. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1901. #define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
  1902. #define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
  1904. /*   SH_RTC2_INT_CONFIG_AGT                                             */
  1905. /*   Description:  Agent, must be 0 for SHub                            */
  1906. #define SH_RTC2_INT_CONFIG_AGT_SHFT              3
  1907. #define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
  1909. /*   SH_RTC2_INT_CONFIG_PID                                             */
  1910. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1911. #define SH_RTC2_INT_CONFIG_PID_SHFT              4
  1912. #define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
  1914. /*   SH_RTC2_INT_CONFIG_BASE                                            */
  1915. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1916. #define SH_RTC2_INT_CONFIG_BASE_SHFT             21
  1917. #define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
  1919. /*   SH_RTC2_INT_CONFIG_IDX                                             */
  1920. /*   Description:  Targeted McKinley interrupt vector                   */
  1921. #define SH_RTC2_INT_CONFIG_IDX_SHFT              52
  1922. #define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
  1924. /* ==================================================================== */
  1925. /*                    Register "SH_RTC2_INT_ENABLE"                     */
  1926. /*                SHub RTC 2 Interrupt Enable Registers                 */
  1927. /* ==================================================================== */
  1929. #define SH_RTC2_INT_ENABLE                       0x0000000110001600
  1930. #define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
  1931. #define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
  1933. /*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
  1934. /*   Description:  Enable RTC 2 Interrupt                               */
  1935. #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
  1936. #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
  1938. /* ==================================================================== */
  1939. /*                    Register "SH_RTC3_INT_CONFIG"                     */
  1940. /*                SHub RTC 3 Interrupt Config Registers                 */
  1941. /* ==================================================================== */
  1943. #define SH_RTC3_INT_CONFIG                       0x0000000110001680
  1944. #define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
  1945. #define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
  1947. /*   SH_RTC3_INT_CONFIG_TYPE                                            */
  1948. /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  1949. #define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
  1950. #define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
  1952. /*   SH_RTC3_INT_CONFIG_AGT                                             */
  1953. /*   Description:  Agent, must be 0 for SHub                            */
  1954. #define SH_RTC3_INT_CONFIG_AGT_SHFT              3
  1955. #define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
  1957. /*   SH_RTC3_INT_CONFIG_PID                                             */
  1958. /*   Description:  Processor ID, same setting as on targeted McKinley  */
  1959. #define SH_RTC3_INT_CONFIG_PID_SHFT              4
  1960. #define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
  1962. /*   SH_RTC3_INT_CONFIG_BASE                                            */
  1963. /*   Description:  Optional interrupt vector area, 2MB aligned          */
  1964. #define SH_RTC3_INT_CONFIG_BASE_SHFT             21
  1965. #define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
  1967. /*   SH_RTC3_INT_CONFIG_IDX                                             */
  1968. /*   Description:  Targeted McKinley interrupt vector                   */
  1969. #define SH_RTC3_INT_CONFIG_IDX_SHFT              52
  1970. #define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
  1972. /* ==================================================================== */
  1973. /*                    Register "SH_RTC3_INT_ENABLE"                     */
  1974. /*                SHub RTC 3 Interrupt Enable Registers                 */
  1975. /* ==================================================================== */
  1977. #define SH_RTC3_INT_ENABLE                       0x0000000110001700
  1978. #define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
  1979. #define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
  1981. /*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
  1982. /*   Description:  Enable RTC 3 Interrupt                               */
  1983. #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
  1984. #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
  1986. /* ==================================================================== */
  1987. /*                     Register "SH_EVENT_OCCURRED"                     */
  1988. /*                    SHub Interrupt Event Occurred                     */
  1989. /* ==================================================================== */
  1991. #define SH_EVENT_OCCURRED                        0x0000000110010000
  1992. #define SH_EVENT_OCCURRED_MASK                   0x000000007fffffff
  1993. #define SH_EVENT_OCCURRED_INIT                   0x0000000000000000
  1995. /*   SH_EVENT_OCCURRED_PI_HW_INT                                        */
  1996. /*   Description:  Pending PI Hardware interrupt                        */
  1997. #define SH_EVENT_OCCURRED_PI_HW_INT_SHFT         0
  1998. #define SH_EVENT_OCCURRED_PI_HW_INT_MASK         0x0000000000000001
  2000. /*   SH_EVENT_OCCURRED_MD_HW_INT                                        */
  2001. /*   Description:  Pending MD Hardware interrupt                        */
  2002. #define SH_EVENT_OCCURRED_MD_HW_INT_SHFT         1
  2003. #define SH_EVENT_OCCURRED_MD_HW_INT_MASK         0x0000000000000002
  2005. /*   SH_EVENT_OCCURRED_XN_HW_INT                                        */
  2006. /*   Description:  Pending XN Hardware interrupt                        */
  2007. #define SH_EVENT_OCCURRED_XN_HW_INT_SHFT         2
  2008. #define SH_EVENT_OCCURRED_XN_HW_INT_MASK         0x0000000000000004
  2010. /*   SH_EVENT_OCCURRED_LB_HW_INT                                        */
  2011. /*   Description:  Pending LB Hardware interrupt                        */
  2012. #define SH_EVENT_OCCURRED_LB_HW_INT_SHFT         3
  2013. #define SH_EVENT_OCCURRED_LB_HW_INT_MASK         0x0000000000000008
  2015. /*   SH_EVENT_OCCURRED_II_HW_INT                                        */
  2016. /*   Description:  Pending II wrapper Hardware interrupt                */
  2017. #define SH_EVENT_OCCURRED_II_HW_INT_SHFT         4
  2018. #define SH_EVENT_OCCURRED_II_HW_INT_MASK         0x0000000000000010
  2020. /*   SH_EVENT_OCCURRED_PI_CE_INT                                        */
  2021. /*   Description:  Pending PI Correctable Error Interrupt               */
  2022. #define SH_EVENT_OCCURRED_PI_CE_INT_SHFT         5
  2023. #define SH_EVENT_OCCURRED_PI_CE_INT_MASK         0x0000000000000020
  2025. /*   SH_EVENT_OCCURRED_MD_CE_INT                                        */
  2026. /*   Description:  Pending MD Correctable Error Interrupt               */
  2027. #define SH_EVENT_OCCURRED_MD_CE_INT_SHFT         6
  2028. #define SH_EVENT_OCCURRED_MD_CE_INT_MASK         0x0000000000000040
  2030. /*   SH_EVENT_OCCURRED_XN_CE_INT                                        */
  2031. /*   Description:  Pending XN Correctable Error Interrupt               */
  2032. #define SH_EVENT_OCCURRED_XN_CE_INT_SHFT         7
  2033. #define SH_EVENT_OCCURRED_XN_CE_INT_MASK         0x0000000000000080
  2035. /*   SH_EVENT_OCCURRED_PI_UCE_INT                                       */
  2036. /*   Description:  Pending PI Correctable Error Interrupt               */
  2037. #define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT        8
  2038. #define SH_EVENT_OCCURRED_PI_UCE_INT_MASK        0x0000000000000100
  2040. /*   SH_EVENT_OCCURRED_MD_UCE_INT                                       */
  2041. /*   Description:  Pending MD Correctable Error Interrupt               */
  2042. #define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT        9
  2043. #define SH_EVENT_OCCURRED_MD_UCE_INT_MASK        0x0000000000000200
  2045. /*   SH_EVENT_OCCURRED_XN_UCE_INT                                       */
  2046. /*   Description:  Pending XN Correctable Error Interrupt               */
  2047. #define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT        10
  2048. #define SH_EVENT_OCCURRED_XN_UCE_INT_MASK        0x0000000000000400
  2050. /*   SH_EVENT_OCCURRED_PROC0_ADV_INT                                    */
  2051. /*   Description:  Pending Processor 0 Advisory Interrupt               */
  2052. #define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT     11
  2053. #define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK     0x0000000000000800
  2055. /*   SH_EVENT_OCCURRED_PROC1_ADV_INT                                    */
  2056. /*   Description:  Pending Processor 1 Advisory Interrupt               */
  2057. #define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT     12
  2058. #define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK     0x0000000000001000
  2060. /*   SH_EVENT_OCCURRED_PROC2_ADV_INT                                    */
  2061. /*   Description:  Pending Processor 2 Advisory Interrupt               */
  2062. #define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT     13
  2063. #define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK     0x0000000000002000
  2065. /*   SH_EVENT_OCCURRED_PROC3_ADV_INT                                    */
  2066. /*   Description:  Pending Processor 3 Advisory Interrupt               */
  2067. #define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT     14
  2068. #define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK     0x0000000000004000
  2070. /*   SH_EVENT_OCCURRED_PROC0_ERR_INT                                    */
  2071. /*   Description:  Pending Processor 0 Error Interrupt                  */
  2072. #define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT     15
  2073. #define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK     0x0000000000008000
  2075. /*   SH_EVENT_OCCURRED_PROC1_ERR_INT                                    */
  2076. /*   Description:  Pending Processor 1 Error Interrupt                  */
  2077. #define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT     16
  2078. #define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK     0x0000000000010000
  2080. /*   SH_EVENT_OCCURRED_PROC2_ERR_INT                                    */
  2081. /*   Description:  Pending Processor 2 Error Interrupt                  */
  2082. #define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT     17
  2083. #define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK     0x0000000000020000
  2085. /*   SH_EVENT_OCCURRED_PROC3_ERR_INT                                    */
  2086. /*   Description:  Pending Processor 3 Error Interrupt                  */
  2087. #define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT     18
  2088. #define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK     0x0000000000040000
  2090. /*   SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT                              */
  2091. /*   Description:  Pending System Shutdown Interrupt                    */
  2092. #define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19
  2093. #define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
  2095. /*   SH_EVENT_OCCURRED_UART_INT                                         */
  2096. /*   Description:  Pending Junk Bus UART Interrupt                      */
  2097. #define SH_EVENT_OCCURRED_UART_INT_SHFT          20
  2098. #define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
  2100. /*   SH_EVENT_OCCURRED_L1_NMI_INT                                       */
  2101. /*   Description:  Pending L1 Controller NMI Interrupt                  */
  2102. #define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT        21
  2103. #define SH_EVENT_OCCURRED_L1_NMI_INT_MASK        0x0000000000200000
  2105. /*   SH_EVENT_OCCURRED_STOP_CLOCK                                       */
  2106. /*   Description:  Pending Stop Clock Interrupt                         */
  2107. #define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT        22
  2108. #define SH_EVENT_OCCURRED_STOP_CLOCK_MASK        0x0000000000400000
  2110. /*   SH_EVENT_OCCURRED_RTC0_INT                                         */
  2111. /*   Description:  Pending RTC 0 Interrupt                              */
  2112. #define SH_EVENT_OCCURRED_RTC0_INT_SHFT          23
  2113. #define SH_EVENT_OCCURRED_RTC0_INT_MASK          0x0000000000800000
  2115. /*   SH_EVENT_OCCURRED_RTC1_INT                                         */
  2116. /*   Description:  Pending RTC 1 Interrupt                              */
  2117. #define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
  2118. #define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
  2120. /*   SH_EVENT_OCCURRED_RTC2_INT                                         */
  2121. /*   Description:  Pending RTC 2 Interrupt                              */
  2122. #define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
  2123. #define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
  2125. /*   SH_EVENT_OCCURRED_RTC3_INT                                         */
  2126. /*   Description:  Pending RTC 3 Interrupt                              */
  2127. #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
  2128. #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
  2130. /*   SH_EVENT_OCCURRED_PROFILE_INT                                      */
  2131. /*   Description:  Pending Profile Interrupt                            */
  2132. #define SH_EVENT_OCCURRED_PROFILE_INT_SHFT       27
  2133. #define SH_EVENT_OCCURRED_PROFILE_INT_MASK       0x0000000008000000
  2135. /*   SH_EVENT_OCCURRED_IPI_INT                                          */
  2136. /*   Description:  Pending IPI Interrupt                                */
  2137. #define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
  2138. #define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
  2140. /*   SH_EVENT_OCCURRED_II_INT0                                          */
  2141. /*   Description:  Pending II 0 Interrupt                               */
  2142. #define SH_EVENT_OCCURRED_II_INT0_SHFT           29
  2143. #define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
  2145. /*   SH_EVENT_OCCURRED_II_INT1                                          */
  2146. /*   Description:  Pending II 1 Interrupt                               */
  2147. #define SH_EVENT_OCCURRED_II_INT1_SHFT           30
  2148. #define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
  2150. /* ==================================================================== */
  2151. /*                  Register "SH_EVENT_OCCURRED_ALIAS"                  */
  2152. /*                 SHub Interrupt Event Occurred Alias                  */
  2153. /* ==================================================================== */
  2155. #define SH_EVENT_OCCURRED_ALIAS                  0x0000000110010008
  2157. /* ==================================================================== */
  2158. /*                     Register "SH_EVENT_OVERFLOW"                     */
  2159. /*                SHub Interrupt Event Occurred Overflow                */
  2160. /* ==================================================================== */
  2162. #define SH_EVENT_OVERFLOW                        0x0000000110010080
  2163. #define SH_EVENT_OVERFLOW_MASK                   0x000000000fffffff
  2164. #define SH_EVENT_OVERFLOW_INIT                   0x0000000000000000
  2166. /*   SH_EVENT_OVERFLOW_PI_HW_INT                                        */
  2167. /*   Description:  Pending PI Hardware interrupt                        */
  2168. #define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT         0
  2169. #define SH_EVENT_OVERFLOW_PI_HW_INT_MASK         0x0000000000000001
  2171. /*   SH_EVENT_OVERFLOW_MD_HW_INT                                        */
  2172. /*   Description:  Pending MD Hardware interrupt                        */
  2173. #define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT         1
  2174. #define SH_EVENT_OVERFLOW_MD_HW_INT_MASK         0x0000000000000002
  2176. /*   SH_EVENT_OVERFLOW_XN_HW_INT                                        */
  2177. /*   Description:  Pending XN Hardware interrupt                        */
  2178. #define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT         2
  2179. #define SH_EVENT_OVERFLOW_XN_HW_INT_MASK         0x0000000000000004
  2181. /*   SH_EVENT_OVERFLOW_LB_HW_INT                                        */
  2182. /*   Description:  Pending LB Hardware interrupt                        */
  2183. #define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT         3
  2184. #define SH_EVENT_OVERFLOW_LB_HW_INT_MASK         0x0000000000000008
  2186. /*   SH_EVENT_OVERFLOW_II_HW_INT                                        */
  2187. /*   Description:  Pending II wrapper Hardware interrupt                */
  2188. #define SH_EVENT_OVERFLOW_II_HW_INT_SHFT         4
  2189. #define SH_EVENT_OVERFLOW_II_HW_INT_MASK         0x0000000000000010
  2191. /*   SH_EVENT_OVERFLOW_PI_CE_INT                                        */
  2192. /*   Description:  Pending PI Correctable Error Interrupt               */
  2193. #define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT         5
  2194. #define SH_EVENT_OVERFLOW_PI_CE_INT_MASK         0x0000000000000020
  2196. /*   SH_EVENT_OVERFLOW_MD_CE_INT                                        */
  2197. /*   Description:  Pending MD Correctable Error Interrupt               */
  2198. #define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT         6
  2199. #define SH_EVENT_OVERFLOW_MD_CE_INT_MASK         0x0000000000000040
  2201. /*   SH_EVENT_OVERFLOW_XN_CE_INT                                        */
  2202. /*   Description:  Pending XN Correctable Error Interrupt               */
  2203. #define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT         7
  2204. #define SH_EVENT_OVERFLOW_XN_CE_INT_MASK         0x0000000000000080
  2206. /*   SH_EVENT_OVERFLOW_PI_UCE_INT                                       */
  2207. /*   Description:  Pending PI Correctable Error Interrupt               */
  2208. #define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT        8
  2209. #define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK        0x0000000000000100
  2211. /*   SH_EVENT_OVERFLOW_MD_UCE_INT                                       */
  2212. /*   Description:  Pending MD Correctable Error Interrupt               */
  2213. #define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT        9
  2214. #define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK        0x0000000000000200
  2216. /*   SH_EVENT_OVERFLOW_XN_UCE_INT                                       */
  2217. /*   Description:  Pending XN Correctable Error Interrupt               */
  2218. #define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT        10
  2219. #define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK        0x0000000000000400
  2221. /*   SH_EVENT_OVERFLOW_PROC0_ADV_INT                                    */
  2222. /*   Description:  Pending Processor 0 Advisory Interrupt               */
  2223. #define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT     11
  2224. #define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK     0x0000000000000800
  2226. /*   SH_EVENT_OVERFLOW_PROC1_ADV_INT                                    */
  2227. /*   Description:  Pending Processor 1 Advisory Interrupt               */
  2228. #define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT     12
  2229. #define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK     0x0000000000001000
  2231. /*   SH_EVENT_OVERFLOW_PROC2_ADV_INT                                    */
  2232. /*   Description:  Pending Processor 2 Advisory Interrupt               */
  2233. #define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT     13
  2234. #define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK     0x0000000000002000
  2236. /*   SH_EVENT_OVERFLOW_PROC3_ADV_INT                                    */
  2237. /*   Description:  Pending Processor 3 Advisory Interrupt               */
  2238. #define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT     14
  2239. #define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK     0x0000000000004000
  2241. /*   SH_EVENT_OVERFLOW_PROC0_ERR_INT                                    */
  2242. /*   Description:  Pending Processor 0 Error Interrupt                  */
  2243. #define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT     15
  2244. #define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK     0x0000000000008000
  2246. /*   SH_EVENT_OVERFLOW_PROC1_ERR_INT                                    */
  2247. /*   Description:  Pending Processor 1 Error Interrupt                  */
  2248. #define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT     16
  2249. #define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK     0x0000000000010000
  2251. /*   SH_EVENT_OVERFLOW_PROC2_ERR_INT                                    */
  2252. /*   Description:  Pending Processor 2 Error Interrupt                  */
  2253. #define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT     17
  2254. #define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK     0x0000000000020000
  2256. /*   SH_EVENT_OVERFLOW_PROC3_ERR_INT                                    */
  2257. /*   Description:  Pending Processor 3 Error Interrupt                  */