Linux/Unix编程

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Unix_Linux

shubio.h：源码内容

} ii_iprte2a_fld_s;
} ii_iprte2a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte3a_u {
shubreg_t ii_iprte3a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprte3a_fld_s;
} ii_iprte3a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte4a_u {
shubreg_t ii_iprte4a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprte4a_fld_s;
} ii_iprte4a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte5a_u {
shubreg_t ii_iprte5a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprte5a_fld_s;
} ii_iprte5a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte6a_u {
shubreg_t ii_iprte6a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprte6a_fld_s;
} ii_iprte6a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte7a_u {
shubreg_t ii_iprte7a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprtea7_fld_s;
} ii_iprte7a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte0b_u {
shubreg_t ii_iprte0b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte0b_fld_s;
} ii_iprte0b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte1b_u {
shubreg_t ii_iprte1b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte1b_fld_s;
} ii_iprte1b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte2b_u {
shubreg_t ii_iprte2b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte2b_fld_s;
} ii_iprte2b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte3b_u {
shubreg_t ii_iprte3b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte3b_fld_s;
} ii_iprte3b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte4b_u {
shubreg_t ii_iprte4b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte4b_fld_s;
} ii_iprte4b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte5b_u {
shubreg_t ii_iprte5b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte5b_fld_s;
} ii_iprte5b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte6b_u {
shubreg_t ii_iprte6b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte6b_fld_s;
} ii_iprte6b_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte7b_u {
shubreg_t ii_iprte7b_regval;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_address : 47;
shubreg_t i_init : 3;
shubreg_t i_source : 11;
} ii_iprte7b_fld_s;
} ii_iprte7b_u_t;
/************************************************************************
* *
* Description: SHub II contains a feature which did not exist in *
* the Hub which automatically cleans up after a Read Response *
* timeout, including deallocation of the IPRTE and recovery of IBuf *
* space. The inclusion of this register in SHub is for backward *
* compatibility *
* A write to this register causes an entry from the table of *
* outstanding PIO Read Requests to be freed and returned to the *
* stack of free entries. This register is used in handling the *
* timeout errors that result in a PIO Reply never returning from *
* Crosstalk. *
* Note that this register does not affect the contents of the IPRTE *
* registers. The Valid bits in those registers have to be *
* specifically turned off by software. *
* *
************************************************************************/
typedef union ii_ipdr_u {
shubreg_t ii_ipdr_regval;
struct {
shubreg_t i_te : 3;
shubreg_t i_rsvd_1 : 1;
shubreg_t i_pnd : 1;
shubreg_t i_init_rpcnt : 1;
shubreg_t i_rsvd : 58;
} ii_ipdr_fld_s;
} ii_ipdr_u_t;
/************************************************************************
* *
* A write to this register causes a CRB entry to be returned to the *
* queue of free CRBs. The entry should have previously been cleared *
* (mark bit) via backdoor access to the pertinent CRB entry. This *
* register is used in the last step of handling the errors that are *
* captured and marked in CRB entries. Briefly: 1) first error for *
* DMA write from a particular device, and first error for a *
* particular BTE stream, lead to a marked CRB entry, and processor *
* interrupt, 2) software reads the error information captured in the *
* CRB entry, and presumably takes some corrective action, 3) *
* software clears the mark bit, and finally 4) software writes to *
* the ICDR register to return the CRB entry to the list of free CRB *
* entries. *
* *
************************************************************************/
typedef union ii_icdr_u {
shubreg_t ii_icdr_regval;
struct {
shubreg_t i_crb_num : 4;
shubreg_t i_pnd : 1;
shubreg_t i_rsvd : 59;
} ii_icdr_fld_s;
} ii_icdr_u_t;
/************************************************************************
* *
* This register provides debug access to two FIFOs inside of II. *
* Both IOQ_MAX* fields of this register contain the instantaneous *
* depth (in units of the number of available entries) of the *
* associated IOQ FIFO. A read of this register will return the *
* number of free entries on each FIFO at the time of the read. So *
* when a FIFO is idle, the associated field contains the maximum *
* depth of the FIFO. This register is writable for debug reasons *
* and is intended to be written with the maximum desired FIFO depth *
* while the FIFO is idle. Software must assure that II is idle when *
* this register is written. If there are any active entries in any *
* of these FIFOs when this register is written, the results are *
* undefined. *
* *
************************************************************************/
typedef union ii_ifdr_u {
shubreg_t ii_ifdr_regval;
struct {
shubreg_t i_ioq_max_rq : 7;
shubreg_t i_set_ioq_rq : 1;
shubreg_t i_ioq_max_rp : 7;
shubreg_t i_set_ioq_rp : 1;
shubreg_t i_rsvd : 48;
} ii_ifdr_fld_s;
} ii_ifdr_u_t;
/************************************************************************
* *
* This register allows the II to become sluggish in removing *
* messages from its inbound queue (IIQ). This will cause messages to *
* back up in either virtual channel. Disabling the "molasses" mode *
* subsequently allows the II to be tested under stress. In the *
* sluggish ("Molasses") mode, the localized effects of congestion *
* can be observed. *
* *
************************************************************************/
typedef union ii_iiap_u {
shubreg_t ii_iiap_regval;
struct {
shubreg_t i_rq_mls : 6;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_rp_mls : 6;
shubreg_t i_rsvd : 50;
} ii_iiap_fld_s;
} ii_iiap_u_t;
/************************************************************************
* *
* This register allows several parameters of CRB operation to be *
* set. Note that writing to this register can have catastrophic side *
* effects, if the CRB is not quiescent, i.e. if the CRB is *
* processing protocol messages when the write occurs. *
* *
************************************************************************/
typedef union ii_icmr_u {
shubreg_t ii_icmr_regval;
struct {
shubreg_t i_sp_msg : 1;
shubreg_t i_rd_hdr : 1;
shubreg_t i_rsvd_4 : 2;
shubreg_t i_c_cnt : 4;
shubreg_t i_rsvd_3 : 4;
shubreg_t i_clr_rqpd : 1;
shubreg_t i_clr_rppd : 1;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_fc_cnt : 4;
shubreg_t i_crb_vld : 15;
shubreg_t i_crb_mark : 15;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_precise : 1;
shubreg_t i_rsvd : 11;
} ii_icmr_fld_s;
} ii_icmr_u_t;
/************************************************************************
* *
* This register allows control of the table portion of the CRB *
* logic via software. Control operations from this register have *
* priority over all incoming Crosstalk or BTE requests. *
* *
************************************************************************/
typedef union ii_iccr_u {
shubreg_t ii_iccr_regval;
struct {
shubreg_t i_crb_num : 4;
shubreg_t i_rsvd_1 : 4;
shubreg_t i_cmd : 8;
shubreg_t i_pending : 1;
shubreg_t i_rsvd : 47;
} ii_iccr_fld_s;
} ii_iccr_u_t;
/************************************************************************
* *
* This register allows the maximum timeout value to be programmed. *
* *
************************************************************************/
typedef union ii_icto_u {
shubreg_t ii_icto_regval;
struct {
shubreg_t i_timeout : 8;
shubreg_t i_rsvd : 56;
} ii_icto_fld_s;
} ii_icto_u_t;
/************************************************************************
* *
* This register allows the timeout prescalar to be programmed. An *
* internal counter is associated with this register. When the *
* internal counter reaches the value of the PRESCALE field, the *
* timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
* field). The internal counter resets to zero, and then continues *
* counting. *
* *
************************************************************************/
typedef union ii_ictp_u {
shubreg_t ii_ictp_regval;
struct {
shubreg_t i_prescale : 24;
shubreg_t i_rsvd : 40;
} ii_ictp_fld_s;
} ii_ictp_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
* used for Crosstalk operations (both cacheline and partial *
* operations) or BTE/IO. Because the CRB entries are very wide, five *
* registers (_A to _E) are required to read and write each entry. *
* The CRB Entry registers can be conceptualized as rows and columns *
* (illustrated in the table above). Each row contains the 4 *
* registers required for a single CRB Entry. The first doubleword *
* (column) for each entry is labeled A, and the second doubleword *
* (higher address) is labeled B, the third doubleword is labeled C, *
* the fourth doubleword is labeled D and the fifth doubleword is *
* labeled E. All CRB entries have their addresses on a quarter *
* cacheline aligned boundary. *
* Upon reset, only the following fields are initialized: valid *
* (VLD), priority count, timeout, timeout valid, and context valid. *
* All other bits should be cleared by software before use (after *
* recovering any potential error state from before the reset). *
* The following four tables summarize the format for the four *
* registers that are used for each ICRB# Entry. *
* *
************************************************************************/
typedef union ii_icrb0_a_u {
shubreg_t ii_icrb0_a_regval;
struct {
shubreg_t ia_iow : 1;
shubreg_t ia_vld : 1;
shubreg_t ia_addr : 47;
shubreg_t ia_tnum : 5;
shubreg_t ia_sidn : 4;
shubreg_t ia_rsvd : 6;
} ii_icrb0_a_fld_s;
} ii_icrb0_a_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
* used for Crosstalk operations (both cacheline and partial *
* operations) or BTE/IO. Because the CRB entries are very wide, five *
* registers (_A to _E) are required to read and write each entry. *
* *
************************************************************************/
typedef union ii_icrb0_b_u {
shubreg_t ii_icrb0_b_regval;
struct {
shubreg_t ib_xt_err : 1;
shubreg_t ib_mark : 1;
shubreg_t ib_ln_uce : 1;
shubreg_t ib_errcode : 3;
shubreg_t ib_error : 1;
shubreg_t ib_stall__bte_1 : 1;
shubreg_t ib_stall__bte_0 : 1;
shubreg_t ib_stall__intr : 1;
shubreg_t ib_stall_ib : 1;
shubreg_t ib_intvn : 1;
shubreg_t ib_wb : 1;
shubreg_t ib_hold : 1;
shubreg_t ib_ack : 1;
shubreg_t ib_resp : 1;
shubreg_t ib_ack_cnt : 11;
shubreg_t ib_rsvd : 7;
shubreg_t ib_exc : 5;
shubreg_t ib_init : 3;
shubreg_t ib_imsg : 8;
shubreg_t ib_imsgtype : 2;
shubreg_t ib_use_old : 1;
shubreg_t ib_rsvd_1 : 11;
} ii_icrb0_b_fld_s;
} ii_icrb0_b_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
* used for Crosstalk operations (both cacheline and partial *
* operations) or BTE/IO. Because the CRB entries are very wide, five *
* registers (_A to _E) are required to read and write each entry. *
* *
************************************************************************/
typedef union ii_icrb0_c_u {
shubreg_t ii_icrb0_c_regval;
struct {
shubreg_t ic_source : 15;
shubreg_t ic_size : 2;
shubreg_t ic_ct : 1;
shubreg_t ic_bte_num : 1;
shubreg_t ic_gbr : 1;
shubreg_t ic_resprqd : 1;
shubreg_t ic_bo : 1;
shubreg_t ic_suppl : 15;
shubreg_t ic_rsvd : 27;
} ii_icrb0_c_fld_s;
} ii_icrb0_c_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
* used for Crosstalk operations (both cacheline and partial *
* operations) or BTE/IO. Because the CRB entries are very wide, five *
* registers (_A to _E) are required to read and write each entry. *
* *
************************************************************************/
typedef union ii_icrb0_d_u {
shubreg_t ii_icrb0_d_regval;
struct {
shubreg_t id_pa_be : 43;
shubreg_t id_bte_op : 1;
shubreg_t id_pr_psc : 4;
shubreg_t id_pr_cnt : 4;
shubreg_t id_sleep : 1;
shubreg_t id_rsvd : 11;
} ii_icrb0_d_fld_s;
} ii_icrb0_d_u_t;
/************************************************************************
* *
* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
* used for Crosstalk operations (both cacheline and partial *
* operations) or BTE/IO. Because the CRB entries are very wide, five *
* registers (_A to _E) are required to read and write each entry. *
* *
************************************************************************/
typedef union ii_icrb0_e_u {
shubreg_t ii_icrb0_e_regval;
struct {
shubreg_t ie_timeout : 8;
shubreg_t ie_context : 15;
shubreg_t ie_rsvd : 1;
shubreg_t ie_tvld : 1;
shubreg_t ie_cvld : 1;
shubreg_t ie_rsvd_0 : 38;
} ii_icrb0_e_fld_s;
} ii_icrb0_e_u_t;
/************************************************************************
* *
* This register contains the lower 64 bits of the header of the *
* spurious message captured by II. Valid when the SP_MSG bit in ICMR *
* register is set. *
* *
************************************************************************/
typedef union ii_icsml_u {
shubreg_t ii_icsml_regval;
struct {
shubreg_t i_tt_addr : 47;
shubreg_t i_newsuppl_ex : 14;
shubreg_t i_reserved : 2;
shubreg_t i_overflow : 1;
} ii_icsml_fld_s;
} ii_icsml_u_t;
/************************************************************************
* *
* This register contains the middle 64 bits of the header of the *
* spurious message captured by II. Valid when the SP_MSG bit in ICMR *
* register is set. *
* *
************************************************************************/
typedef union ii_icsmm_u {
shubreg_t ii_icsmm_regval;
struct {
shubreg_t i_tt_ack_cnt : 11;
shubreg_t i_reserved : 53;
} ii_icsmm_fld_s;
} ii_icsmm_u_t;
/************************************************************************
* *
* This register contains the microscopic state, all the inputs to *
* the protocol table, captured with the spurious message. Valid when *
* the SP_MSG bit in the ICMR register is set. *
* *
************************************************************************/
typedef union ii_icsmh_u {
shubreg_t ii_icsmh_regval;
struct {
shubreg_t i_tt_vld : 1;
shubreg_t i_xerr : 1;
shubreg_t i_ft_cwact_o : 1;
shubreg_t i_ft_wact_o : 1;
shubreg_t i_ft_active_o : 1;
shubreg_t i_sync : 1;
shubreg_t i_mnusg : 1;
shubreg_t i_mnusz : 1;
shubreg_t i_plusz : 1;
shubreg_t i_plusg : 1;
shubreg_t i_tt_exc : 5;
shubreg_t i_tt_wb : 1;
shubreg_t i_tt_hold : 1;
shubreg_t i_tt_ack : 1;
shubreg_t i_tt_resp : 1;
shubreg_t i_tt_intvn : 1;
shubreg_t i_g_stall_bte1 : 1;
shubreg_t i_g_stall_bte0 : 1;
shubreg_t i_g_stall_il : 1;
shubreg_t i_g_stall_ib : 1;
shubreg_t i_tt_imsg : 8;
shubreg_t i_tt_imsgtype : 2;
shubreg_t i_tt_use_old : 1;
shubreg_t i_tt_respreqd : 1;
shubreg_t i_tt_bte_num : 1;
shubreg_t i_cbn : 1;
shubreg_t i_match : 1;
shubreg_t i_rpcnt_lt_34 : 1;
shubreg_t i_rpcnt_ge_34 : 1;
shubreg_t i_rpcnt_lt_18 : 1;
shubreg_t i_rpcnt_ge_18 : 1;
shubreg_t i_rpcnt_lt_2 : 1;
shubreg_t i_rpcnt_ge_2 : 1;
shubreg_t i_rqcnt_lt_18 : 1;
shubreg_t i_rqcnt_ge_18 : 1;
shubreg_t i_rqcnt_lt_2 : 1;
shubreg_t i_rqcnt_ge_2 : 1;
shubreg_t i_tt_device : 7;
shubreg_t i_tt_init : 3;
shubreg_t i_reserved : 5;
} ii_icsmh_fld_s;
} ii_icsmh_u_t;
/************************************************************************
* *
* The Shub DEBUG unit provides a 3-bit selection signal to the *
* II core and a 3-bit selection signal to the fsbclk domain in the II *
* wrapper. *
* *
************************************************************************/
typedef union ii_idbss_u {
shubreg_t ii_idbss_regval;
struct {
shubreg_t i_iioclk_core_submenu : 3;
shubreg_t i_rsvd : 5;
shubreg_t i_fsbclk_wrapper_submenu : 3;
shubreg_t i_rsvd_1 : 5;
shubreg_t i_iioclk_menu : 5;
shubreg_t i_rsvd_2 : 43;
} ii_idbss_fld_s;
} ii_idbss_u_t;
/************************************************************************
* *
* Description: This register is used to set up the length for a *
* transfer and then to monitor the progress of that transfer. This *
* register needs to be initialized before a transfer is started. A *
* legitimate write to this register will set the Busy bit, clear the *
* Error bit, and initialize the length to the value desired. *
* While the transfer is in progress, hardware will decrement the *
* length field with each successful block that is copied. Once the *
* transfer completes, hardware will clear the Busy bit. The length *
* field will also contain the number of cache lines left to be *
* transferred. *
* *
************************************************************************/
typedef union ii_ibls0_u {
shubreg_t ii_ibls0_regval;
struct {
shubreg_t i_length : 16;
shubreg_t i_error : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_busy : 1;
shubreg_t i_rsvd : 43;
} ii_ibls0_fld_s;
} ii_ibls0_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
* address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
* address as described in Section 1.3, Figure2 and Figure3. Since *
* the bottom 7 bits of the address are always taken to be zero, BTE *
* transfers are always cacheline-aligned. *
* *
************************************************************************/
typedef union ii_ibsa0_u {
shubreg_t ii_ibsa0_regval;
struct {
shubreg_t i_rsvd_1 : 7;
shubreg_t i_addr : 42;
shubreg_t i_rsvd : 15;
} ii_ibsa0_fld_s;
} ii_ibsa0_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
* address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
* address as described in Section 1.3, Figure2 and Figure3. Since *
* the bottom 7 bits of the address are always taken to be zero, BTE *
* transfers are always cacheline-aligned. *
* *
************************************************************************/
typedef union ii_ibda0_u {
shubreg_t ii_ibda0_regval;
struct {
shubreg_t i_rsvd_1 : 7;
shubreg_t i_addr : 42;
shubreg_t i_rsvd : 15;
} ii_ibda0_fld_s;
} ii_ibda0_u_t;
/************************************************************************
* *
* Writing to this register sets up the attributes of the transfer *
* and initiates the transfer operation. Reading this register has *
* the side effect of terminating any transfer in progress. Note: *
* stopping a transfer midstream could have an adverse impact on the *
* other BTE. If a BTE stream has to be stopped (due to error *
* handling for example), both BTE streams should be stopped and *
* their transfers discarded. *
* *
************************************************************************/
typedef union ii_ibct0_u {
shubreg_t ii_ibct0_regval;
struct {
shubreg_t i_zerofill : 1;
shubreg_t i_rsvd_2 : 3;
shubreg_t i_notify : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_poison : 1;
shubreg_t i_rsvd : 55;
} ii_ibct0_fld_s;
} ii_ibct0_u_t;
/************************************************************************
* *
* This register contains the address to which the WINV is sent. *
* This address has to be cache line aligned. *
* *
************************************************************************/
typedef union ii_ibna0_u {
shubreg_t ii_ibna0_regval;
struct {
shubreg_t i_rsvd_1 : 7;
shubreg_t i_addr : 42;
shubreg_t i_rsvd : 15;
} ii_ibna0_fld_s;
} ii_ibna0_u_t;
/************************************************************************
* *
* This register contains the programmable level as well as the node *
* ID and PI unit of the processor to which the interrupt will be *
* sent. *
* *
************************************************************************/
typedef union ii_ibia0_u {
shubreg_t ii_ibia0_regval;
struct {
shubreg_t i_rsvd_2 : 1;
shubreg_t i_node_id : 11;
shubreg_t i_rsvd_1 : 4;
shubreg_t i_level : 7;
shubreg_t i_rsvd : 41;
} ii_ibia0_fld_s;
} ii_ibia0_u_t;
/************************************************************************
* *
* Description: This register is used to set up the length for a *
* transfer and then to monitor the progress of that transfer. This *
* register needs to be initialized before a transfer is started. A *
* legitimate write to this register will set the Busy bit, clear the *
* Error bit, and initialize the length to the value desired. *
* While the transfer is in progress, hardware will decrement the *
* length field with each successful block that is copied. Once the *
* transfer completes, hardware will clear the Busy bit. The length *
* field will also contain the number of cache lines left to be *
* transferred. *
* *
************************************************************************/
typedef union ii_ibls1_u {
shubreg_t ii_ibls1_regval;
struct {
shubreg_t i_length : 16;
shubreg_t i_error : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_busy : 1;
shubreg_t i_rsvd : 43;
} ii_ibls1_fld_s;
} ii_ibls1_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
* address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
* address as described in Section 1.3, Figure2 and Figure3. Since *
* the bottom 7 bits of the address are always taken to be zero, BTE *
* transfers are always cacheline-aligned. *
* *
************************************************************************/
typedef union ii_ibsa1_u {
shubreg_t ii_ibsa1_regval;
struct {
shubreg_t i_rsvd_1 : 7;
shubreg_t i_addr : 33;
shubreg_t i_rsvd : 24;
} ii_ibsa1_fld_s;
} ii_ibsa1_u_t;
/************************************************************************
* *
* This register should be loaded before a transfer is started. The *
* address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
* address as described in Section 1.3, Figure2 and Figure3. Since *
* the bottom 7 bits of the address are always taken to be zero, BTE *
* transfers are always cacheline-aligned. *
* *
************************************************************************/
typedef union ii_ibda1_u {
shubreg_t ii_ibda1_regval;
struct {
shubreg_t i_rsvd_1 : 7;
shubreg_t i_addr : 33;
shubreg_t i_rsvd : 24;
} ii_ibda1_fld_s;
} ii_ibda1_u_t;
/************************************************************************
* *
* Writing to this register sets up the attributes of the transfer *
* and initiates the transfer operation. Reading this register has *
* the side effect of terminating any transfer in progress. Note: *
* stopping a transfer midstream could have an adverse impact on the *
* other BTE. If a BTE stream has to be stopped (due to error *
* handling for example), both BTE streams should be stopped and *
* their transfers discarded. *
* *
************************************************************************/
typedef union ii_ibct1_u {
shubreg_t ii_ibct1_regval;
struct {
shubreg_t i_zerofill : 1;
shubreg_t i_rsvd_2 : 3;
shubreg_t i_notify : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_poison : 1;
shubreg_t i_rsvd : 55;
} ii_ibct1_fld_s;
} ii_ibct1_u_t;
/************************************************************************
* *
* This register contains the address to which the WINV is sent. *
* This address has to be cache line aligned. *
* *
************************************************************************/
typedef union ii_ibna1_u {
shubreg_t ii_ibna1_regval;
struct {
shubreg_t i_rsvd_1 : 7;
shubreg_t i_addr : 33;
shubreg_t i_rsvd : 24;
} ii_ibna1_fld_s;
} ii_ibna1_u_t;
/************************************************************************
* *
* This register contains the programmable level as well as the node *
* ID and PI unit of the processor to which the interrupt will be *
* sent. *
* *
************************************************************************/
typedef union ii_ibia1_u {
shubreg_t ii_ibia1_regval;
struct {
shubreg_t i_pi_id : 1;
shubreg_t i_node_id : 8;
shubreg_t i_rsvd_1 : 7;
shubreg_t i_level : 7;
shubreg_t i_rsvd : 41;
} ii_ibia1_fld_s;
} ii_ibia1_u_t;
/************************************************************************
* *
* This register defines the resources that feed information into *
* the two performance counters located in the IO Performance *
* Profiling Register. There are 17 different quantities that can be *
* measured. Given these 17 different options, the two performance *
* counters have 15 of them in common; menu selections 0 through 0xE *
* are identical for each performance counter. As for the other two *
* options, one is available from one performance counter and the *
* other is available from the other performance counter. Hence, the *
* II supports all 17*16=272 possible combinations of quantities to *
* measure. *
* *
************************************************************************/
typedef union ii_ipcr_u {
shubreg_t ii_ipcr_regval;
struct {
shubreg_t i_ippr0_c : 4;
shubreg_t i_ippr1_c : 4;
shubreg_t i_icct : 8;
shubreg_t i_rsvd : 48;
} ii_ipcr_fld_s;
} ii_ipcr_u_t;
/************************************************************************
* *
* *
* *
************************************************************************/
typedef union ii_ippr_u {
shubreg_t ii_ippr_regval;
struct {
shubreg_t i_ippr0 : 32;
shubreg_t i_ippr1 : 32;
} ii_ippr_fld_s;
} ii_ippr_u_t;
#endif /* __ASSEMBLY__ */
/**************************************************************************
* *
* The following defines which were not formed into structures are *
* probably indentical to another register, and the name of the *
* register is provided against each of these registers. This *
* information needs to be checked carefully *
* *
* IIO_ICRB1_A IIO_ICRB0_A *
* IIO_ICRB1_B IIO_ICRB0_B *
* IIO_ICRB1_C IIO_ICRB0_C *
* IIO_ICRB1_D IIO_ICRB0_D *
* IIO_ICRB1_E IIO_ICRB0_E *
* IIO_ICRB2_A IIO_ICRB0_A *
* IIO_ICRB2_B IIO_ICRB0_B *
* IIO_ICRB2_C IIO_ICRB0_C *
* IIO_ICRB2_D IIO_ICRB0_D *
* IIO_ICRB2_E IIO_ICRB0_E *
* IIO_ICRB3_A IIO_ICRB0_A *
* IIO_ICRB3_B IIO_ICRB0_B *
* IIO_ICRB3_C IIO_ICRB0_C *
* IIO_ICRB3_D IIO_ICRB0_D *
* IIO_ICRB3_E IIO_ICRB0_E *
* IIO_ICRB4_A IIO_ICRB0_A *
* IIO_ICRB4_B IIO_ICRB0_B *
* IIO_ICRB4_C IIO_ICRB0_C *
* IIO_ICRB4_D IIO_ICRB0_D *
* IIO_ICRB4_E IIO_ICRB0_E *
* IIO_ICRB5_A IIO_ICRB0_A *
* IIO_ICRB5_B IIO_ICRB0_B *
* IIO_ICRB5_C IIO_ICRB0_C *
* IIO_ICRB5_D IIO_ICRB0_D *
* IIO_ICRB5_E IIO_ICRB0_E *
* IIO_ICRB6_A IIO_ICRB0_A *
* IIO_ICRB6_B IIO_ICRB0_B *
* IIO_ICRB6_C IIO_ICRB0_C *
* IIO_ICRB6_D IIO_ICRB0_D *
* IIO_ICRB6_E IIO_ICRB0_E *
* IIO_ICRB7_A IIO_ICRB0_A *
* IIO_ICRB7_B IIO_ICRB0_B *
* IIO_ICRB7_C IIO_ICRB0_C *
* IIO_ICRB7_D IIO_ICRB0_D *
* IIO_ICRB7_E IIO_ICRB0_E *
* IIO_ICRB8_A IIO_ICRB0_A *
* IIO_ICRB8_B IIO_ICRB0_B *
* IIO_ICRB8_C IIO_ICRB0_C *
* IIO_ICRB8_D IIO_ICRB0_D *
* IIO_ICRB8_E IIO_ICRB0_E *
* IIO_ICRB9_A IIO_ICRB0_A *
* IIO_ICRB9_B IIO_ICRB0_B *
* IIO_ICRB9_C IIO_ICRB0_C *
* IIO_ICRB9_D IIO_ICRB0_D *
* IIO_ICRB9_E IIO_ICRB0_E *
* IIO_ICRBA_A IIO_ICRB0_A *
* IIO_ICRBA_B IIO_ICRB0_B *
* IIO_ICRBA_C IIO_ICRB0_C *
* IIO_ICRBA_D IIO_ICRB0_D *
* IIO_ICRBA_E IIO_ICRB0_E *
* IIO_ICRBB_A IIO_ICRB0_A *
* IIO_ICRBB_B IIO_ICRB0_B *
* IIO_ICRBB_C IIO_ICRB0_C *
* IIO_ICRBB_D IIO_ICRB0_D *
* IIO_ICRBB_E IIO_ICRB0_E *
* IIO_ICRBC_A IIO_ICRB0_A *
* IIO_ICRBC_B IIO_ICRB0_B *
* IIO_ICRBC_C IIO_ICRB0_C *
* IIO_ICRBC_D IIO_ICRB0_D *
* IIO_ICRBC_E IIO_ICRB0_E *
* IIO_ICRBD_A IIO_ICRB0_A *
* IIO_ICRBD_B IIO_ICRB0_B *
* IIO_ICRBD_C IIO_ICRB0_C *
* IIO_ICRBD_D IIO_ICRB0_D *
* IIO_ICRBD_E IIO_ICRB0_E *
* IIO_ICRBE_A IIO_ICRB0_A *
* IIO_ICRBE_B IIO_ICRB0_B *
* IIO_ICRBE_C IIO_ICRB0_C *
* IIO_ICRBE_D IIO_ICRB0_D *
* IIO_ICRBE_E IIO_ICRB0_E *
* *
**************************************************************************/
/*
* Slightly friendlier names for some common registers.
*/
#define IIO_WIDGET IIO_WID /* Widget identification */
#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
#define IIO_LLP_LOG IIO_ILLR /* LLP log */
#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
#define IIO_IGFX_0 IIO_IGFX0
#define IIO_IGFX_1 IIO_IGFX1
#define IIO_IBCT_0 IIO_IBCT0
#define IIO_IBCT_1 IIO_IBCT1
#define IIO_IBLS_0 IIO_IBLS0
#define IIO_IBLS_1 IIO_IBLS1
#define IIO_IBSA_0 IIO_IBSA0
#define IIO_IBSA_1 IIO_IBSA1
#define IIO_IBDA_0 IIO_IBDA0
#define IIO_IBDA_1 IIO_IBDA1
#define IIO_IBNA_0 IIO_IBNA0
#define IIO_IBNA_1 IIO_IBNA1
#define IIO_IBIA_0 IIO_IBIA0
#define IIO_IBIA_1 IIO_IBIA1
#define IIO_IOPRB_0 IIO_IPRB0
#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
#define IIO_NUM_IPRBS (9)
#define IIO_LLP_CSR_IS_UP 0x00002000
#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
#define IIO_LLP_CSR_LLP_STAT_SHFT 12
#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
/* key to IIO_PROTECT_OVRRD */
#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
/* BTE register names */
#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
/* BTE register offsets from base */
#define BTEOFF_STAT 0
#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
/* names used in shub diags */
#define IIO_BASE_BTE0 IIO_IBLS_0
#define IIO_BASE_BTE1 IIO_IBLS_1
/*
* Macro which takes the widget number, and returns the
* IO PRB address of that widget.
* value _x is expected to be a widget number in the range
* 0, 8 - 0xF
*/
#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ?
(_x) :
(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
/* GFX Flow Control Node/Widget Register */
#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
#define IIO_IGFX_W_NUM_SHIFT 0
#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
#define IIO_IGFX_PI_NUM_SHIFT 4
#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
#define IIO_IGFX_N_NUM_SHIFT 5
#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
#define IIO_IGFX_P_NUM_SHIFT 16
#define IIO_IGFX_INIT(widget, pi, node, cpu) (
(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |
(((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|
(((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |
(((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
/* Scratch registers (all bits available) */
#define IIO_SCRATCH_REG0 IIO_ISCR0
#define IIO_SCRATCH_REG1 IIO_ISCR1
#define IIO_SCRATCH_MASK 0xffffffffffffffff
#define IIO_SCRATCH_BIT0_0 0x0000000000000001
#define IIO_SCRATCH_BIT0_1 0x0000000000000002
#define IIO_SCRATCH_BIT0_2 0x0000000000000004
#define IIO_SCRATCH_BIT0_3 0x0000000000000008
#define IIO_SCRATCH_BIT0_4 0x0000000000000010
#define IIO_SCRATCH_BIT0_5 0x0000000000000020
#define IIO_SCRATCH_BIT0_6 0x0000000000000040
#define IIO_SCRATCH_BIT0_7 0x0000000000000080
#define IIO_SCRATCH_BIT0_8 0x0000000000000100
#define IIO_SCRATCH_BIT0_9 0x0000000000000200
#define IIO_SCRATCH_BIT0_A 0x0000000000000400
#define IIO_SCRATCH_BIT1_0 0x0000000000000001
#define IIO_SCRATCH_BIT1_1 0x0000000000000002
/* IO Translation Table Entries */
#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
/* Hw manuals number them 1..7! */
/*
* IIO_IMEM Register fields.
*/
#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */
#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */
#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */
/*
* As a permanent workaround for a bug in the PI side of the shub, we've
* redefined big window 7 as small window 0.
XXX does this still apply for SN1??
*/
#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
/*
* Use the top big window as a surrogate for the first small window
*/
#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
#define ILCSR_WARM_RESET 0x100
/*
* CRB manipulation macros
* The CRB macros are slightly complicated, since there are up to
* four registers associated with each CRB entry.
*/
#define IIO_NUM_CRBS 15 /* Number of CRBs */
#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
#define IIO_ICRB_OFFSET 8
#define IIO_ICRB_0 IIO_ICRB0_A
#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
/* XXX - This is now tuneable:
#define IIO_FIRST_PC_ENTRY 12
*/
#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))
#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
#define IIO_ICRB_E(_x) (IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)
#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
/*
* values for "ecode" field
*/
#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
* e.g. WINV to a Read only line. */
#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
/*
* Values for field imsgtype
*/
#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
/*
* values for field initiator.
*/
#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
/*
* Number of credits Hub widget has while sending req/response to
* xbow.
* Value of 3 is required by Xbow 1.1
* We may be able to increase this to 4 with Xbow 1.2.
*/
#define HUBII_XBOW_CREDIT 3
#define HUBII_XBOW_REV2_CREDIT 4
/*
* Number of credits that xtalk devices should use when communicating
* with a SHub (depth of SHub's queue).
*/
#define HUB_CREDIT 4
/*
* Some IIO_PRB fields
*/
#define IIO_PRB_MULTI_ERR (1LL << 63)
#define IIO_PRB_SPUR_RD (1LL << 51)
#define IIO_PRB_SPUR_WR (1LL << 50)
#define IIO_PRB_RD_TO (1LL << 49)
#define IIO_PRB_ERROR (1LL << 48)
/*************************************************************************
Some of the IIO field masks and shifts are defined here.
This is in order to maintain compatibility in SN0 and SN1 code
**************************************************************************/
/*
* ICMR register fields
* (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
* present in SHub)
*/
#define IIO_ICMR_CRB_VLD_SHFT 20
#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
#define IIO_ICMR_FC_CNT_SHFT 16
#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
#define IIO_ICMR_C_CNT_SHFT 4
#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
#define IIO_ICMR_PRECISE (1UL << 52)
#define IIO_ICMR_CLR_RPPD (1UL << 13)
#define IIO_ICMR_CLR_RQPD (1UL << 12)
/*
* IIO PIO Deallocation register field masks : (IIO_IPDR)
XXX present but not needed in bedrock? See the manual.
*/
#define IIO_IPDR_PND (1 << 4)
/*
* IIO CRB deallocation register field masks: (IIO_ICDR)
*/
#define IIO_ICDR_PND (1 << 4)
/*
* IO BTE Length/Status (IIO_IBLS) register bit field definitions
*/
#define IBLS_BUSY (0x1 << 20)
#define IBLS_ERROR_SHFT 16
#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT)
#define IBLS_LENGTH_MASK 0xffff
/*
* IO BTE Control/Terminate register (IBCT) register bit field definitions
*/
#define IBCT_POISON (0x1 << 8)
#define IBCT_NOTIFY (0x1 << 4)
#define IBCT_ZFIL_MODE (0x1 << 0)
/*
* IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
*/
#define IIEPH1_VALID (1 << 44)
#define IIEPH1_OVERRUN (1 << 40)
#define IIEPH1_ERR_TYPE_SHFT 32
#define IIEPH1_ERR_TYPE_MASK 0xf
#define IIEPH1_SOURCE_SHFT 20
#define IIEPH1_SOURCE_MASK 11
#define IIEPH1_SUPPL_SHFT 8
#define IIEPH1_SUPPL_MASK 11
#define IIEPH1_CMD_SHFT 0
#define IIEPH1_CMD_MASK 7
#define IIEPH2_TAIL (1 << 40)
#define IIEPH2_ADDRESS_SHFT 0
#define IIEPH2_ADDRESS_MASK 38
#define IIEPH1_ERR_SHORT_REQ 2
#define IIEPH1_ERR_SHORT_REPLY 3
#define IIEPH1_ERR_LONG_REQ 4
#define IIEPH1_ERR_LONG_REPLY 5
/*
* IO Error Clear register bit field definitions
*/
#define IECLR_PI1_FWD_INT (1 << 31) /* clear PI1_FORWARD_INT in iidsr */
#define IECLR_PI0_FWD_INT (1 << 30) /* clear PI0_FORWARD_INT in iidsr */
#define IECLR_SPUR_RD_HDR (1 << 29) /* clear valid bit in ixss reg */
#define IECLR_BTE1 (1 << 18) /* clear bte error 1 */
#define IECLR_BTE0 (1 << 17) /* clear bte error 0 */
#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */
#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */
#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */
#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */
#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */
#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */
#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */
#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */
#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */
#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */
/*
* IIO CRB control register Fields: IIO_ICCR
*/
#define IIO_ICCR_PENDING (0x10000)
#define IIO_ICCR_CMD_MASK (0xFF)
#define IIO_ICCR_CMD_SHFT (7)
#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
* via a WB
*/
#define IIO_ICCR_CMD_FLUSH (0x800)
/*
*
* CRB Register description.
*
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
* WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
*
* Many of the fields in CRB are status bits used by hardware
* for implementation of the protocol. It's very dangerous to
* mess around with the CRB registers.
*
* It's OK to read the CRB registers and try to make sense out of the
* fields in CRB.
*
* Updating CRB requires all activities in Hub IIO to be quiesced.
* otherwise, a write to CRB could corrupt other CRB entries.
* CRBs are here only as a back door peek to shub IIO's status.
* Quiescing implies no dmas no PIOs
* either directly from the cpu or from sn0net.
* this is not something that can be done easily. So, AVOID updating
* CRBs.
*/
#ifndef __ASSEMBLY__
/*
* Easy access macros for CRBs, all 4 registers (A-D)
*/
typedef ii_icrb0_a_u_t icrba_t;
#define a_lnetuce ii_icrb0_a_fld_s.ia_ln_uce
#define a_mark ii_icrb0_a_fld_s.ia_mark
#define a_xerr ii_icrb0_a_fld_s.ia_xt_err
#define a_sidn ii_icrb0_a_fld_s.ia_sidn
#define a_tnum ii_icrb0_a_fld_s.ia_tnum
#define a_addr ii_icrb0_a_fld_s.ia_addr
#define a_valid ii_icrb0_a_fld_s.ia_vld
#define a_iow ii_icrb0_a_fld_s.ia_iow
#define a_regvalue ii_icrb0_a_regval
typedef ii_icrb0_b_u_t icrbb_t;
#define b_error ii_icrb0_b_fld_s.ib_error
#define b_ecode ii_icrb0_b_fld_s.ib_errcode
#define b_cohtrans ii_icrb0_b_fld_s.ib_ct
#define b_xtsize ii_icrb0_b_fld_s.ib_size
#define b_source ii_icrb0_b_fld_s.ib_source
#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
#define b_imsg ii_icrb0_b_fld_s.ib_imsg
#define b_initiator ii_icrb0_b_fld_s.ib_init
#define b_regvalue ii_icrb0_b_regval
typedef ii_icrb0_c_u_t icrbc_t;
#define c_btenum ii_icrb0_c_fld_s.ic_bte_num
#define c_pricnt ii_icrb0_c_fld_s.ic_pr_cnt
#define c_pripsc ii_icrb0_c_fld_s.ic_pr_psc
#define c_bteaddr ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
#define c_benable ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
#define c_suppl ii_icrb0_c_fld_s.ic_suppl
#define c_barrop ii_icrb0_c_fld_s.ic_bo
#define c_doresp ii_icrb0_c_fld_s.ic_resprqd
#define c_gbr ii_icrb0_c_fld_s.ic_gbr
#define c_regvalue ii_icrb0_c_regval
typedef ii_icrb0_d_u_t icrbd_t;
#define d_bteop ii_icrb0_d_fld_s.id_bte_op
#define icrbd_ctxtvld ii_icrb0_d_fld_s.id_cvld
#define icrbd_toutvld ii_icrb0_d_fld_s.id_tvld
#define icrbd_context ii_icrb0_d_fld_s.id_context
#define d_regvalue ii_icrb0_d_regval
#endif /* __ASSEMBLY__ */
/* Number of widgets supported by shub */
#define HUB_NUM_WIDGET 9
#define HUB_WIDGET_ID_MIN 0x8
#define HUB_WIDGET_ID_MAX 0xf
#define HUB_WIDGET_PART_NUM 0xc120
#define MAX_HUBS_PER_XBOW 2
#ifndef __ASSEMBLY__
/* A few more #defines for backwards compatibility */
#define iprb_t ii_iprb0_u_t
#define iprb_regval ii_iprb0_regval
#define iprb_mult_err ii_iprb0_fld_s.i_mult_err
#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
#define iprb_rd_to ii_iprb0_fld_s.i_rd_to
#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
#define iprb_error ii_iprb0_fld_s.i_error
#define iprb_ff ii_iprb0_fld_s.i_f
#define iprb_mode ii_iprb0_fld_s.i_m
#define iprb_bnakctr ii_iprb0_fld_s.i_nb
#define iprb_anakctr ii_iprb0_fld_s.i_na
#define iprb_xtalkctr ii_iprb0_fld_s.i_c
#endif
#define LNK_STAT_WORKING 0x2 /* LLP is working */
#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */
#define IIO_WSTAT_TXRETRY_SHFT (16)
#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) &
IIO_WSTAT_TXRETRY_MASK)
/* Number of II perf. counters we can multiplex at once */
#define IO_PERF_SETS 32
#if __KERNEL__
#ifndef __ASSEMBLY__
#include <asm/sn/alenlist.h>
#include <asm/sn/dmamap.h>
#include <asm/sn/driver.h>
#include <asm/sn/xtalk/xtalk.h>
/* Bit for the widget in inbound access register */
#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w))
/* Bit for the widget in outbound access register */
#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w))
/* NOTE: The following define assumes that we are going to get
* widget numbers from 8 thru F and the device numbers within
* widget from 0 thru 7.
*/
#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
/* IO Interrupt Destination Register */
#define IIO_IIDSR_SENT_SHIFT 28
#define IIO_IIDSR_SENT_MASK 0x30000000
#define IIO_IIDSR_ENB_SHIFT 24
#define IIO_IIDSR_ENB_MASK 0x01000000
#define IIO_IIDSR_NODE_SHIFT 9
#define IIO_IIDSR_NODE_MASK 0x000ff700
#define IIO_IIDSR_PI_ID_SHIFT 8
#define IIO_IIDSR_PI_ID_MASK 0x00000100
#define IIO_IIDSR_LVL_SHIFT 0
#define IIO_IIDSR_LVL_MASK 0x000000ff
/* Xtalk timeout threshhold register (IIO_IXTT) */
#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
/*
* The IO LLP control status register and widget control register
*/
typedef union hubii_wcr_u {
uint64_t wcr_reg_value;
struct {
uint64_t wcr_widget_id: 4, /* LLP crossbar credit */
wcr_tag_mode: 1, /* Tag mode */
wcr_rsvd1: 8, /* Reserved */
wcr_xbar_crd: 3, /* LLP crossbar credit */
wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
wcr_dir_con: 1, /* widget direct connect */
wcr_e_thresh: 5, /* elasticity threshold */
wcr_rsvd: 41; /* unused */
} wcr_fields_s;
} hubii_wcr_t;
#define iwcr_dir_con wcr_fields_s.wcr_dir_con
/* The structures below are defined to extract and modify the ii
performance registers */
/* io_perf_sel allows the caller to specify what tests will be
performed */
typedef union io_perf_sel {
uint64_t perf_sel_reg;
struct {
uint64_t perf_ippr0 : 4,
perf_ippr1 : 4,
perf_icct : 8,
perf_rsvd : 48;
} perf_sel_bits;
} io_perf_sel_t;
/* io_perf_cnt is to extract the count from the shub registers. Due to
hardware problems there is only one counter, not two. */
typedef union io_perf_cnt {
uint64_t perf_cnt;
struct {
uint64_t perf_cnt : 20,
perf_rsvd2 : 12,
perf_rsvd1 : 32;
} perf_cnt_bits;
} io_perf_cnt_t;
typedef union iprte_a {
shubreg_t entry;
struct {
shubreg_t i_rsvd_1 : 3;
shubreg_t i_addr : 38;
shubreg_t i_init : 3;
shubreg_t i_source : 8;
shubreg_t i_rsvd : 2;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} iprte_fields;
} iprte_a_t;
/* PIO MANAGEMENT */
typedef struct hub_piomap_s *hub_piomap_t;
extern hub_piomap_t
hub_piomap_alloc(devfs_handle_t dev, /* set up mapping for this device */
device_desc_t dev_desc, /* device descriptor */
iopaddr_t xtalk_addr, /* map for this xtalk_addr range */
size_t byte_count,
size_t byte_count_max, /* maximum size of a mapping */
unsigned flags); /* defined in sys/pio.h */
extern void hub_piomap_free(hub_piomap_t hub_piomap);
extern caddr_t
hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */
iopaddr_t xtalk_addr, /* map for this xtalk addr */
size_t byte_count); /* map this many bytes */
extern void
hub_piomap_done(hub_piomap_t hub_piomap);
extern caddr_t
hub_piotrans_addr( devfs_handle_t dev, /* translate to this device */
device_desc_t dev_desc, /* device descriptor */
iopaddr_t xtalk_addr, /* Crosstalk address */
size_t byte_count, /* map this many bytes */
unsigned flags); /* (currently unused) */
/* DMA MANAGEMENT */
typedef struct hub_dmamap_s *hub_dmamap_t;
extern hub_dmamap_t
hub_dmamap_alloc( devfs_handle_t dev, /* set up mappings for dev */
device_desc_t dev_desc, /* device descriptor */
size_t byte_count_max, /* max size of a mapping */
unsigned flags); /* defined in dma.h */
extern void
hub_dmamap_free(hub_dmamap_t dmamap);
extern iopaddr_t
hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */
paddr_t paddr, /* map for this address */
size_t byte_count); /* map this many bytes */
extern alenlist_t
hub_dmamap_list( hub_dmamap_t dmamap, /* use mapping resources */
alenlist_t alenlist, /* map this Addr/Length List */
unsigned flags);
extern void
hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */
extern iopaddr_t
hub_dmatrans_addr( devfs_handle_t dev, /* translate for this device */
device_desc_t dev_desc, /* device descriptor */
paddr_t paddr, /* system physical address */
size_t byte_count, /* length */
unsigned flags); /* defined in dma.h */
extern alenlist_t
hub_dmatrans_list( devfs_handle_t dev, /* translate for this device */
device_desc_t dev_desc, /* device descriptor */
alenlist_t palenlist, /* system addr/length list */
unsigned flags); /* defined in dma.h */
extern void
hub_dmamap_drain( hub_dmamap_t map);
extern void
hub_dmaaddr_drain( devfs_handle_t vhdl,
paddr_t addr,
size_t bytes);
extern void
hub_dmalist_drain( devfs_handle_t vhdl,
alenlist_t list);
/* INTERRUPT MANAGEMENT */
typedef struct hub_intr_s *hub_intr_t;
extern hub_intr_t
hub_intr_alloc( devfs_handle_t dev, /* which device */
device_desc_t dev_desc, /* device descriptor */
devfs_handle_t owner_dev); /* owner of this interrupt */
extern hub_intr_t
hub_intr_alloc_nothd(devfs_handle_t dev, /* which device */
device_desc_t dev_desc, /* device descriptor */
devfs_handle_t owner_dev); /* owner of this interrupt */
extern void
hub_intr_free(hub_intr_t intr_hdl);
extern int
hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */
xtalk_intr_setfunc_t setfunc,
/* func to set intr hw */
void *setfunc_arg); /* arg to setfunc */
extern void
hub_intr_disconnect(hub_intr_t intr_hdl);
extern devfs_handle_t
hub_intr_cpu_get(hub_intr_t intr_hdl);
/* CONFIGURATION MANAGEMENT */
extern void
hub_provider_startup(devfs_handle_t hub);
extern void
hub_provider_shutdown(devfs_handle_t hub);
#define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */
#define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */
/* Flags that make sense to hub_widget_flags_set */
#define HUB_WIDGET_FLAGS (
HUB_PIO_CONVEYOR |
HUB_PIO_FIRE_N_FORGET
)
typedef int hub_widget_flags_t;
/* Set the PIO mode for a widget. These two functions perform the
* same operation, but hub_device_flags_set() takes a hardware graph
* vertex while hub_widget_flags_set() takes a nasid and widget
* number. In most cases, hub_device_flags_set() should be used.
*/
extern int hub_widget_flags_set(nasid_t nasid,
xwidgetnum_t widget_num,
hub_widget_flags_t flags);
/* Depending on the flags set take the appropriate actions */
extern int hub_device_flags_set(devfs_handle_t widget_dev,
hub_widget_flags_t flags);
/* Error Handling. */
extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *);
extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t,
int, paddr_t, caddr_t, ioerror_mode_t);
extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t);
extern int hub_error_devenable(devfs_handle_t, int, int);
extern void hub_widgetdev_enable(devfs_handle_t, int);
extern void hub_widgetdev_shutdown(devfs_handle_t, int);
extern int hub_dma_enabled(devfs_handle_t);
/* hubdev */
extern void hubdev_init(void);
extern void hubdev_register(int (*attach_method)(devfs_handle_t));
extern int hubdev_unregister(int (*attach_method)(devfs_handle_t));
extern int hubdev_docallouts(devfs_handle_t hub);
extern caddr_t hubdev_prombase_get(devfs_handle_t hub);
extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub);
#endif /* __ASSEMBLY__ */
#endif /* _KERNEL */
#endif /* _ASM_IA64_SN_SN2_SHUBIO_H */