Linux/Unix编程

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Unix_Linux

hubpi.h：源码内容

bdrkreg_t gba_rsvd : 52;
bdrkreg_t gba_gfx_bias : 12;
} pi_gfx_bias_a_fld_s;
} pi_gfx_bias_a_u_t;
#endif
/************************************************************************
* *
* Description: There is one of these registers for each CPU. When *
* this counter reaches the value of the GFX_INT_CMP register, an *
* interrupt is sent to the associated processor. At each clock *
* cycle, the value in this register can be changed by any one of the *
* following actions: *
* - Written by software. *
* - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or *
* soft reset occurs, thus preventing an additional interrupt. *
* - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. *
* - Incremented (by one at each clock) for each clock that the *
* GFX_CREDIT_CNTR is less than or equal to zero. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_int_cntr_a_u {
bdrkreg_t pi_gfx_int_cntr_a_regval;
struct {
bdrkreg_t gica_gfx_int_cntr : 26;
bdrkreg_t gica_rsvd : 38;
} pi_gfx_int_cntr_a_fld_s;
} pi_gfx_int_cntr_a_u_t;
#else
typedef union pi_gfx_int_cntr_a_u {
bdrkreg_t pi_gfx_int_cntr_a_regval;
struct {
bdrkreg_t gica_rsvd : 38;
bdrkreg_t gica_gfx_int_cntr : 26;
} pi_gfx_int_cntr_a_fld_s;
} pi_gfx_int_cntr_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. The value in this *
* register is loaded into the GFX_INT_CNTR register when an *
* interrupt, NMI, or soft reset is sent to the processor. The value *
* in this register is compared to the value of GFX_INT_CNTR and an *
* interrupt is sent when they become equal. *
* *
************************************************************************/
#ifdef LINUX
typedef union pi_gfx_int_cmp_a_u {
bdrkreg_t pi_gfx_int_cmp_a_regval;
struct {
bdrkreg_t gica_gfx_int_cmp : 26;
bdrkreg_t gica_rsvd : 38;
} pi_gfx_int_cmp_a_fld_s;
} pi_gfx_int_cmp_a_u_t;
#else
typedef union pi_gfx_int_cmp_a_u {
bdrkreg_t pi_gfx_int_cmp_a_regval;
struct {
bdrkreg_t gica_rsvd : 38;
bdrkreg_t gica_gfx_int_cmp : 26;
} pi_gfx_int_cmp_a_fld_s;
} pi_gfx_int_cmp_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. This register *
* specifies the value of the Graphics Page. Uncached writes into the *
* Graphics Page (with uncached attribute of IO) are done with GFXWS *
* commands rather than the normal PWRI commands. GFXWS commands are *
* tracked with the graphics credit counters. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_page_b_u {
bdrkreg_t pi_gfx_page_b_regval;
struct {
bdrkreg_t gpb_rsvd_1 : 17;
bdrkreg_t gpb_gfx_page_addr : 23;
bdrkreg_t gpb_en_gfx_page : 1;
bdrkreg_t gpb_rsvd : 23;
} pi_gfx_page_b_fld_s;
} pi_gfx_page_b_u_t;
#else
typedef union pi_gfx_page_b_u {
bdrkreg_t pi_gfx_page_b_regval;
struct {
bdrkreg_t gpb_rsvd : 23;
bdrkreg_t gpb_en_gfx_page : 1;
bdrkreg_t gpb_gfx_page_addr : 23;
bdrkreg_t gpb_rsvd_1 : 17;
} pi_gfx_page_b_fld_s;
} pi_gfx_page_b_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. This register *
* counts graphics credits. This counter is decremented for each *
* doubleword sent to graphics with GFXWS or GFXWL commands. It is *
* incremented for each doubleword acknowledge from graphics. When *
* this counter has a smaller value than the GFX_BIAS register, *
* SysWrRdy_L is deasserted, an interrupt is sent to the processor, *
* and SysWrRdy_L is allowed to be asserted again. This is the basic *
* mechanism for flow-controlling graphics writes. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_credit_cntr_b_u {
bdrkreg_t pi_gfx_credit_cntr_b_regval;
struct {
bdrkreg_t gccb_gfx_credit_cntr : 12;
bdrkreg_t gccb_rsvd : 52;
} pi_gfx_credit_cntr_b_fld_s;
} pi_gfx_credit_cntr_b_u_t;
#else
typedef union pi_gfx_credit_cntr_b_u {
bdrkreg_t pi_gfx_credit_cntr_b_regval;
struct {
bdrkreg_t gccb_rsvd : 52;
bdrkreg_t gccb_gfx_credit_cntr : 12;
} pi_gfx_credit_cntr_b_fld_s;
} pi_gfx_credit_cntr_b_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. When the graphics *
* credit counter is less than or equal to this value, a flow control *
* interrupt is sent. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_bias_b_u {
bdrkreg_t pi_gfx_bias_b_regval;
struct {
bdrkreg_t gbb_gfx_bias : 12;
bdrkreg_t gbb_rsvd : 52;
} pi_gfx_bias_b_fld_s;
} pi_gfx_bias_b_u_t;
#else
typedef union pi_gfx_bias_b_u {
bdrkreg_t pi_gfx_bias_b_regval;
struct {
bdrkreg_t gbb_rsvd : 52;
bdrkreg_t gbb_gfx_bias : 12;
} pi_gfx_bias_b_fld_s;
} pi_gfx_bias_b_u_t;
#endif
/************************************************************************
* *
* Description: There is one of these registers for each CPU. When *
* this counter reaches the value of the GFX_INT_CMP register, an *
* interrupt is sent to the associated processor. At each clock *
* cycle, the value in this register can be changed by any one of the *
* following actions: *
* - Written by software. *
* - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or *
* soft reset occurs, thus preventing an additional interrupt. *
* - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. *
* - Incremented (by one at each clock) for each clock that the *
* GFX_CREDIT_CNTR is less than or equal to zero. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_int_cntr_b_u {
bdrkreg_t pi_gfx_int_cntr_b_regval;
struct {
bdrkreg_t gicb_gfx_int_cntr : 26;
bdrkreg_t gicb_rsvd : 38;
} pi_gfx_int_cntr_b_fld_s;
} pi_gfx_int_cntr_b_u_t;
#else
typedef union pi_gfx_int_cntr_b_u {
bdrkreg_t pi_gfx_int_cntr_b_regval;
struct {
bdrkreg_t gicb_rsvd : 38;
bdrkreg_t gicb_gfx_int_cntr : 26;
} pi_gfx_int_cntr_b_fld_s;
} pi_gfx_int_cntr_b_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. The value in this *
* register is loaded into the GFX_INT_CNTR register when an *
* interrupt, NMI, or soft reset is sent to the processor. The value *
* in this register is compared to the value of GFX_INT_CNTR and an *
* interrupt is sent when they become equal. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_int_cmp_b_u {
bdrkreg_t pi_gfx_int_cmp_b_regval;
struct {
bdrkreg_t gicb_gfx_int_cmp : 26;
bdrkreg_t gicb_rsvd : 38;
} pi_gfx_int_cmp_b_fld_s;
} pi_gfx_int_cmp_b_u_t;
#else
typedef union pi_gfx_int_cmp_b_u {
bdrkreg_t pi_gfx_int_cmp_b_regval;
struct {
bdrkreg_t gicb_rsvd : 38;
bdrkreg_t gicb_gfx_int_cmp : 26;
} pi_gfx_int_cmp_b_fld_s;
} pi_gfx_int_cmp_b_u_t;
#endif
/************************************************************************
* *
* Description: A read of this register returns all sources of *
* Bedrock Error Interrupts. Storing to the write-with-clear location *
* clears any bit for which a one appears on the data bus. Storing to *
* the writable location does a direct write to all unreserved bits *
* (except for MEM_UNC). *
* In Synergy mode, the processor that is the source of the command *
* that got an error is independent of the A or B SysAD bus. So in *
* Synergy mode, Synergy provides the source processor number in bit *
* 52 of the SysAD bus in all commands. The PI saves this in the RRB *
* or WRB entry, and uses that value to determine which error bit (A *
* or B) to set, as well as which ERR_STATUS and spool registers to *
* use, for all error types in this register that are specified as an *
* error to CPU_A or CPU_B. *
* This register is not cleared at reset. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_int_pend_wr_u {
bdrkreg_t pi_err_int_pend_wr_regval;
struct {
bdrkreg_t eipw_spool_comp_b : 1;
bdrkreg_t eipw_spool_comp_a : 1;
bdrkreg_t eipw_spurious_b : 1;
bdrkreg_t eipw_spurious_a : 1;
bdrkreg_t eipw_wrb_terr_b : 1;
bdrkreg_t eipw_wrb_terr_a : 1;
bdrkreg_t eipw_wrb_werr_b : 1;
bdrkreg_t eipw_wrb_werr_a : 1;
bdrkreg_t eipw_sysstate_par_b : 1;
bdrkreg_t eipw_sysstate_par_a : 1;
bdrkreg_t eipw_sysad_data_ecc_b : 1;
bdrkreg_t eipw_sysad_data_ecc_a : 1;
bdrkreg_t eipw_sysad_addr_ecc_b : 1;
bdrkreg_t eipw_sysad_addr_ecc_a : 1;
bdrkreg_t eipw_syscmd_data_par_b : 1;
bdrkreg_t eipw_syscmd_data_par_a : 1;
bdrkreg_t eipw_syscmd_addr_par_b : 1;
bdrkreg_t eipw_syscmd_addr_par_a : 1;
bdrkreg_t eipw_spool_err_b : 1;
bdrkreg_t eipw_spool_err_a : 1;
bdrkreg_t eipw_ue_uncached_b : 1;
bdrkreg_t eipw_ue_uncached_a : 1;
bdrkreg_t eipw_sysstate_tag_b : 1;
bdrkreg_t eipw_sysstate_tag_a : 1;
bdrkreg_t eipw_mem_unc : 1;
bdrkreg_t eipw_sysad_bad_data_b : 1;
bdrkreg_t eipw_sysad_bad_data_a : 1;
bdrkreg_t eipw_ue_cached_b : 1;
bdrkreg_t eipw_ue_cached_a : 1;
bdrkreg_t eipw_pkt_len_err_b : 1;
bdrkreg_t eipw_pkt_len_err_a : 1;
bdrkreg_t eipw_irb_err_b : 1;
bdrkreg_t eipw_irb_err_a : 1;
bdrkreg_t eipw_irb_timeout_b : 1;
bdrkreg_t eipw_irb_timeout_a : 1;
bdrkreg_t eipw_rsvd : 29;
} pi_err_int_pend_wr_fld_s;
} pi_err_int_pend_wr_u_t;
#else
typedef union pi_err_int_pend_wr_u {
bdrkreg_t pi_err_int_pend_wr_regval;
struct {
bdrkreg_t eipw_rsvd : 29;
bdrkreg_t eipw_irb_timeout_a : 1;
bdrkreg_t eipw_irb_timeout_b : 1;
bdrkreg_t eipw_irb_err_a : 1;
bdrkreg_t eipw_irb_err_b : 1;
bdrkreg_t eipw_pkt_len_err_a : 1;
bdrkreg_t eipw_pkt_len_err_b : 1;
bdrkreg_t eipw_ue_cached_a : 1;
bdrkreg_t eipw_ue_cached_b : 1;
bdrkreg_t eipw_sysad_bad_data_a : 1;
bdrkreg_t eipw_sysad_bad_data_b : 1;
bdrkreg_t eipw_mem_unc : 1;
bdrkreg_t eipw_sysstate_tag_a : 1;
bdrkreg_t eipw_sysstate_tag_b : 1;
bdrkreg_t eipw_ue_uncached_a : 1;
bdrkreg_t eipw_ue_uncached_b : 1;
bdrkreg_t eipw_spool_err_a : 1;
bdrkreg_t eipw_spool_err_b : 1;
bdrkreg_t eipw_syscmd_addr_par_a : 1;
bdrkreg_t eipw_syscmd_addr_par_b : 1;
bdrkreg_t eipw_syscmd_data_par_a : 1;
bdrkreg_t eipw_syscmd_data_par_b : 1;
bdrkreg_t eipw_sysad_addr_ecc_a : 1;
bdrkreg_t eipw_sysad_addr_ecc_b : 1;
bdrkreg_t eipw_sysad_data_ecc_a : 1;
bdrkreg_t eipw_sysad_data_ecc_b : 1;
bdrkreg_t eipw_sysstate_par_a : 1;
bdrkreg_t eipw_sysstate_par_b : 1;
bdrkreg_t eipw_wrb_werr_a : 1;
bdrkreg_t eipw_wrb_werr_b : 1;
bdrkreg_t eipw_wrb_terr_a : 1;
bdrkreg_t eipw_wrb_terr_b : 1;
bdrkreg_t eipw_spurious_a : 1;
bdrkreg_t eipw_spurious_b : 1;
bdrkreg_t eipw_spool_comp_a : 1;
bdrkreg_t eipw_spool_comp_b : 1;
} pi_err_int_pend_wr_fld_s;
} pi_err_int_pend_wr_u_t;
#endif
/************************************************************************
* *
* Description: A read of this register returns all sources of *
* Bedrock Error Interrupts. Storing to the write-with-clear location *
* clears any bit for which a one appears on the data bus. Storing to *
* the writable location does a direct write to all unreserved bits *
* (except for MEM_UNC). *
* In Synergy mode, the processor that is the source of the command *
* that got an error is independent of the A or B SysAD bus. So in *
* Synergy mode, Synergy provides the source processor number in bit *
* 52 of the SysAD bus in all commands. The PI saves this in the RRB *
* or WRB entry, and uses that value to determine which error bit (A *
* or B) to set, as well as which ERR_STATUS and spool registers to *
* use, for all error types in this register that are specified as an *
* error to CPU_A or CPU_B. *
* This register is not cleared at reset. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_int_pend_u {
bdrkreg_t pi_err_int_pend_regval;
struct {
bdrkreg_t eip_spool_comp_b : 1;
bdrkreg_t eip_spool_comp_a : 1;
bdrkreg_t eip_spurious_b : 1;
bdrkreg_t eip_spurious_a : 1;
bdrkreg_t eip_wrb_terr_b : 1;
bdrkreg_t eip_wrb_terr_a : 1;
bdrkreg_t eip_wrb_werr_b : 1;
bdrkreg_t eip_wrb_werr_a : 1;
bdrkreg_t eip_sysstate_par_b : 1;
bdrkreg_t eip_sysstate_par_a : 1;
bdrkreg_t eip_sysad_data_ecc_b : 1;
bdrkreg_t eip_sysad_data_ecc_a : 1;
bdrkreg_t eip_sysad_addr_ecc_b : 1;
bdrkreg_t eip_sysad_addr_ecc_a : 1;
bdrkreg_t eip_syscmd_data_par_b : 1;
bdrkreg_t eip_syscmd_data_par_a : 1;
bdrkreg_t eip_syscmd_addr_par_b : 1;
bdrkreg_t eip_syscmd_addr_par_a : 1;
bdrkreg_t eip_spool_err_b : 1;
bdrkreg_t eip_spool_err_a : 1;
bdrkreg_t eip_ue_uncached_b : 1;
bdrkreg_t eip_ue_uncached_a : 1;
bdrkreg_t eip_sysstate_tag_b : 1;
bdrkreg_t eip_sysstate_tag_a : 1;
bdrkreg_t eip_mem_unc : 1;
bdrkreg_t eip_sysad_bad_data_b : 1;
bdrkreg_t eip_sysad_bad_data_a : 1;
bdrkreg_t eip_ue_cached_b : 1;
bdrkreg_t eip_ue_cached_a : 1;
bdrkreg_t eip_pkt_len_err_b : 1;
bdrkreg_t eip_pkt_len_err_a : 1;
bdrkreg_t eip_irb_err_b : 1;
bdrkreg_t eip_irb_err_a : 1;
bdrkreg_t eip_irb_timeout_b : 1;
bdrkreg_t eip_irb_timeout_a : 1;
bdrkreg_t eip_rsvd : 29;
} pi_err_int_pend_fld_s;
} pi_err_int_pend_u_t;
#else
typedef union pi_err_int_pend_u {
bdrkreg_t pi_err_int_pend_regval;
struct {
bdrkreg_t eip_rsvd : 29;
bdrkreg_t eip_irb_timeout_a : 1;
bdrkreg_t eip_irb_timeout_b : 1;
bdrkreg_t eip_irb_err_a : 1;
bdrkreg_t eip_irb_err_b : 1;
bdrkreg_t eip_pkt_len_err_a : 1;
bdrkreg_t eip_pkt_len_err_b : 1;
bdrkreg_t eip_ue_cached_a : 1;
bdrkreg_t eip_ue_cached_b : 1;
bdrkreg_t eip_sysad_bad_data_a : 1;
bdrkreg_t eip_sysad_bad_data_b : 1;
bdrkreg_t eip_mem_unc : 1;
bdrkreg_t eip_sysstate_tag_a : 1;
bdrkreg_t eip_sysstate_tag_b : 1;
bdrkreg_t eip_ue_uncached_a : 1;
bdrkreg_t eip_ue_uncached_b : 1;
bdrkreg_t eip_spool_err_a : 1;
bdrkreg_t eip_spool_err_b : 1;
bdrkreg_t eip_syscmd_addr_par_a : 1;
bdrkreg_t eip_syscmd_addr_par_b : 1;
bdrkreg_t eip_syscmd_data_par_a : 1;
bdrkreg_t eip_syscmd_data_par_b : 1;
bdrkreg_t eip_sysad_addr_ecc_a : 1;
bdrkreg_t eip_sysad_addr_ecc_b : 1;
bdrkreg_t eip_sysad_data_ecc_a : 1;
bdrkreg_t eip_sysad_data_ecc_b : 1;
bdrkreg_t eip_sysstate_par_a : 1;
bdrkreg_t eip_sysstate_par_b : 1;
bdrkreg_t eip_wrb_werr_a : 1;
bdrkreg_t eip_wrb_werr_b : 1;
bdrkreg_t eip_wrb_terr_a : 1;
bdrkreg_t eip_wrb_terr_b : 1;
bdrkreg_t eip_spurious_a : 1;
bdrkreg_t eip_spurious_b : 1;
bdrkreg_t eip_spool_comp_a : 1;
bdrkreg_t eip_spool_comp_b : 1;
} pi_err_int_pend_fld_s;
} pi_err_int_pend_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. This read/write *
* register masks the contents of ERR_INT_PEND to determine which *
* conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set *
* allows the interrupt. Only one processor in a Bedrock should *
* enable the Memory/Directory Uncorrectable Error bit. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_int_mask_a_u {
bdrkreg_t pi_err_int_mask_a_regval;
struct {
bdrkreg_t eima_mask : 35;
bdrkreg_t eima_rsvd : 29;
} pi_err_int_mask_a_fld_s;
} pi_err_int_mask_a_u_t;
#else
typedef union pi_err_int_mask_a_u {
bdrkreg_t pi_err_int_mask_a_regval;
struct {
bdrkreg_t eima_rsvd : 29;
bdrkreg_t eima_mask : 35;
} pi_err_int_mask_a_fld_s;
} pi_err_int_mask_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. This read/write *
* register masks the contents of ERR_INT_PEND to determine which *
* conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set *
* allows the interrupt. Only one processor in a Bedrock should *
* enable the Memory/Directory Uncorrectable Error bit. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_int_mask_b_u {
bdrkreg_t pi_err_int_mask_b_regval;
struct {
bdrkreg_t eimb_mask : 35;
bdrkreg_t eimb_rsvd : 29;
} pi_err_int_mask_b_fld_s;
} pi_err_int_mask_b_u_t;
#else
typedef union pi_err_int_mask_b_u {
bdrkreg_t pi_err_int_mask_b_regval;
struct {
bdrkreg_t eimb_rsvd : 29;
bdrkreg_t eimb_mask : 35;
} pi_err_int_mask_b_fld_s;
} pi_err_int_mask_b_u_t;
#endif
/************************************************************************
* *
* Description: There is one of these registers for each CPU. This *
* register is the address of the next write to the error stack. This *
* register is incremented after each such write. Only the low N bits *
* are incremented, where N is defined by the size of the error stack *
* specified in the ERR_STACK_SIZE register. *
* This register is not reset by a soft reset. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_stack_addr_a_u {
bdrkreg_t pi_err_stack_addr_a_regval;
struct {
bdrkreg_t esaa_rsvd_1 : 3;
bdrkreg_t esaa_addr : 30;
bdrkreg_t esaa_rsvd : 31;
} pi_err_stack_addr_a_fld_s;
} pi_err_stack_addr_a_u_t;
#else
typedef union pi_err_stack_addr_a_u {
bdrkreg_t pi_err_stack_addr_a_regval;
struct {
bdrkreg_t esaa_rsvd : 31;
bdrkreg_t esaa_addr : 30;
bdrkreg_t esaa_rsvd_1 : 3;
} pi_err_stack_addr_a_fld_s;
} pi_err_stack_addr_a_u_t;
#endif
/************************************************************************
* *
* Description: There is one of these registers for each CPU. This *
* register is the address of the next write to the error stack. This *
* register is incremented after each such write. Only the low N bits *
* are incremented, where N is defined by the size of the error stack *
* specified in the ERR_STACK_SIZE register. *
* This register is not reset by a soft reset. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_stack_addr_b_u {
bdrkreg_t pi_err_stack_addr_b_regval;
struct {
bdrkreg_t esab_rsvd_1 : 3;
bdrkreg_t esab_addr : 30;
bdrkreg_t esab_rsvd : 31;
} pi_err_stack_addr_b_fld_s;
} pi_err_stack_addr_b_u_t;
#else
typedef union pi_err_stack_addr_b_u {
bdrkreg_t pi_err_stack_addr_b_regval;
struct {
bdrkreg_t esab_rsvd : 31;
bdrkreg_t esab_addr : 30;
bdrkreg_t esab_rsvd_1 : 3;
} pi_err_stack_addr_b_fld_s;
} pi_err_stack_addr_b_u_t;
#endif
/************************************************************************
* *
* Description: Sets the size (number of 64-bit entries) in the *
* error stack that is spooled to local memory when an error occurs. *
* Table16 defines the format of each entry in the spooled error *
* stack. *
* This register is not reset by a soft reset. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_stack_size_u {
bdrkreg_t pi_err_stack_size_regval;
struct {
bdrkreg_t ess_size : 4;
bdrkreg_t ess_rsvd : 60;
} pi_err_stack_size_fld_s;
} pi_err_stack_size_u_t;
#else
typedef union pi_err_stack_size_u {
bdrkreg_t pi_err_stack_size_regval;
struct {
bdrkreg_t ess_rsvd : 60;
bdrkreg_t ess_size : 4;
} pi_err_stack_size_fld_s;
} pi_err_stack_size_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_A and ERR_STATUS1_A registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status0_a_u {
bdrkreg_t pi_err_status0_a_regval;
struct {
bdrkreg_t esa_error_type : 3;
bdrkreg_t esa_proc_req_num : 3;
bdrkreg_t esa_supplemental : 11;
bdrkreg_t esa_cmd : 8;
bdrkreg_t esa_addr : 37;
bdrkreg_t esa_over_run : 1;
bdrkreg_t esa_valid : 1;
} pi_err_status0_a_fld_s;
} pi_err_status0_a_u_t;
#else
typedef union pi_err_status0_a_u {
bdrkreg_t pi_err_status0_a_regval;
struct {
bdrkreg_t esa_valid : 1;
bdrkreg_t esa_over_run : 1;
bdrkreg_t esa_addr : 37;
bdrkreg_t esa_cmd : 8;
bdrkreg_t esa_supplemental : 11;
bdrkreg_t esa_proc_req_num : 3;
bdrkreg_t esa_error_type : 3;
} pi_err_status0_a_fld_s;
} pi_err_status0_a_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_A and ERR_STATUS1_A registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status0_a_clr_u {
bdrkreg_t pi_err_status0_a_clr_regval;
struct {
bdrkreg_t esac_error_type : 3;
bdrkreg_t esac_proc_req_num : 3;
bdrkreg_t esac_supplemental : 11;
bdrkreg_t esac_cmd : 8;
bdrkreg_t esac_addr : 37;
bdrkreg_t esac_over_run : 1;
bdrkreg_t esac_valid : 1;
} pi_err_status0_a_clr_fld_s;
} pi_err_status0_a_clr_u_t;
#else
typedef union pi_err_status0_a_clr_u {
bdrkreg_t pi_err_status0_a_clr_regval;
struct {
bdrkreg_t esac_valid : 1;
bdrkreg_t esac_over_run : 1;
bdrkreg_t esac_addr : 37;
bdrkreg_t esac_cmd : 8;
bdrkreg_t esac_supplemental : 11;
bdrkreg_t esac_proc_req_num : 3;
bdrkreg_t esac_error_type : 3;
} pi_err_status0_a_clr_fld_s;
} pi_err_status0_a_clr_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_A and ERR_STATUS1_A registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status1_a_u {
bdrkreg_t pi_err_status1_a_regval;
struct {
bdrkreg_t esa_spool_count : 21;
bdrkreg_t esa_time_out_count : 8;
bdrkreg_t esa_inval_count : 10;
bdrkreg_t esa_crb_num : 3;
bdrkreg_t esa_wrb : 1;
bdrkreg_t esa_e_bits : 2;
bdrkreg_t esa_t_bit : 1;
bdrkreg_t esa_i_bit : 1;
bdrkreg_t esa_h_bit : 1;
bdrkreg_t esa_w_bit : 1;
bdrkreg_t esa_a_bit : 1;
bdrkreg_t esa_r_bit : 1;
bdrkreg_t esa_v_bit : 1;
bdrkreg_t esa_p_bit : 1;
bdrkreg_t esa_source : 11;
} pi_err_status1_a_fld_s;
} pi_err_status1_a_u_t;
#else
typedef union pi_err_status1_a_u {
bdrkreg_t pi_err_status1_a_regval;
struct {
bdrkreg_t esa_source : 11;
bdrkreg_t esa_p_bit : 1;
bdrkreg_t esa_v_bit : 1;
bdrkreg_t esa_r_bit : 1;
bdrkreg_t esa_a_bit : 1;
bdrkreg_t esa_w_bit : 1;
bdrkreg_t esa_h_bit : 1;
bdrkreg_t esa_i_bit : 1;
bdrkreg_t esa_t_bit : 1;
bdrkreg_t esa_e_bits : 2;
bdrkreg_t esa_wrb : 1;
bdrkreg_t esa_crb_num : 3;
bdrkreg_t esa_inval_count : 10;
bdrkreg_t esa_time_out_count : 8;
bdrkreg_t esa_spool_count : 21;
} pi_err_status1_a_fld_s;
} pi_err_status1_a_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_A and ERR_STATUS1_A registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status1_a_clr_u {
bdrkreg_t pi_err_status1_a_clr_regval;
struct {
bdrkreg_t esac_spool_count : 21;
bdrkreg_t esac_time_out_count : 8;
bdrkreg_t esac_inval_count : 10;
bdrkreg_t esac_crb_num : 3;
bdrkreg_t esac_wrb : 1;
bdrkreg_t esac_e_bits : 2;
bdrkreg_t esac_t_bit : 1;
bdrkreg_t esac_i_bit : 1;
bdrkreg_t esac_h_bit : 1;
bdrkreg_t esac_w_bit : 1;
bdrkreg_t esac_a_bit : 1;
bdrkreg_t esac_r_bit : 1;
bdrkreg_t esac_v_bit : 1;
bdrkreg_t esac_p_bit : 1;
bdrkreg_t esac_source : 11;
} pi_err_status1_a_clr_fld_s;
} pi_err_status1_a_clr_u_t;
#else
typedef union pi_err_status1_a_clr_u {
bdrkreg_t pi_err_status1_a_clr_regval;
struct {
bdrkreg_t esac_source : 11;
bdrkreg_t esac_p_bit : 1;
bdrkreg_t esac_v_bit : 1;
bdrkreg_t esac_r_bit : 1;
bdrkreg_t esac_a_bit : 1;
bdrkreg_t esac_w_bit : 1;
bdrkreg_t esac_h_bit : 1;
bdrkreg_t esac_i_bit : 1;
bdrkreg_t esac_t_bit : 1;
bdrkreg_t esac_e_bits : 2;
bdrkreg_t esac_wrb : 1;
bdrkreg_t esac_crb_num : 3;
bdrkreg_t esac_inval_count : 10;
bdrkreg_t esac_time_out_count : 8;
bdrkreg_t esac_spool_count : 21;
} pi_err_status1_a_clr_fld_s;
} pi_err_status1_a_clr_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_B and ERR_STATUS1_B registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status0_b_u {
bdrkreg_t pi_err_status0_b_regval;
struct {
bdrkreg_t esb_error_type : 3;
bdrkreg_t esb_proc_request_number : 3;
bdrkreg_t esb_supplemental : 11;
bdrkreg_t esb_cmd : 8;
bdrkreg_t esb_addr : 37;
bdrkreg_t esb_over_run : 1;
bdrkreg_t esb_valid : 1;
} pi_err_status0_b_fld_s;
} pi_err_status0_b_u_t;
#else
typedef union pi_err_status0_b_u {
bdrkreg_t pi_err_status0_b_regval;
struct {
bdrkreg_t esb_valid : 1;
bdrkreg_t esb_over_run : 1;
bdrkreg_t esb_addr : 37;
bdrkreg_t esb_cmd : 8;
bdrkreg_t esb_supplemental : 11;
bdrkreg_t esb_proc_request_number : 3;
bdrkreg_t esb_error_type : 3;
} pi_err_status0_b_fld_s;
} pi_err_status0_b_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_B and ERR_STATUS1_B registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status0_b_clr_u {
bdrkreg_t pi_err_status0_b_clr_regval;
struct {
bdrkreg_t esbc_error_type : 3;
bdrkreg_t esbc_proc_request_number : 3;
bdrkreg_t esbc_supplemental : 11;
bdrkreg_t esbc_cmd : 8;
bdrkreg_t esbc_addr : 37;
bdrkreg_t esbc_over_run : 1;
bdrkreg_t esbc_valid : 1;
} pi_err_status0_b_clr_fld_s;
} pi_err_status0_b_clr_u_t;
#else
typedef union pi_err_status0_b_clr_u {
bdrkreg_t pi_err_status0_b_clr_regval;
struct {
bdrkreg_t esbc_valid : 1;
bdrkreg_t esbc_over_run : 1;
bdrkreg_t esbc_addr : 37;
bdrkreg_t esbc_cmd : 8;
bdrkreg_t esbc_supplemental : 11;
bdrkreg_t esbc_proc_request_number : 3;
bdrkreg_t esbc_error_type : 3;
} pi_err_status0_b_clr_fld_s;
} pi_err_status0_b_clr_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_B and ERR_STATUS1_B registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status1_b_u {
bdrkreg_t pi_err_status1_b_regval;
struct {
bdrkreg_t esb_spool_count : 21;
bdrkreg_t esb_time_out_count : 8;
bdrkreg_t esb_inval_count : 10;
bdrkreg_t esb_crb_num : 3;
bdrkreg_t esb_wrb : 1;
bdrkreg_t esb_e_bits : 2;
bdrkreg_t esb_t_bit : 1;
bdrkreg_t esb_i_bit : 1;
bdrkreg_t esb_h_bit : 1;
bdrkreg_t esb_w_bit : 1;
bdrkreg_t esb_a_bit : 1;
bdrkreg_t esb_r_bit : 1;
bdrkreg_t esb_v_bit : 1;
bdrkreg_t esb_p_bit : 1;
bdrkreg_t esb_source : 11;
} pi_err_status1_b_fld_s;
} pi_err_status1_b_u_t;
#else
typedef union pi_err_status1_b_u {
bdrkreg_t pi_err_status1_b_regval;
struct {
bdrkreg_t esb_source : 11;
bdrkreg_t esb_p_bit : 1;
bdrkreg_t esb_v_bit : 1;
bdrkreg_t esb_r_bit : 1;
bdrkreg_t esb_a_bit : 1;
bdrkreg_t esb_w_bit : 1;
bdrkreg_t esb_h_bit : 1;
bdrkreg_t esb_i_bit : 1;
bdrkreg_t esb_t_bit : 1;
bdrkreg_t esb_e_bits : 2;
bdrkreg_t esb_wrb : 1;
bdrkreg_t esb_crb_num : 3;
bdrkreg_t esb_inval_count : 10;
bdrkreg_t esb_time_out_count : 8;
bdrkreg_t esb_spool_count : 21;
} pi_err_status1_b_fld_s;
} pi_err_status1_b_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. Writing this register with *
* the Write-clear address (with any data) clears both the *
* ERR_STATUS0_B and ERR_STATUS1_B registers. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_status1_b_clr_u {
bdrkreg_t pi_err_status1_b_clr_regval;
struct {
bdrkreg_t esbc_spool_count : 21;
bdrkreg_t esbc_time_out_count : 8;
bdrkreg_t esbc_inval_count : 10;
bdrkreg_t esbc_crb_num : 3;
bdrkreg_t esbc_wrb : 1;
bdrkreg_t esbc_e_bits : 2;
bdrkreg_t esbc_t_bit : 1;
bdrkreg_t esbc_i_bit : 1;
bdrkreg_t esbc_h_bit : 1;
bdrkreg_t esbc_w_bit : 1;
bdrkreg_t esbc_a_bit : 1;
bdrkreg_t esbc_r_bit : 1;
bdrkreg_t esbc_v_bit : 1;
bdrkreg_t esbc_p_bit : 1;
bdrkreg_t esbc_source : 11;
} pi_err_status1_b_clr_fld_s;
} pi_err_status1_b_clr_u_t;
#else
typedef union pi_err_status1_b_clr_u {
bdrkreg_t pi_err_status1_b_clr_regval;
struct {
bdrkreg_t esbc_source : 11;
bdrkreg_t esbc_p_bit : 1;
bdrkreg_t esbc_v_bit : 1;
bdrkreg_t esbc_r_bit : 1;
bdrkreg_t esbc_a_bit : 1;
bdrkreg_t esbc_w_bit : 1;
bdrkreg_t esbc_h_bit : 1;
bdrkreg_t esbc_i_bit : 1;
bdrkreg_t esbc_t_bit : 1;
bdrkreg_t esbc_e_bits : 2;
bdrkreg_t esbc_wrb : 1;
bdrkreg_t esbc_crb_num : 3;
bdrkreg_t esbc_inval_count : 10;
bdrkreg_t esbc_time_out_count : 8;
bdrkreg_t esbc_spool_count : 21;
} pi_err_status1_b_clr_fld_s;
} pi_err_status1_b_clr_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_spool_cmp_a_u {
bdrkreg_t pi_spool_cmp_a_regval;
struct {
bdrkreg_t sca_compare : 20;
bdrkreg_t sca_rsvd : 44;
} pi_spool_cmp_a_fld_s;
} pi_spool_cmp_a_u_t;
#else
typedef union pi_spool_cmp_a_u {
bdrkreg_t pi_spool_cmp_a_regval;
struct {
bdrkreg_t sca_rsvd : 44;
bdrkreg_t sca_compare : 20;
} pi_spool_cmp_a_fld_s;
} pi_spool_cmp_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_spool_cmp_b_u {
bdrkreg_t pi_spool_cmp_b_regval;
struct {
bdrkreg_t scb_compare : 20;
bdrkreg_t scb_rsvd : 44;
} pi_spool_cmp_b_fld_s;
} pi_spool_cmp_b_u_t;
#else
typedef union pi_spool_cmp_b_u {
bdrkreg_t pi_spool_cmp_b_regval;
struct {
bdrkreg_t scb_rsvd : 44;
bdrkreg_t scb_compare : 20;
} pi_spool_cmp_b_fld_s;
} pi_spool_cmp_b_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. A timeout can be *
* forced by writing one(s). *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_crb_timeout_a_u {
bdrkreg_t pi_crb_timeout_a_regval;
struct {
bdrkreg_t cta_rrb : 4;
bdrkreg_t cta_wrb : 8;
bdrkreg_t cta_rsvd : 52;
} pi_crb_timeout_a_fld_s;
} pi_crb_timeout_a_u_t;
#else
typedef union pi_crb_timeout_a_u {
bdrkreg_t pi_crb_timeout_a_regval;
struct {
bdrkreg_t cta_rsvd : 52;
bdrkreg_t cta_wrb : 8;
bdrkreg_t cta_rrb : 4;
} pi_crb_timeout_a_fld_s;
} pi_crb_timeout_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. A timeout can be *
* forced by writing one(s). *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_crb_timeout_b_u {
bdrkreg_t pi_crb_timeout_b_regval;
struct {
bdrkreg_t ctb_rrb : 4;
bdrkreg_t ctb_wrb : 8;
bdrkreg_t ctb_rsvd : 52;
} pi_crb_timeout_b_fld_s;
} pi_crb_timeout_b_u_t;
#else
typedef union pi_crb_timeout_b_u {
bdrkreg_t pi_crb_timeout_b_regval;
struct {
bdrkreg_t ctb_rsvd : 52;
bdrkreg_t ctb_wrb : 8;
bdrkreg_t ctb_rrb : 4;
} pi_crb_timeout_b_fld_s;
} pi_crb_timeout_b_u_t;
#endif
/************************************************************************
* *
* This register controls error checking and forwarding of SysAD *
* errors. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_sysad_errchk_en_u {
bdrkreg_t pi_sysad_errchk_en_regval;
struct {
bdrkreg_t see_ecc_gen_en : 1;
bdrkreg_t see_qual_gen_en : 1;
bdrkreg_t see_sadp_chk_en : 1;
bdrkreg_t see_cmdp_chk_en : 1;
bdrkreg_t see_state_chk_en : 1;
bdrkreg_t see_qual_chk_en : 1;
bdrkreg_t see_rsvd : 58;
} pi_sysad_errchk_en_fld_s;
} pi_sysad_errchk_en_u_t;
#else
typedef union pi_sysad_errchk_en_u {
bdrkreg_t pi_sysad_errchk_en_regval;
struct {
bdrkreg_t see_rsvd : 58;
bdrkreg_t see_qual_chk_en : 1;
bdrkreg_t see_state_chk_en : 1;
bdrkreg_t see_cmdp_chk_en : 1;
bdrkreg_t see_sadp_chk_en : 1;
bdrkreg_t see_qual_gen_en : 1;
bdrkreg_t see_ecc_gen_en : 1;
} pi_sysad_errchk_en_fld_s;
} pi_sysad_errchk_en_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. If any bit in this *
* register is set, then whenever reply data arrives with the UE *
* (uncorrectable error) indication set, the check-bits that are *
* generated and sent to the SysAD will be inverted corresponding to *
* the bits set in the register. This will also prevent the assertion *
* of the data quality indicator. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_force_bad_check_bit_a_u {
bdrkreg_t pi_force_bad_check_bit_a_regval;
struct {
bdrkreg_t fbcba_bad_check_bit : 8;
bdrkreg_t fbcba_rsvd : 56;
} pi_force_bad_check_bit_a_fld_s;
} pi_force_bad_check_bit_a_u_t;
#else
typedef union pi_force_bad_check_bit_a_u {
bdrkreg_t pi_force_bad_check_bit_a_regval;
struct {
bdrkreg_t fbcba_rsvd : 56;
bdrkreg_t fbcba_bad_check_bit : 8;
} pi_force_bad_check_bit_a_fld_s;
} pi_force_bad_check_bit_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. If any bit in this *
* register is set, then whenever reply data arrives with the UE *
* (uncorrectable error) indication set, the check-bits that are *
* generated and sent to the SysAD will be inverted corresponding to *
* the bits set in the register. This will also prevent the assertion *
* of the data quality indicator. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_force_bad_check_bit_b_u {
bdrkreg_t pi_force_bad_check_bit_b_regval;
struct {
bdrkreg_t fbcbb_bad_check_bit : 8;
bdrkreg_t fbcbb_rsvd : 56;
} pi_force_bad_check_bit_b_fld_s;
} pi_force_bad_check_bit_b_u_t;
#else
typedef union pi_force_bad_check_bit_b_u {
bdrkreg_t pi_force_bad_check_bit_b_regval;
struct {
bdrkreg_t fbcbb_rsvd : 56;
bdrkreg_t fbcbb_bad_check_bit : 8;
} pi_force_bad_check_bit_b_fld_s;
} pi_force_bad_check_bit_b_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. When a counter is *
* enabled, it increments each time a DNACK reply is received. The *
* counter is cleared when any other reply is received. The register *
* is cleared when the CNT_EN bit is zero. If a DNACK reply is *
* received when the counter equals the value in the NACK_CMP *
* register, the counter is cleared, an error response is sent to the *
* CPU instead of a nack response, and the NACK_INT_A/B bit is set in *
* INT_PEND1. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_nack_cnt_a_u {
bdrkreg_t pi_nack_cnt_a_regval;
struct {
bdrkreg_t nca_nack_cnt : 20;
bdrkreg_t nca_cnt_en : 1;
bdrkreg_t nca_rsvd : 43;
} pi_nack_cnt_a_fld_s;
} pi_nack_cnt_a_u_t;
#else
typedef union pi_nack_cnt_a_u {
bdrkreg_t pi_nack_cnt_a_regval;
struct {
bdrkreg_t nca_rsvd : 43;
bdrkreg_t nca_cnt_en : 1;
bdrkreg_t nca_nack_cnt : 20;
} pi_nack_cnt_a_fld_s;
} pi_nack_cnt_a_u_t;
#endif
/************************************************************************
* *
* There is one of these registers for each CPU. When a counter is *
* enabled, it increments each time a DNACK reply is received. The *
* counter is cleared when any other reply is received. The register *
* is cleared when the CNT_EN bit is zero. If a DNACK reply is *
* received when the counter equals the value in the NACK_CMP *
* register, the counter is cleared, an error response is sent to the *
* CPU instead of a nack response, and the NACK_INT_A/B bit is set in *
* INT_PEND1. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_nack_cnt_b_u {
bdrkreg_t pi_nack_cnt_b_regval;
struct {
bdrkreg_t ncb_nack_cnt : 20;
bdrkreg_t ncb_cnt_en : 1;
bdrkreg_t ncb_rsvd : 43;
} pi_nack_cnt_b_fld_s;
} pi_nack_cnt_b_u_t;
#else
typedef union pi_nack_cnt_b_u {
bdrkreg_t pi_nack_cnt_b_regval;
struct {
bdrkreg_t ncb_rsvd : 43;
bdrkreg_t ncb_cnt_en : 1;
bdrkreg_t ncb_nack_cnt : 20;
} pi_nack_cnt_b_fld_s;
} pi_nack_cnt_b_u_t;
#endif
/************************************************************************
* *
* The setting of this register affects both CPUs on this PI. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_nack_cmp_u {
bdrkreg_t pi_nack_cmp_regval;
struct {
bdrkreg_t nc_nack_cmp : 20;
bdrkreg_t nc_rsvd : 44;
} pi_nack_cmp_fld_s;
} pi_nack_cmp_u_t;
#else
typedef union pi_nack_cmp_u {
bdrkreg_t pi_nack_cmp_regval;
struct {
bdrkreg_t nc_rsvd : 44;
bdrkreg_t nc_nack_cmp : 20;
} pi_nack_cmp_fld_s;
} pi_nack_cmp_u_t;
#endif
/************************************************************************
* *
* This register controls which errors are spooled. When a bit in *
* this register is set, the corresponding error is spooled. The *
* setting of this register affects both CPUs on this PI. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_spool_mask_u {
bdrkreg_t pi_spool_mask_regval;
struct {
bdrkreg_t sm_access_err : 1;
bdrkreg_t sm_uncached_err : 1;
bdrkreg_t sm_dir_err : 1;
bdrkreg_t sm_timeout_err : 1;
bdrkreg_t sm_poison_err : 1;
bdrkreg_t sm_nack_oflow_err : 1;
bdrkreg_t sm_rsvd : 58;
} pi_spool_mask_fld_s;
} pi_spool_mask_u_t;
#else
typedef union pi_spool_mask_u {
bdrkreg_t pi_spool_mask_regval;
struct {
bdrkreg_t sm_rsvd : 58;
bdrkreg_t sm_nack_oflow_err : 1;
bdrkreg_t sm_poison_err : 1;
bdrkreg_t sm_timeout_err : 1;
bdrkreg_t sm_dir_err : 1;
bdrkreg_t sm_uncached_err : 1;
bdrkreg_t sm_access_err : 1;
} pi_spool_mask_fld_s;
} pi_spool_mask_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. When the VALID bit is *
* zero, this register (along with SPURIOUS_HDR_1) will capture the *
* header of an incoming spurious message received from the XBar. A *
* spurious message is a message that does not match up with any of *
* the CRB entries. This is a read/write register, so it is cleared *
* by writing of all zeros. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_spurious_hdr_0_u {
bdrkreg_t pi_spurious_hdr_0_regval;
struct {
bdrkreg_t sh0_prev_valid_b : 1;
bdrkreg_t sh0_prev_valid_a : 1;
bdrkreg_t sh0_rsvd : 4;
bdrkreg_t sh0_supplemental : 11;
bdrkreg_t sh0_cmd : 8;
bdrkreg_t sh0_addr : 37;
bdrkreg_t sh0_tail : 1;
bdrkreg_t sh0_valid : 1;
} pi_spurious_hdr_0_fld_s;
} pi_spurious_hdr_0_u_t;
#else
typedef union pi_spurious_hdr_0_u {
bdrkreg_t pi_spurious_hdr_0_regval;
struct {
bdrkreg_t sh0_valid : 1;
bdrkreg_t sh0_tail : 1;
bdrkreg_t sh0_addr : 37;
bdrkreg_t sh0_cmd : 8;
bdrkreg_t sh0_supplemental : 11;
bdrkreg_t sh0_rsvd : 4;
bdrkreg_t sh0_prev_valid_a : 1;
bdrkreg_t sh0_prev_valid_b : 1;
} pi_spurious_hdr_0_fld_s;
} pi_spurious_hdr_0_u_t;
#endif
/************************************************************************
* *
* This register is not cleared at reset. When the VALID bit in *
* SPURIOUS_HDR_0 is zero, this register (along with SPURIOUS_HDR_0) *
* will capture the header of an incoming spurious message received *
* from the XBar. A spurious message is a message that does not match *
* up with any of the CRB entries. This is a read/write register, so *
* it is cleared by writing of all zeros. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_spurious_hdr_1_u {
bdrkreg_t pi_spurious_hdr_1_regval;
struct {
bdrkreg_t sh1_rsvd : 53;
bdrkreg_t sh1_source : 11;
} pi_spurious_hdr_1_fld_s;
} pi_spurious_hdr_1_u_t;
#else
typedef union pi_spurious_hdr_1_u {
bdrkreg_t pi_spurious_hdr_1_regval;
struct {
bdrkreg_t sh1_source : 11;
bdrkreg_t sh1_rsvd : 53;
} pi_spurious_hdr_1_fld_s;
} pi_spurious_hdr_1_u_t;
#endif
/************************************************************************
* *
* Description: This register controls the injection of errors in *
* outbound SysAD transfers. When a write sets a bit in this *
* register, the PI logic is "armed" to inject that error. At the *
* first transfer of the specified type, the error is injected and *
* the bit in this register is cleared. Writing to this register does *
* not cause a transaction to occur. A bit in this register will *
* remain set until a transaction of the specified type occurs as a *
* result of normal system activity. This register can be polled to *
* determine if an error has been injected or is still "armed". *
* This register does not control injection of data quality bad *
* indicator on a data cycle. This type of error can be created by *
* reading from a memory location that has an uncorrectable ECC *
* error. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_err_inject_u {
bdrkreg_t pi_err_inject_regval;
struct {
bdrkreg_t ei_cmd_syscmd_par_a : 1;
bdrkreg_t ei_data_syscmd_par_a : 1;
bdrkreg_t ei_cmd_sysad_corecc_a : 1;
bdrkreg_t ei_data_sysad_corecc_a : 1;
bdrkreg_t ei_cmd_sysad_uncecc_a : 1;
bdrkreg_t ei_data_sysad_uncecc_a : 1;
bdrkreg_t ei_sysresp_par_a : 1;
bdrkreg_t ei_reserved_1 : 25;
bdrkreg_t ei_cmd_syscmd_par_b : 1;
bdrkreg_t ei_data_syscmd_par_b : 1;
bdrkreg_t ei_cmd_sysad_corecc_b : 1;
bdrkreg_t ei_data_sysad_corecc_b : 1;
bdrkreg_t ei_cmd_sysad_uncecc_b : 1;
bdrkreg_t ei_data_sysad_uncecc_b : 1;
bdrkreg_t ei_sysresp_par_b : 1;
bdrkreg_t ei_reserved : 25;
} pi_err_inject_fld_s;
} pi_err_inject_u_t;
#else
typedef union pi_err_inject_u {
bdrkreg_t pi_err_inject_regval;
struct {
bdrkreg_t ei_reserved : 25;
bdrkreg_t ei_sysresp_par_b : 1;
bdrkreg_t ei_data_sysad_uncecc_b : 1;
bdrkreg_t ei_cmd_sysad_uncecc_b : 1;
bdrkreg_t ei_data_sysad_corecc_b : 1;
bdrkreg_t ei_cmd_sysad_corecc_b : 1;
bdrkreg_t ei_data_syscmd_par_b : 1;
bdrkreg_t ei_cmd_syscmd_par_b : 1;
bdrkreg_t ei_reserved_1 : 25;
bdrkreg_t ei_sysresp_par_a : 1;
bdrkreg_t ei_data_sysad_uncecc_a : 1;
bdrkreg_t ei_cmd_sysad_uncecc_a : 1;
bdrkreg_t ei_data_sysad_corecc_a : 1;
bdrkreg_t ei_cmd_sysad_corecc_a : 1;
bdrkreg_t ei_data_syscmd_par_a : 1;
bdrkreg_t ei_cmd_syscmd_par_a : 1;
} pi_err_inject_fld_s;
} pi_err_inject_u_t;
#endif
/************************************************************************
* *
* This Read/Write location determines at what point the TRex+ is *
* stopped from issuing requests, based on the number of entries in *
* the incoming reply FIFO. When the number of entries in the Reply *
* FIFO is greater than the value of this register, the PI will *
* deassert both SysWrRdy and SysRdRdy to both processors. The Reply *
* FIFO has a depth of 0x3F entries, so setting this register to 0x3F *
* effectively disables this feature, allowing requests to be issued *
* always. Setting this register to 0x00 effectively lowers the *
* TRex+'s priority below the reply FIFO, disabling TRex+ requests *
* any time there is an entry waiting in the incoming FIFO.This *
* register is in its own 64KB page so that it can be mapped to user *
* space. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_reply_level_u {
bdrkreg_t pi_reply_level_regval;
struct {
bdrkreg_t rl_reply_level : 6;
bdrkreg_t rl_rsvd : 58;
} pi_reply_level_fld_s;
} pi_reply_level_u_t;
#else
typedef union pi_reply_level_u {
bdrkreg_t pi_reply_level_regval;
struct {
bdrkreg_t rl_rsvd : 58;
bdrkreg_t rl_reply_level : 6;
} pi_reply_level_fld_s;
} pi_reply_level_u_t;
#endif
/************************************************************************
* *
* This register is used to change the graphics credit counter *
* operation from "Doubleword" mode to "Transaction" mode. This *
* register is in its own 64KB page so that it can be mapped to user *
* space. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_gfx_credit_mode_u {
bdrkreg_t pi_gfx_credit_mode_regval;
struct {
bdrkreg_t gcm_trans_mode : 1;
bdrkreg_t gcm_rsvd : 63;
} pi_gfx_credit_mode_fld_s;
} pi_gfx_credit_mode_u_t;
#else
typedef union pi_gfx_credit_mode_u {
bdrkreg_t pi_gfx_credit_mode_regval;
struct {
bdrkreg_t gcm_rsvd : 63;
bdrkreg_t gcm_trans_mode : 1;
} pi_gfx_credit_mode_fld_s;
} pi_gfx_credit_mode_u_t;
#endif
/************************************************************************
* *
* This location contains a 55-bit read/write counter that wraps to *
* zero when the maximum value is reached. This counter is *
* incremented at each rising edge of the global clock (GCLK). This *
* register is in its own 64KB page so that it can be mapped to user *
* space. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_rt_counter_u {
bdrkreg_t pi_rt_counter_regval;
struct {
bdrkreg_t rc_count : 55;
bdrkreg_t rc_rsvd : 9;
} pi_rt_counter_fld_s;
} pi_rt_counter_u_t;
#else
typedef union pi_rt_counter_u {
bdrkreg_t pi_rt_counter_regval;
struct {
bdrkreg_t rc_rsvd : 9;
bdrkreg_t rc_count : 55;
} pi_rt_counter_fld_s;
} pi_rt_counter_u_t;
#endif
/************************************************************************
* *
* This register controls the performance counters for one CPU. *
* There are two counters for each CPU. Each counter can be *
* configured to count a variety of events. The performance counter *
* registers for each processor are in their own 64KB page so that *
* they can be mapped to user space. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_perf_cntl_a_u {
bdrkreg_t pi_perf_cntl_a_regval;
struct {
bdrkreg_t pca_cntr_0_select : 28;
bdrkreg_t pca_cntr_0_mode : 3;
bdrkreg_t pca_cntr_0_enable : 1;
bdrkreg_t pca_cntr_1_select : 28;
bdrkreg_t pca_cntr_1_mode : 3;
bdrkreg_t pca_cntr_1_enable : 1;
} pi_perf_cntl_a_fld_s;
} pi_perf_cntl_a_u_t;
#else
typedef union pi_perf_cntl_a_u {
bdrkreg_t pi_perf_cntl_a_regval;
struct {
bdrkreg_t pca_cntr_1_enable : 1;
bdrkreg_t pca_cntr_1_mode : 3;
bdrkreg_t pca_cntr_1_select : 28;
bdrkreg_t pca_cntr_0_enable : 1;
bdrkreg_t pca_cntr_0_mode : 3;
bdrkreg_t pca_cntr_0_select : 28;
} pi_perf_cntl_a_fld_s;
} pi_perf_cntl_a_u_t;
#endif
/************************************************************************
* *
* This register accesses the performance counter 0 for each CPU. *
* Each performance counter is 40-bits wide. On overflow, It wraps to *
* zero, sets the overflow bit in this register, and sets the *
* PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_perf_cntr0_a_u {
bdrkreg_t pi_perf_cntr0_a_regval;
struct {
bdrkreg_t pca_count_value : 40;
bdrkreg_t pca_overflow : 1;
bdrkreg_t pca_rsvd : 23;
} pi_perf_cntr0_a_fld_s;
} pi_perf_cntr0_a_u_t;
#else
typedef union pi_perf_cntr0_a_u {
bdrkreg_t pi_perf_cntr0_a_regval;
struct {
bdrkreg_t pca_rsvd : 23;
bdrkreg_t pca_overflow : 1;
bdrkreg_t pca_count_value : 40;
} pi_perf_cntr0_a_fld_s;
} pi_perf_cntr0_a_u_t;
#endif
/************************************************************************
* *
* This register accesses the performance counter 1for each CPU. *
* Each performance counter is 40-bits wide. On overflow, It wraps to *
* zero, sets the overflow bit in this register, and sets the *
* PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_perf_cntr1_a_u {
bdrkreg_t pi_perf_cntr1_a_regval;
struct {
bdrkreg_t pca_count_value : 40;
bdrkreg_t pca_overflow : 1;
bdrkreg_t pca_rsvd : 23;
} pi_perf_cntr1_a_fld_s;
} pi_perf_cntr1_a_u_t;
#else
typedef union pi_perf_cntr1_a_u {
bdrkreg_t pi_perf_cntr1_a_regval;
struct {
bdrkreg_t pca_rsvd : 23;
bdrkreg_t pca_overflow : 1;
bdrkreg_t pca_count_value : 40;
} pi_perf_cntr1_a_fld_s;
} pi_perf_cntr1_a_u_t;
#endif
/************************************************************************
* *
* This register controls the performance counters for one CPU. *
* There are two counters for each CPU. Each counter can be *
* configured to count a variety of events. The performance counter *
* registers for each processor are in their own 64KB page so that *
* they can be mapped to user space. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_perf_cntl_b_u {
bdrkreg_t pi_perf_cntl_b_regval;
struct {
bdrkreg_t pcb_cntr_0_select : 28;
bdrkreg_t pcb_cntr_0_mode : 3;
bdrkreg_t pcb_cntr_0_enable : 1;
bdrkreg_t pcb_cntr_1_select : 28;
bdrkreg_t pcb_cntr_1_mode : 3;
bdrkreg_t pcb_cntr_1_enable : 1;
} pi_perf_cntl_b_fld_s;
} pi_perf_cntl_b_u_t;
#else
typedef union pi_perf_cntl_b_u {
bdrkreg_t pi_perf_cntl_b_regval;
struct {
bdrkreg_t pcb_cntr_1_enable : 1;
bdrkreg_t pcb_cntr_1_mode : 3;
bdrkreg_t pcb_cntr_1_select : 28;
bdrkreg_t pcb_cntr_0_enable : 1;
bdrkreg_t pcb_cntr_0_mode : 3;
bdrkreg_t pcb_cntr_0_select : 28;
} pi_perf_cntl_b_fld_s;
} pi_perf_cntl_b_u_t;
#endif
/************************************************************************
* *
* This register accesses the performance counter 0 for each CPU. *
* Each performance counter is 40-bits wide. On overflow, It wraps to *
* zero, sets the overflow bit in this register, and sets the *
* PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_perf_cntr0_b_u {
bdrkreg_t pi_perf_cntr0_b_regval;
struct {
bdrkreg_t pcb_count_value : 40;
bdrkreg_t pcb_overflow : 1;
bdrkreg_t pcb_rsvd : 23;
} pi_perf_cntr0_b_fld_s;
} pi_perf_cntr0_b_u_t;
#else
typedef union pi_perf_cntr0_b_u {
bdrkreg_t pi_perf_cntr0_b_regval;
struct {
bdrkreg_t pcb_rsvd : 23;
bdrkreg_t pcb_overflow : 1;
bdrkreg_t pcb_count_value : 40;
} pi_perf_cntr0_b_fld_s;
} pi_perf_cntr0_b_u_t;
#endif
/************************************************************************
* *
* This register accesses the performance counter 1for each CPU. *
* Each performance counter is 40-bits wide. On overflow, It wraps to *
* zero, sets the overflow bit in this register, and sets the *
* PERF_CNTR_OFLOW bit in the INT_PEND1 register. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union pi_perf_cntr1_b_u {
bdrkreg_t pi_perf_cntr1_b_regval;
struct {
bdrkreg_t pcb_count_value : 40;
bdrkreg_t pcb_overflow : 1;
bdrkreg_t pcb_rsvd : 23;
} pi_perf_cntr1_b_fld_s;
} pi_perf_cntr1_b_u_t;
#else
typedef union pi_perf_cntr1_b_u {
bdrkreg_t pi_perf_cntr1_b_regval;
struct {
bdrkreg_t pcb_rsvd : 23;
bdrkreg_t pcb_overflow : 1;
bdrkreg_t pcb_count_value : 40;
} pi_perf_cntr1_b_fld_s;
} pi_perf_cntr1_b_u_t;
#endif
#endif /* __ASSEMBLY__ */
/************************************************************************
* *
* MAKE ALL ADDITIONS AFTER THIS LINE *
* *
************************************************************************/
#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
#endif /* _ASM_IA64_SN_SN1_HUBPI_H */