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hubio.h：源码内容

/* $Id$
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
/************************************************************************
* *
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! *
* *
* This file is created by an automated script. Any (minimal) changes *
* made manually to this file should be made with care. *
* *
* MAKE ALL ADDITIONS TO THE END OF THIS FILE *
* *
************************************************************************/
#ifndef _ASM_IA64_SN_SN1_HUBIO_H
#define _ASM_IA64_SN_SN1_HUBIO_H
#define IIO_WID 0x00400000 /*
* Crosstalk Widget
* Identification This
* register is also
* accessible from
* Crosstalk at
* address 0x0.
*/
#define IIO_WSTAT 0x00400008 /*
* Crosstalk Widget
* Status
*/
#define IIO_WCR 0x00400020 /*
* Crosstalk Widget
* Control Register
*/
#define IIO_ILAPR 0x00400100 /*
* IO Local Access
* Protection Register
*/
#define IIO_ILAPO 0x00400108 /*
* IO Local Access
* Protection Override
*/
#define IIO_IOWA 0x00400110 /*
* IO Outbound Widget
* Access
*/
#define IIO_IIWA 0x00400118 /*
* IO Inbound Widget
* Access
*/
#define IIO_IIDEM 0x00400120 /*
* IO Inbound Device
* Error Mask
*/
#define IIO_ILCSR 0x00400128 /*
* IO LLP Control and
* Status Register
*/
#define IIO_ILLR 0x00400130 /* IO LLP Log Register */
#define IIO_IIDSR 0x00400138 /*
* IO Interrupt
* Destination
*/
#define IIO_IGFX0 0x00400140 /*
* IO Graphics
* Node-Widget Map 0
*/
#define IIO_IGFX1 0x00400148 /*
* IO Graphics
* Node-Widget Map 1
*/
#define IIO_ISCR0 0x00400150 /*
* IO Scratch Register
* 0
*/
#define IIO_ISCR1 0x00400158 /*
* IO Scratch Register
* 1
*/
#define IIO_ITTE1 0x00400160 /*
* IO Translation
* Table Entry 1
*/
#define IIO_ITTE2 0x00400168 /*
* IO Translation
* Table Entry 2
*/
#define IIO_ITTE3 0x00400170 /*
* IO Translation
* Table Entry 3
*/
#define IIO_ITTE4 0x00400178 /*
* IO Translation
* Table Entry 4
*/
#define IIO_ITTE5 0x00400180 /*
* IO Translation
* Table Entry 5
*/
#define IIO_ITTE6 0x00400188 /*
* IO Translation
* Table Entry 6
*/
#define IIO_ITTE7 0x00400190 /*
* IO Translation
* Table Entry 7
*/
#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
#define IIO_IXCC 0x004001E0 /*
* IO Crosstalk Credit
* Count Timeout
*/
#define IIO_IMEM 0x004001E8 /*
* IO Miscellaneous
* Error Mask
*/
#define IIO_IXTT 0x004001F0 /*
* IO Crosstalk
* Timeout Threshold
*/
#define IIO_IECLR 0x004001F8 /*
* IO Error Clear
* Register
*/
#define IIO_IBCR 0x00400200 /*
* IO BTE Control
* Register
*/
#define IIO_IXSM 0x00400208 /*
* IO Crosstalk
* Spurious Message
*/
#define IIO_IXSS 0x00400210 /*
* IO Crosstalk
* Spurious Sideband
*/
#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
#define IIO_IIEPH1 0x00400220 /*
* IO Incoming Error
* Packet Header, Part
* 1
*/
#define IIO_IIEPH2 0x00400228 /*
* IO Incoming Error
* Packet Header, Part
* 2
*/
#define IIO_IPCA 0x00400300 /*
* IO PRB Counter
* Adjust
*/
#define IIO_IPRTE0 0x00400308 /*
* IO PIO Read Address
* Table Entry 0
*/
#define IIO_IPRTE1 0x00400310 /*
* IO PIO Read Address
* Table Entry 1
*/
#define IIO_IPRTE2 0x00400318 /*
* IO PIO Read Address
* Table Entry 2
*/
#define IIO_IPRTE3 0x00400320 /*
* IO PIO Read Address
* Table Entry 3
*/
#define IIO_IPRTE4 0x00400328 /*
* IO PIO Read Address
* Table Entry 4
*/
#define IIO_IPRTE5 0x00400330 /*
* IO PIO Read Address
* Table Entry 5
*/
#define IIO_IPRTE6 0x00400338 /*
* IO PIO Read Address
* Table Entry 6
*/
#define IIO_IPRTE7 0x00400340 /*
* IO PIO Read Address
* Table Entry 7
*/
#define IIO_IPDR 0x00400388 /*
* IO PIO Deallocation
* Register
*/
#define IIO_ICDR 0x00400390 /*
* IO CRB Entry
* Deallocation
* Register
*/
#define IIO_IFDR 0x00400398 /*
* IO IOQ FIFO Depth
* Register
*/
#define IIO_IIAP 0x004003A0 /*
* IO IIQ Arbitration
* Parameters
*/
#define IIO_ICMR 0x004003A8 /*
* IO CRB Management
* Register
*/
#define IIO_ICCR 0x004003B0 /*
* IO CRB Control
* Register
*/
#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
#define IIO_ICTP 0x004003C0 /*
* IO CRB Timeout
* Prescalar
*/
#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
#define IIO_ICRB1_A 0x00400420 /* IO CRB Entry 1_A */
#define IIO_ICRB1_B 0x00400428 /* IO CRB Entry 1_B */
#define IIO_ICRB1_C 0x00400430 /* IO CRB Entry 1_C */
#define IIO_ICRB1_D 0x00400438 /* IO CRB Entry 1_D */
#define IIO_ICRB2_A 0x00400440 /* IO CRB Entry 2_A */
#define IIO_ICRB2_B 0x00400448 /* IO CRB Entry 2_B */
#define IIO_ICRB2_C 0x00400450 /* IO CRB Entry 2_C */
#define IIO_ICRB2_D 0x00400458 /* IO CRB Entry 2_D */
#define IIO_ICRB3_A 0x00400460 /* IO CRB Entry 3_A */
#define IIO_ICRB3_B 0x00400468 /* IO CRB Entry 3_B */
#define IIO_ICRB3_C 0x00400470 /* IO CRB Entry 3_C */
#define IIO_ICRB3_D 0x00400478 /* IO CRB Entry 3_D */
#define IIO_ICRB4_A 0x00400480 /* IO CRB Entry 4_A */
#define IIO_ICRB4_B 0x00400488 /* IO CRB Entry 4_B */
#define IIO_ICRB4_C 0x00400490 /* IO CRB Entry 4_C */
#define IIO_ICRB4_D 0x00400498 /* IO CRB Entry 4_D */
#define IIO_ICRB5_A 0x004004A0 /* IO CRB Entry 5_A */
#define IIO_ICRB5_B 0x004004A8 /* IO CRB Entry 5_B */
#define IIO_ICRB5_C 0x004004B0 /* IO CRB Entry 5_C */
#define IIO_ICRB5_D 0x004004B8 /* IO CRB Entry 5_D */
#define IIO_ICRB6_A 0x004004C0 /* IO CRB Entry 6_A */
#define IIO_ICRB6_B 0x004004C8 /* IO CRB Entry 6_B */
#define IIO_ICRB6_C 0x004004D0 /* IO CRB Entry 6_C */
#define IIO_ICRB6_D 0x004004D8 /* IO CRB Entry 6_D */
#define IIO_ICRB7_A 0x004004E0 /* IO CRB Entry 7_A */
#define IIO_ICRB7_B 0x004004E8 /* IO CRB Entry 7_B */
#define IIO_ICRB7_C 0x004004F0 /* IO CRB Entry 7_C */
#define IIO_ICRB7_D 0x004004F8 /* IO CRB Entry 7_D */
#define IIO_ICRB8_A 0x00400500 /* IO CRB Entry 8_A */
#define IIO_ICRB8_B 0x00400508 /* IO CRB Entry 8_B */
#define IIO_ICRB8_C 0x00400510 /* IO CRB Entry 8_C */
#define IIO_ICRB8_D 0x00400518 /* IO CRB Entry 8_D */
#define IIO_ICRB9_A 0x00400520 /* IO CRB Entry 9_A */
#define IIO_ICRB9_B 0x00400528 /* IO CRB Entry 9_B */
#define IIO_ICRB9_C 0x00400530 /* IO CRB Entry 9_C */
#define IIO_ICRB9_D 0x00400538 /* IO CRB Entry 9_D */
#define IIO_ICRBA_A 0x00400540 /* IO CRB Entry A_A */
#define IIO_ICRBA_B 0x00400548 /* IO CRB Entry A_B */
#define IIO_ICRBA_C 0x00400550 /* IO CRB Entry A_C */
#define IIO_ICRBA_D 0x00400558 /* IO CRB Entry A_D */
#define IIO_ICRBB_A 0x00400560 /* IO CRB Entry B_A */
#define IIO_ICRBB_B 0x00400568 /* IO CRB Entry B_B */
#define IIO_ICRBB_C 0x00400570 /* IO CRB Entry B_C */
#define IIO_ICRBB_D 0x00400578 /* IO CRB Entry B_D */
#define IIO_ICRBC_A 0x00400580 /* IO CRB Entry C_A */
#define IIO_ICRBC_B 0x00400588 /* IO CRB Entry C_B */
#define IIO_ICRBC_C 0x00400590 /* IO CRB Entry C_C */
#define IIO_ICRBC_D 0x00400598 /* IO CRB Entry C_D */
#define IIO_ICRBD_A 0x004005A0 /* IO CRB Entry D_A */
#define IIO_ICRBD_B 0x004005A8 /* IO CRB Entry D_B */
#define IIO_ICRBD_C 0x004005B0 /* IO CRB Entry D_C */
#define IIO_ICRBD_D 0x004005B8 /* IO CRB Entry D_D */
#define IIO_ICRBE_A 0x004005C0 /* IO CRB Entry E_A */
#define IIO_ICRBE_B 0x004005C8 /* IO CRB Entry E_B */
#define IIO_ICRBE_C 0x004005D0 /* IO CRB Entry E_C */
#define IIO_ICRBE_D 0x004005D8 /* IO CRB Entry E_D */
#define IIO_ICSML 0x00400600 /*
* IO CRB Spurious
* Message Low
*/
#define IIO_ICSMH 0x00400608 /*
* IO CRB Spurious
* Message High
*/
#define IIO_IDBSS 0x00400610 /*
* IO Debug Submenu
* Select
*/
#define IIO_IBLS0 0x00410000 /*
* IO BTE Length
* Status 0
*/
#define IIO_IBSA0 0x00410008 /*
* IO BTE Source
* Address 0
*/
#define IIO_IBDA0 0x00410010 /*
* IO BTE Destination
* Address 0
*/
#define IIO_IBCT0 0x00410018 /*
* IO BTE Control
* Terminate 0
*/
#define IIO_IBNA0 0x00410020 /*
* IO BTE Notification
* Address 0
*/
#define IIO_IBIA0 0x00410028 /*
* IO BTE Interrupt
* Address 0
*/
#define IIO_IBLS1 0x00420000 /*
* IO BTE Length
* Status 1
*/
#define IIO_IBSA1 0x00420008 /*
* IO BTE Source
* Address 1
*/
#define IIO_IBDA1 0x00420010 /*
* IO BTE Destination
* Address 1
*/
#define IIO_IBCT1 0x00420018 /*
* IO BTE Control
* Terminate 1
*/
#define IIO_IBNA1 0x00420020 /*
* IO BTE Notification
* Address 1
*/
#define IIO_IBIA1 0x00420028 /*
* IO BTE Interrupt
* Address 1
*/
#define IIO_IPCR 0x00430000 /*
* IO Performance
* Control
*/
#define IIO_IPPR 0x00430008 /*
* IO Performance
* Profiling
*/
#ifndef __ASSEMBLY__
/************************************************************************
* *
* Description: This register echoes some information from the *
* LB_REV_ID register. It is available through Crosstalk as described *
* above. The REV_NUM and MFG_NUM fields receive their values from *
* the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
* The PART_NUM field's value is the Crosstalk device ID number that *
* Steve Miller assigned to the Bedrock chip. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_wid_u {
bdrkreg_t ii_wid_regval;
struct {
bdrkreg_t w_rsvd_1 : 1;
bdrkreg_t w_mfg_num : 11;
bdrkreg_t w_part_num : 16;
bdrkreg_t w_rev_num : 4;
bdrkreg_t w_rsvd : 32;
} ii_wid_fld_s;
} ii_wid_u_t;
#else
typedef union ii_wid_u {
bdrkreg_t ii_wid_regval;
struct {
bdrkreg_t w_rsvd : 32;
bdrkreg_t w_rev_num : 4;
bdrkreg_t w_part_num : 16;
bdrkreg_t w_mfg_num : 11;
bdrkreg_t w_rsvd_1 : 1;
} ii_wid_fld_s;
} ii_wid_u_t;
#endif
/************************************************************************
* *
* The fields in this register are set upon detection of an error *
* and cleared by various mechanisms, as explained in the *
* description. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_wstat_u {
bdrkreg_t ii_wstat_regval;
struct {
bdrkreg_t w_pending : 4;
bdrkreg_t w_xt_crd_to : 1;
bdrkreg_t w_xt_tail_to : 1;
bdrkreg_t w_rsvd_3 : 3;
bdrkreg_t w_tx_mx_rty : 1;
bdrkreg_t w_rsvd_2 : 6;
bdrkreg_t w_llp_tx_cnt : 8;
bdrkreg_t w_rsvd_1 : 8;
bdrkreg_t w_crazy : 1;
bdrkreg_t w_rsvd : 31;
} ii_wstat_fld_s;
} ii_wstat_u_t;
#else
typedef union ii_wstat_u {
bdrkreg_t ii_wstat_regval;
struct {
bdrkreg_t w_rsvd : 31;
bdrkreg_t w_crazy : 1;
bdrkreg_t w_rsvd_1 : 8;
bdrkreg_t w_llp_tx_cnt : 8;
bdrkreg_t w_rsvd_2 : 6;
bdrkreg_t w_tx_mx_rty : 1;
bdrkreg_t w_rsvd_3 : 3;
bdrkreg_t w_xt_tail_to : 1;
bdrkreg_t w_xt_crd_to : 1;
bdrkreg_t w_pending : 4;
} ii_wstat_fld_s;
} ii_wstat_u_t;
#endif
/************************************************************************
* *
* Description: This is a read-write enabled register. It controls *
* various aspects of the Crosstalk flow control. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_wcr_u {
bdrkreg_t ii_wcr_regval;
struct {
bdrkreg_t w_wid : 4;
bdrkreg_t w_tag : 1;
bdrkreg_t w_rsvd_1 : 8;
bdrkreg_t w_dst_crd : 3;
bdrkreg_t w_f_bad_pkt : 1;
bdrkreg_t w_dir_con : 1;
bdrkreg_t w_e_thresh : 5;
bdrkreg_t w_rsvd : 41;
} ii_wcr_fld_s;
} ii_wcr_u_t;
#else
typedef union ii_wcr_u {
bdrkreg_t ii_wcr_regval;
struct {
bdrkreg_t w_rsvd : 41;
bdrkreg_t w_e_thresh : 5;
bdrkreg_t w_dir_con : 1;
bdrkreg_t w_f_bad_pkt : 1;
bdrkreg_t w_dst_crd : 3;
bdrkreg_t w_rsvd_1 : 8;
bdrkreg_t w_tag : 1;
bdrkreg_t w_wid : 4;
} ii_wcr_fld_s;
} ii_wcr_u_t;
#endif
/************************************************************************
* *
* Description: This register's value is a bit vector that guards *
* access to local registers within the II as well as to external *
* Crosstalk widgets. Each bit in the register corresponds to a *
* particular region in the system; a region consists of one, two or *
* four nodes (depending on the value of the REGION_SIZE field in the *
* LB_REV_ID register, which is documented in Section 8.3.1.1). The *
* protection provided by this register applies to PIO read *
* operations as well as PIO write operations. The II will perform a *
* PIO read or write request only if the bit for the requestor's *
* region is set; otherwise, the II will not perform the requested *
* operation and will return an error response. When a PIO read or *
* write request targets an external Crosstalk widget, then not only *
* must the bit for the requestor's region be set in the ILAPR, but *
* also the target widget's bit in the IOWA register must be set in *
* order for the II to perform the requested operation; otherwise, *
* the II will return an error response. Hence, the protection *
* provided by the IOWA register supplements the protection provided *
* by the ILAPR for requests that target external Crosstalk widgets. *
* This register itself can be accessed only by the nodes whose *
* region ID bits are enabled in this same register. It can also be *
* accessed through the IAlias space by the local processors. *
* The reset value of this register allows access by all nodes. *
* *
************************************************************************/
typedef union ii_ilapr_u {
bdrkreg_t ii_ilapr_regval;
struct {
bdrkreg_t i_region : 64;
} ii_ilapr_fld_s;
} ii_ilapr_u_t;
/************************************************************************
* *
* Description: A write to this register of the 64-bit value *
* "SGIrules" in ASCII, will cause the bit in the ILAPR register *
* corresponding to the region of the requestor to be set (allow *
* access). A write of any other value will be ignored. Access *
* protection for this register is "SGIrules". *
* This register can also be accessed through the IAlias space. *
* However, this access will not change the access permissions in the *
* ILAPR. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_ilapo_u {
bdrkreg_t ii_ilapo_regval;
struct {
bdrkreg_t i_io_ovrride : 9;
bdrkreg_t i_rsvd : 55;
} ii_ilapo_fld_s;
} ii_ilapo_u_t;
#else
typedef union ii_ilapo_u {
bdrkreg_t ii_ilapo_regval;
struct {
bdrkreg_t i_rsvd : 55;
bdrkreg_t i_io_ovrride : 9;
} ii_ilapo_fld_s;
} ii_ilapo_u_t;
#endif
/************************************************************************
* *
* This register qualifies all the PIO and Graphics writes launched *
* from the Bedrock towards a widget. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iowa_u {
bdrkreg_t ii_iowa_regval;
struct {
bdrkreg_t i_w0_oac : 1;
bdrkreg_t i_rsvd_1 : 7;
bdrkreg_t i_wx_oac : 8;
bdrkreg_t i_rsvd : 48;
} ii_iowa_fld_s;
} ii_iowa_u_t;
#else
typedef union ii_iowa_u {
bdrkreg_t ii_iowa_regval;
struct {
bdrkreg_t i_rsvd : 48;
bdrkreg_t i_wx_oac : 8;
bdrkreg_t i_rsvd_1 : 7;
bdrkreg_t i_w0_oac : 1;
} ii_iowa_fld_s;
} ii_iowa_u_t;
#endif
/************************************************************************
* *
* Description: This register qualifies all the requests launched *
* from a widget towards the Bedrock. This register is intended to be *
* used by software in case of misbehaving widgets. *
* *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iiwa_u {
bdrkreg_t ii_iiwa_regval;
struct {
bdrkreg_t i_w0_iac : 1;
bdrkreg_t i_rsvd_1 : 7;
bdrkreg_t i_wx_iac : 8;
bdrkreg_t i_rsvd : 48;
} ii_iiwa_fld_s;
} ii_iiwa_u_t;
#else
typedef union ii_iiwa_u {
bdrkreg_t ii_iiwa_regval;
struct {
bdrkreg_t i_rsvd : 48;
bdrkreg_t i_wx_iac : 8;
bdrkreg_t i_rsvd_1 : 7;
bdrkreg_t i_w0_iac : 1;
} ii_iiwa_fld_s;
} ii_iiwa_u_t;
#endif
/************************************************************************
* *
* Description: This register qualifies all the operations launched *
* from a widget towards the Bedrock. It allows individual access *
* control for up to 8 devices per widget. A device refers to *
* individual DMA master hosted by a widget. *
* The bits in each field of this register are cleared by the Bedrock *
* upon detection of an error which requires the device to be *
* disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
* Crosstalk). Whether or not a device has access rights to this *
* Bedrock is determined by an AND of the device enable bit in the *
* appropriate field of this register and the corresponding bit in *
* the Wx_IAC field (for the widget which this device belongs to). *
* The bits in this field are set by writing a 1 to them. Incoming *
* replies from Crosstalk are not subject to this access control *
* mechanism. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iidem_u {
bdrkreg_t ii_iidem_regval;
struct {
bdrkreg_t i_w8_dxs : 8;
bdrkreg_t i_w9_dxs : 8;
bdrkreg_t i_wa_dxs : 8;
bdrkreg_t i_wb_dxs : 8;
bdrkreg_t i_wc_dxs : 8;
bdrkreg_t i_wd_dxs : 8;
bdrkreg_t i_we_dxs : 8;
bdrkreg_t i_wf_dxs : 8;
} ii_iidem_fld_s;
} ii_iidem_u_t;
#else
typedef union ii_iidem_u {
bdrkreg_t ii_iidem_regval;
struct {
bdrkreg_t i_wf_dxs : 8;
bdrkreg_t i_we_dxs : 8;
bdrkreg_t i_wd_dxs : 8;
bdrkreg_t i_wc_dxs : 8;
bdrkreg_t i_wb_dxs : 8;
bdrkreg_t i_wa_dxs : 8;
bdrkreg_t i_w9_dxs : 8;
bdrkreg_t i_w8_dxs : 8;
} ii_iidem_fld_s;
} ii_iidem_u_t;
#endif
/************************************************************************
* *
* This register contains the various programmable fields necessary *
* for controlling and observing the LLP signals. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_ilcsr_u {
bdrkreg_t ii_ilcsr_regval;
struct {
bdrkreg_t i_nullto : 6;
bdrkreg_t i_rsvd_4 : 2;
bdrkreg_t i_wrmrst : 1;
bdrkreg_t i_rsvd_3 : 1;
bdrkreg_t i_llp_en : 1;
bdrkreg_t i_bm8 : 1;
bdrkreg_t i_llp_stat : 2;
bdrkreg_t i_remote_power : 1;
bdrkreg_t i_rsvd_2 : 1;
bdrkreg_t i_maxrtry : 10;
bdrkreg_t i_d_avail_sel : 2;
bdrkreg_t i_rsvd_1 : 4;
bdrkreg_t i_maxbrst : 10;
bdrkreg_t i_rsvd : 22;
} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;
#else
typedef union ii_ilcsr_u {
bdrkreg_t ii_ilcsr_regval;
struct {
bdrkreg_t i_rsvd : 22;
bdrkreg_t i_maxbrst : 10;
bdrkreg_t i_rsvd_1 : 4;
bdrkreg_t i_d_avail_sel : 2;
bdrkreg_t i_maxrtry : 10;
bdrkreg_t i_rsvd_2 : 1;
bdrkreg_t i_remote_power : 1;
bdrkreg_t i_llp_stat : 2;
bdrkreg_t i_bm8 : 1;
bdrkreg_t i_llp_en : 1;
bdrkreg_t i_rsvd_3 : 1;
bdrkreg_t i_wrmrst : 1;
bdrkreg_t i_rsvd_4 : 2;
bdrkreg_t i_nullto : 6;
} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;
#endif
/************************************************************************
* *
* This is simply a status registers that monitors the LLP error *
* rate. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_illr_u {
bdrkreg_t ii_illr_regval;
struct {
bdrkreg_t i_sn_cnt : 16;
bdrkreg_t i_cb_cnt : 16;
bdrkreg_t i_rsvd : 32;
} ii_illr_fld_s;
} ii_illr_u_t;
#else
typedef union ii_illr_u {
bdrkreg_t ii_illr_regval;
struct {
bdrkreg_t i_rsvd : 32;
bdrkreg_t i_cb_cnt : 16;
bdrkreg_t i_sn_cnt : 16;
} ii_illr_fld_s;
} ii_illr_u_t;
#endif
/************************************************************************
* *
* Description: All II-detected non-BTE error interrupts are *
* specified via this register. *
* NOTE: The PI interrupt register address is hardcoded in the II. If *
* PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
* packet) to address offset 0x0180_0090 within the local register *
* address space of PI0 on the node specified by the NODE field. If *
* PI_ID==1, then the II sends the interrupt request to address *
* offset 0x01A0_0090 within the local register address space of PI1 *
* on the node specified by the NODE field. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iidsr_u {
bdrkreg_t ii_iidsr_regval;
struct {
bdrkreg_t i_level : 7;
bdrkreg_t i_rsvd_4 : 1;
bdrkreg_t i_pi_id : 1;
bdrkreg_t i_node : 8;
bdrkreg_t i_rsvd_3 : 7;
bdrkreg_t i_enable : 1;
bdrkreg_t i_rsvd_2 : 3;
bdrkreg_t i_int_sent : 1;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_pi0_forward_int : 1;
bdrkreg_t i_pi1_forward_int : 1;
bdrkreg_t i_rsvd : 30;
} ii_iidsr_fld_s;
} ii_iidsr_u_t;
#else
typedef union ii_iidsr_u {
bdrkreg_t ii_iidsr_regval;
struct {
bdrkreg_t i_rsvd : 30;
bdrkreg_t i_pi1_forward_int : 1;
bdrkreg_t i_pi0_forward_int : 1;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_int_sent : 1;
bdrkreg_t i_rsvd_2 : 3;
bdrkreg_t i_enable : 1;
bdrkreg_t i_rsvd_3 : 7;
bdrkreg_t i_node : 8;
bdrkreg_t i_pi_id : 1;
bdrkreg_t i_rsvd_4 : 1;
bdrkreg_t i_level : 7;
} ii_iidsr_fld_s;
} ii_iidsr_u_t;
#endif
/************************************************************************
* *
* There are two instances of this register. This register is used *
* for matching up the incoming responses from the graphics widget to *
* the processor that initiated the graphics operation. The *
* write-responses are converted to graphics credits and returned to *
* the processor so that the processor interface can manage the flow *
* control. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_igfx0_u {
bdrkreg_t ii_igfx0_regval;
struct {
bdrkreg_t i_w_num : 4;
bdrkreg_t i_pi_id : 1;
bdrkreg_t i_n_num : 8;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_p_num : 1;
bdrkreg_t i_rsvd : 47;
} ii_igfx0_fld_s;
} ii_igfx0_u_t;
#else
typedef union ii_igfx0_u {
bdrkreg_t ii_igfx0_regval;
struct {
bdrkreg_t i_rsvd : 47;
bdrkreg_t i_p_num : 1;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_n_num : 8;
bdrkreg_t i_pi_id : 1;
bdrkreg_t i_w_num : 4;
} ii_igfx0_fld_s;
} ii_igfx0_u_t;
#endif
/************************************************************************
* *
* There are two instances of this register. This register is used *
* for matching up the incoming responses from the graphics widget to *
* the processor that initiated the graphics operation. The *
* write-responses are converted to graphics credits and returned to *
* the processor so that the processor interface can manage the flow *
* control. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_igfx1_u {
bdrkreg_t ii_igfx1_regval;
struct {
bdrkreg_t i_w_num : 4;
bdrkreg_t i_pi_id : 1;
bdrkreg_t i_n_num : 8;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_p_num : 1;
bdrkreg_t i_rsvd : 47;
} ii_igfx1_fld_s;
} ii_igfx1_u_t;
#else
typedef union ii_igfx1_u {
bdrkreg_t ii_igfx1_regval;
struct {
bdrkreg_t i_rsvd : 47;
bdrkreg_t i_p_num : 1;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_n_num : 8;
bdrkreg_t i_pi_id : 1;
bdrkreg_t i_w_num : 4;
} ii_igfx1_fld_s;
} ii_igfx1_u_t;
#endif
/************************************************************************
* *
* There are two instances of this registers. These registers are *
* used as scratch registers for software use. *
* *
************************************************************************/
typedef union ii_iscr0_u {
bdrkreg_t ii_iscr0_regval;
struct {
bdrkreg_t i_scratch : 64;
} ii_iscr0_fld_s;
} ii_iscr0_u_t;
/************************************************************************
* *
* There are two instances of this registers. These registers are *
* used as scratch registers for software use. *
* *
************************************************************************/
typedef union ii_iscr1_u {
bdrkreg_t ii_iscr1_regval;
struct {
bdrkreg_t i_scratch : 64;
} ii_iscr1_fld_s;
} ii_iscr1_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte1_u {
bdrkreg_t ii_itte1_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte1_fld_s;
} ii_itte1_u_t;
#else
typedef union ii_itte1_u {
bdrkreg_t ii_itte1_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte1_fld_s;
} ii_itte1_u_t;
#endif
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte2_u {
bdrkreg_t ii_itte2_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte2_fld_s;
} ii_itte2_u_t;
#else
typedef union ii_itte2_u {
bdrkreg_t ii_itte2_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte2_fld_s;
} ii_itte2_u_t;
#endif
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte3_u {
bdrkreg_t ii_itte3_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte3_fld_s;
} ii_itte3_u_t;
#else
typedef union ii_itte3_u {
bdrkreg_t ii_itte3_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte3_fld_s;
} ii_itte3_u_t;
#endif
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte4_u {
bdrkreg_t ii_itte4_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte4_fld_s;
} ii_itte4_u_t;
#else
typedef union ii_itte4_u {
bdrkreg_t ii_itte4_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte4_fld_s;
} ii_itte4_u_t;
#endif
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte5_u {
bdrkreg_t ii_itte5_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte5_fld_s;
} ii_itte5_u_t;
#else
typedef union ii_itte5_u {
bdrkreg_t ii_itte5_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte5_fld_s;
} ii_itte5_u_t;
#endif
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte6_u {
bdrkreg_t ii_itte6_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte6_fld_s;
} ii_itte6_u_t;
#else
typedef union ii_itte6_u {
bdrkreg_t ii_itte6_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte6_fld_s;
} ii_itte6_u_t;
#endif
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Bedrock Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Bedrock is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Bedrock is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_itte7_u {
bdrkreg_t ii_itte7_regval;
struct {
bdrkreg_t i_offset : 5;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_rsvd : 51;
} ii_itte7_fld_s;
} ii_itte7_u_t;
#else
typedef union ii_itte7_u {
bdrkreg_t ii_itte7_regval;
struct {
bdrkreg_t i_rsvd : 51;
bdrkreg_t i_iosp : 1;
bdrkreg_t i_w_num : 4;
bdrkreg_t i_rsvd_1 : 3;
bdrkreg_t i_offset : 5;
} ii_itte7_fld_s;
} ii_itte7_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprb0_u {
bdrkreg_t ii_iprb0_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprb0_fld_s;
} ii_iprb0_u_t;
#else
typedef union ii_iprb0_u {
bdrkreg_t ii_iprb0_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprb0_fld_s;
} ii_iprb0_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprb8_u {
bdrkreg_t ii_iprb8_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprb8_fld_s;
} ii_iprb8_u_t;
#else
typedef union ii_iprb8_u {
bdrkreg_t ii_iprb8_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprb8_fld_s;
} ii_iprb8_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprb9_u {
bdrkreg_t ii_iprb9_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprb9_fld_s;
} ii_iprb9_u_t;
#else
typedef union ii_iprb9_u {
bdrkreg_t ii_iprb9_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprb9_fld_s;
} ii_iprb9_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprba_u {
bdrkreg_t ii_iprba_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprba_fld_s;
} ii_iprba_u_t;
#else
typedef union ii_iprba_u {
bdrkreg_t ii_iprba_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprba_fld_s;
} ii_iprba_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprbb_u {
bdrkreg_t ii_iprbb_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprbb_fld_s;
} ii_iprbb_u_t;
#else
typedef union ii_iprbb_u {
bdrkreg_t ii_iprbb_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprbb_fld_s;
} ii_iprbb_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprbc_u {
bdrkreg_t ii_iprbc_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprbc_fld_s;
} ii_iprbc_u_t;
#else
typedef union ii_iprbc_u {
bdrkreg_t ii_iprbc_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprbc_fld_s;
} ii_iprbc_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprbd_u {
bdrkreg_t ii_iprbd_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprbd_fld_s;
} ii_iprbd_u_t;
#else
typedef union ii_iprbd_u {
bdrkreg_t ii_iprbd_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprbd_fld_s;
} ii_iprbd_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprbe_u {
bdrkreg_t ii_iprbe_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprbe_fld_s;
} ii_iprbe_u_t;
#else
typedef union ii_iprbe_u {
bdrkreg_t ii_iprbe_regval;
struct {
bdrkreg_t i_mult_err : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_error : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_f : 1;
bdrkreg_t i_m : 2;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_na : 14;
bdrkreg_t i_c : 8;
} ii_iprbe_fld_s;
} ii_iprbe_u_t;
#endif
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Bedrock and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
#ifdef LITTLE_ENDIAN
typedef union ii_iprbf_u {
bdrkreg_t ii_iprbf_regval;
struct {
bdrkreg_t i_c : 8;
bdrkreg_t i_na : 14;
bdrkreg_t i_rsvd_2 : 2;
bdrkreg_t i_nb : 14;
bdrkreg_t i_rsvd_1 : 2;
bdrkreg_t i_m : 2;
bdrkreg_t i_f : 1;
bdrkreg_t i_of_cnt : 5;
bdrkreg_t i_error : 1;
bdrkreg_t i_rd_to : 1;
bdrkreg_t i_spur_wr : 1;
bdrkreg_t i_spur_rd : 1;
bdrkreg_t i_rsvd : 11;
bdrkreg_t i_mult_err : 1;
} ii_iprbe_fld_s;
} ii_iprbf_u_t;
#else
typedef union ii_iprbf_u {
bdrkreg_t ii_iprbf_regval;